2 * Interrupt handing routines for NEC VR4100 series.
4 * Copyright (C) 2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
23 #include <asm/irq_cpu.h>
24 #include <asm/system.h>
25 #include <asm/vr41xx/vr41xx.h>
27 typedef struct irq_cascade {
28 int (*get_irq)(unsigned int, struct pt_regs *);
31 static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned;
33 static struct irqaction cascade_irqaction = {
35 .mask = CPU_MASK_NONE,
39 int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *))
46 if (irq_cascade[irq].get_irq != NULL)
49 irq_cascade[irq].get_irq = get_irq;
51 if (get_irq != NULL) {
52 retval = setup_irq(irq, &cascade_irqaction);
54 irq_cascade[irq].get_irq = NULL;
60 EXPORT_SYMBOL_GPL(cascade_irq);
62 static void irq_dispatch(unsigned int irq, struct pt_regs *regs)
64 irq_cascade_t *cascade;
65 struct irq_desc *desc;
68 atomic_inc(&irq_err_count);
72 cascade = irq_cascade + irq;
73 if (cascade->get_irq != NULL) {
74 unsigned int source_irq = irq;
75 desc = irq_desc + source_irq;
76 desc->chip->ack(source_irq);
77 irq = cascade->get_irq(irq, regs);
79 atomic_inc(&irq_err_count);
81 irq_dispatch(irq, regs);
82 desc->chip->end(source_irq);
87 asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
89 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
91 if (pending & CAUSEF_IP7)
93 else if (pending & 0x7800) {
94 if (pending & CAUSEF_IP3)
95 irq_dispatch(3, regs);
96 else if (pending & CAUSEF_IP4)
97 irq_dispatch(4, regs);
98 else if (pending & CAUSEF_IP5)
99 irq_dispatch(5, regs);
100 else if (pending & CAUSEF_IP6)
101 irq_dispatch(6, regs);
102 } else if (pending & CAUSEF_IP2)
103 irq_dispatch(2, regs);
104 else if (pending & CAUSEF_IP0)
106 else if (pending & CAUSEF_IP1)
109 spurious_interrupt(regs);
112 void __init arch_init_irq(void)
114 mips_cpu_irq_init(MIPS_CPU_IRQ_BASE);