2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
36 #include "rt2x00pci.h"
37 #include "rt2400pci.h"
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
52 static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, ®);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
61 udelay(REGISTER_BUSY_DELAY);
67 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
68 const unsigned int word, const u8 value)
73 * Wait until the BBP becomes ready.
75 reg = rt2400pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
82 * Write the data into the BBP.
85 rt2x00_set_field32(®, BBPCSR_VALUE, value);
86 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1);
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
93 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
94 const unsigned int word, u8 *value)
99 * Wait until the BBP becomes ready.
101 reg = rt2400pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
108 * Write the request into the BBP.
111 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0);
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
118 * Wait until the BBP becomes ready.
120 reg = rt2400pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
130 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
131 const unsigned int word, const u32 value)
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, ®);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
143 udelay(REGISTER_BUSY_DELAY);
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
151 rt2x00_set_field32(®, RFCSR_VALUE, value);
152 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(®, RFCSR_BUSY, 1);
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
160 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
165 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
175 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
180 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
191 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
193 static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
194 const unsigned int word, u32 *data)
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
199 static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, u32 data)
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
205 static const struct rt2x00debug rt2400pci_rt2x00debug = {
206 .owner = THIS_MODULE,
208 .read = rt2400pci_read_csr,
209 .write = rt2400pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
220 .read = rt2400pci_bbp_read,
221 .write = rt2400pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
226 .read = rt2x00_rf_read,
227 .write = rt2400pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
234 #ifdef CONFIG_RT2X00_LIB_RFKILL
235 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
243 #define rt2400pci_rfkill_poll NULL
244 #endif /* CONFIG_RT2X00_LIB_RFKILL */
246 #ifdef CONFIG_RT2X00_LIB_LEDS
247 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
248 enum led_brightness brightness)
250 struct rt2x00_led *led =
251 container_of(led_cdev, struct rt2x00_led, led_dev);
252 unsigned int enabled = brightness != LED_OFF;
255 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®);
257 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
258 rt2x00_set_field32(®, LEDCSR_LINK, enabled);
259 else if (led->type == LED_TYPE_ACTIVITY)
260 rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled);
262 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
265 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
266 unsigned long *delay_on,
267 unsigned long *delay_off)
269 struct rt2x00_led *led =
270 container_of(led_cdev, struct rt2x00_led, led_dev);
273 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®);
274 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on);
275 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off);
276 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
281 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
282 struct rt2x00_led *led,
285 led->rt2x00dev = rt2x00dev;
287 led->led_dev.brightness_set = rt2400pci_brightness_set;
288 led->led_dev.blink_set = rt2400pci_blink_set;
289 led->flags = LED_INITIALIZED;
291 #endif /* CONFIG_RT2X00_LIB_LEDS */
294 * Configuration handlers.
296 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
297 const unsigned int filter_flags)
302 * Start configuration steps.
303 * Note that the version error will always be dropped
304 * since there is no filter for it at this time.
306 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
307 rt2x00_set_field32(®, RXCSR0_DROP_CRC,
308 !(filter_flags & FIF_FCSFAIL));
309 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL,
310 !(filter_flags & FIF_PLCPFAIL));
311 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL,
312 !(filter_flags & FIF_CONTROL));
313 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME,
314 !(filter_flags & FIF_PROMISC_IN_BSS));
315 rt2x00_set_field32(®, RXCSR0_DROP_TODS,
316 !(filter_flags & FIF_PROMISC_IN_BSS) &&
317 !rt2x00dev->intf_ap_count);
318 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1);
319 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
322 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
323 struct rt2x00_intf *intf,
324 struct rt2x00intf_conf *conf,
325 const unsigned int flags)
327 unsigned int bcn_preload;
330 if (flags & CONFIG_UPDATE_TYPE) {
332 * Enable beacon config
334 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
335 rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®);
336 rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload);
337 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
340 * Enable synchronisation.
342 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
343 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
344 rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync);
345 rt2x00_set_field32(®, CSR14_TBCN, 1);
346 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
349 if (flags & CONFIG_UPDATE_MAC)
350 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
351 conf->mac, sizeof(conf->mac));
353 if (flags & CONFIG_UPDATE_BSSID)
354 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
355 conf->bssid, sizeof(conf->bssid));
358 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
359 struct rt2x00lib_erp *erp)
365 * When short preamble is enabled, we should set bit 0x08
367 preamble_mask = erp->short_preamble << 3;
369 rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
370 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT,
372 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME,
373 erp->ack_consume_time);
374 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
376 rt2x00pci_register_read(rt2x00dev, ARCSR2, ®);
377 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00);
378 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
379 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
380 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
382 rt2x00pci_register_read(rt2x00dev, ARCSR3, ®);
383 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask);
384 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
385 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
386 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
388 rt2x00pci_register_read(rt2x00dev, ARCSR4, ®);
389 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask);
390 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
391 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
392 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
394 rt2x00pci_register_read(rt2x00dev, ARCSR5, ®);
395 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask);
396 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
397 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
398 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
401 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
402 const int basic_rate_mask)
404 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
407 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
408 struct rf_channel *rf)
411 * Switch on tuning bits.
413 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
414 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
416 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
417 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
418 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
421 * RF2420 chipset don't need any additional actions.
423 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
427 * For the RT2421 chipsets we need to write an invalid
428 * reference clock rate to activate auto_tune.
429 * After that we set the value back to the correct channel.
431 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
432 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
433 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
437 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
438 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
439 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
444 * Switch off tuning bits.
446 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
447 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
449 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
450 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
453 * Clear false CRC during channel switch.
455 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
458 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
460 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
463 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
464 struct antenna_setup *ant)
470 * We should never come here because rt2x00lib is supposed
471 * to catch this and send us the correct antenna explicitely.
473 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
474 ant->tx == ANTENNA_SW_DIVERSITY);
476 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
477 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
480 * Configure the TX antenna.
483 case ANTENNA_HW_DIVERSITY:
484 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
487 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
491 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
496 * Configure the RX antenna.
499 case ANTENNA_HW_DIVERSITY:
500 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
503 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
507 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
511 rt2400pci_bbp_write(rt2x00dev, 4, r4);
512 rt2400pci_bbp_write(rt2x00dev, 1, r1);
515 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
516 struct rt2x00lib_conf *libconf)
520 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
521 rt2x00_set_field32(®, CSR11_SLOT_TIME, libconf->slot_time);
522 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
524 rt2x00pci_register_read(rt2x00dev, CSR18, ®);
525 rt2x00_set_field32(®, CSR18_SIFS, libconf->sifs);
526 rt2x00_set_field32(®, CSR18_PIFS, libconf->pifs);
527 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
529 rt2x00pci_register_read(rt2x00dev, CSR19, ®);
530 rt2x00_set_field32(®, CSR19_DIFS, libconf->difs);
531 rt2x00_set_field32(®, CSR19_EIFS, libconf->eifs);
532 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
534 rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
535 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
536 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1);
537 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
539 rt2x00pci_register_read(rt2x00dev, CSR12, ®);
540 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL,
541 libconf->conf->beacon_int * 16);
542 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION,
543 libconf->conf->beacon_int * 16);
544 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
547 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
548 struct rt2x00lib_conf *libconf,
549 const unsigned int flags)
551 if (flags & CONFIG_UPDATE_PHYMODE)
552 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
553 if (flags & CONFIG_UPDATE_CHANNEL)
554 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
555 if (flags & CONFIG_UPDATE_TXPOWER)
556 rt2400pci_config_txpower(rt2x00dev,
557 libconf->conf->power_level);
558 if (flags & CONFIG_UPDATE_ANTENNA)
559 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
560 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
561 rt2400pci_config_duration(rt2x00dev, libconf);
564 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
565 const int cw_min, const int cw_max)
569 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
570 rt2x00_set_field32(®, CSR11_CWMIN, cw_min);
571 rt2x00_set_field32(®, CSR11_CWMAX, cw_max);
572 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
578 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
579 struct link_qual *qual)
585 * Update FCS error count from register.
587 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
588 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
591 * Update False CCA count from register.
593 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
594 qual->false_cca = bbp;
597 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
599 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
600 rt2x00dev->link.vgc_level = 0x08;
603 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
608 * The link tuner should not run longer then 60 seconds,
609 * and should run once every 2 seconds.
611 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
615 * Base r13 link tuning on the false cca count.
617 rt2400pci_bbp_read(rt2x00dev, 13, ®);
619 if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
620 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
621 rt2x00dev->link.vgc_level = reg;
622 } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
623 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
624 rt2x00dev->link.vgc_level = reg;
629 * Initialization functions.
631 static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
632 struct queue_entry *entry)
634 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
635 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
638 rt2x00_desc_read(entry_priv->desc, 2, &word);
639 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
640 rt2x00_desc_write(entry_priv->desc, 2, word);
642 rt2x00_desc_read(entry_priv->desc, 1, &word);
643 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
644 rt2x00_desc_write(entry_priv->desc, 1, word);
646 rt2x00_desc_read(entry_priv->desc, 0, &word);
647 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
648 rt2x00_desc_write(entry_priv->desc, 0, word);
651 static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
652 struct queue_entry *entry)
654 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
657 rt2x00_desc_read(entry_priv->desc, 0, &word);
658 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
659 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
660 rt2x00_desc_write(entry_priv->desc, 0, word);
663 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
665 struct queue_entry_priv_pci *entry_priv;
669 * Initialize registers.
671 rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
672 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
673 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
674 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
675 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
676 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
678 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
679 rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
680 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
681 entry_priv->desc_dma);
682 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
684 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
685 rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
686 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
687 entry_priv->desc_dma);
688 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
690 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
691 rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
692 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
693 entry_priv->desc_dma);
694 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
696 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
697 rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
698 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
699 entry_priv->desc_dma);
700 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
702 rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
703 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
704 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
705 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
707 entry_priv = rt2x00dev->rx->entries[0].priv_data;
708 rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
709 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER,
710 entry_priv->desc_dma);
711 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
716 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
720 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
721 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
722 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
723 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
725 rt2x00pci_register_read(rt2x00dev, TIMECSR, ®);
726 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33);
727 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63);
728 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0);
729 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
731 rt2x00pci_register_read(rt2x00dev, CSR9, ®);
732 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT,
733 (rt2x00dev->rx->data_size / 128));
734 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
736 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
737 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
738 rt2x00_set_field32(®, CSR14_TSF_SYNC, 0);
739 rt2x00_set_field32(®, CSR14_TBCN, 0);
740 rt2x00_set_field32(®, CSR14_TCFP, 0);
741 rt2x00_set_field32(®, CSR14_TATIMW, 0);
742 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
743 rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0);
744 rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0);
745 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
747 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
749 rt2x00pci_register_read(rt2x00dev, ARCSR0, ®);
750 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA0, 133);
751 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID0, 134);
752 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA1, 136);
753 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID1, 135);
754 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
756 rt2x00pci_register_read(rt2x00dev, RXCSR3, ®);
757 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 3); /* Tx power.*/
758 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1);
759 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 32); /* Signal */
760 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1);
761 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 36); /* Rssi */
762 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1);
763 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
765 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
767 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
770 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
771 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
773 rt2x00pci_register_read(rt2x00dev, MACCSR2, ®);
774 rt2x00_set_field32(®, MACCSR2_DELAY, 64);
775 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
777 rt2x00pci_register_read(rt2x00dev, RALINKCSR, ®);
778 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17);
779 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 154);
780 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0);
781 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 154);
782 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
784 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
785 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1);
786 rt2x00_set_field32(®, CSR1_BBP_RESET, 0);
787 rt2x00_set_field32(®, CSR1_HOST_READY, 0);
788 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
790 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
791 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0);
792 rt2x00_set_field32(®, CSR1_HOST_READY, 1);
793 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
796 * We must clear the FCS and FIFO error count.
797 * These registers are cleared on read,
798 * so we may pass a useless variable to store the value.
800 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
801 rt2x00pci_register_read(rt2x00dev, CNT4, ®);
806 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
811 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
812 rt2400pci_bbp_read(rt2x00dev, 0, &value);
813 if ((value != 0xff) && (value != 0x00))
815 udelay(REGISTER_BUSY_DELAY);
818 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
822 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
829 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
832 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
833 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
834 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
835 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
836 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
837 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
838 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
839 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
840 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
841 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
842 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
843 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
844 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
845 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
847 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
848 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
850 if (eeprom != 0xffff && eeprom != 0x0000) {
851 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
852 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
853 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
861 * Device state switch handlers.
863 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
864 enum dev_state state)
868 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
869 rt2x00_set_field32(®, RXCSR0_DISABLE_RX,
870 (state == STATE_RADIO_RX_OFF) ||
871 (state == STATE_RADIO_RX_OFF_LINK));
872 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
875 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
876 enum dev_state state)
878 int mask = (state == STATE_RADIO_IRQ_OFF);
882 * When interrupts are being enabled, the interrupt registers
883 * should clear the register to assure a clean state.
885 if (state == STATE_RADIO_IRQ_ON) {
886 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
887 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
891 * Only toggle the interrupts bits we are going to use.
892 * Non-checked interrupt bits are disabled by default.
894 rt2x00pci_register_read(rt2x00dev, CSR8, ®);
895 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask);
896 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask);
897 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask);
898 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask);
899 rt2x00_set_field32(®, CSR8_RXDONE, mask);
900 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
903 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
906 * Initialize all registers.
908 if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
909 rt2400pci_init_registers(rt2x00dev) ||
910 rt2400pci_init_bbp(rt2x00dev)))
916 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
920 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
923 * Disable synchronisation.
925 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
930 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
931 rt2x00_set_field32(®, TXCSR0_ABORT, 1);
932 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
935 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
936 enum dev_state state)
944 put_to_sleep = (state != STATE_AWAKE);
946 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
947 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1);
948 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state);
949 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state);
950 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
951 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
954 * Device is not guaranteed to be in the requested state yet.
955 * We must wait until the register indicates that the
956 * device has entered the correct state.
958 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
959 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
960 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
961 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
962 if (bbp_state == state && rf_state == state)
970 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
971 enum dev_state state)
977 retval = rt2400pci_enable_radio(rt2x00dev);
979 case STATE_RADIO_OFF:
980 rt2400pci_disable_radio(rt2x00dev);
982 case STATE_RADIO_RX_ON:
983 case STATE_RADIO_RX_ON_LINK:
984 case STATE_RADIO_RX_OFF:
985 case STATE_RADIO_RX_OFF_LINK:
986 rt2400pci_toggle_rx(rt2x00dev, state);
988 case STATE_RADIO_IRQ_ON:
989 case STATE_RADIO_IRQ_OFF:
990 rt2400pci_toggle_irq(rt2x00dev, state);
992 case STATE_DEEP_SLEEP:
996 retval = rt2400pci_set_state(rt2x00dev, state);
1003 if (unlikely(retval))
1004 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1011 * TX descriptor initialization
1013 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1014 struct sk_buff *skb,
1015 struct txentry_desc *txdesc)
1017 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1018 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1019 __le32 *txd = skbdesc->desc;
1023 * Start writing the descriptor words.
1025 rt2x00_desc_read(entry_priv->desc, 1, &word);
1026 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1027 rt2x00_desc_write(entry_priv->desc, 1, word);
1029 rt2x00_desc_read(txd, 2, &word);
1030 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skb->len);
1031 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skb->len);
1032 rt2x00_desc_write(txd, 2, word);
1034 rt2x00_desc_read(txd, 3, &word);
1035 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1036 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1037 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1038 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1039 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1040 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1041 rt2x00_desc_write(txd, 3, word);
1043 rt2x00_desc_read(txd, 4, &word);
1044 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1045 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1046 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1047 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1048 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1049 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1050 rt2x00_desc_write(txd, 4, word);
1052 rt2x00_desc_read(txd, 0, &word);
1053 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1054 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1055 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1056 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1057 rt2x00_set_field32(&word, TXD_W0_ACK,
1058 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1059 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1060 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1061 rt2x00_set_field32(&word, TXD_W0_RTS,
1062 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1063 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1064 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1065 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1066 rt2x00_desc_write(txd, 0, word);
1070 * TX data initialization
1072 static void rt2400pci_write_beacon(struct queue_entry *entry)
1074 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1075 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1076 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1081 * Disable beaconing while we are reloading the beacon data,
1082 * otherwise we might be sending out invalid data.
1084 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
1085 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
1086 rt2x00_set_field32(®, CSR14_TBCN, 0);
1087 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
1088 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1091 * Replace rt2x00lib allocated descriptor with the
1092 * pointer to the _real_ hardware descriptor.
1093 * After that, map the beacon to DMA and update the
1096 memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1097 skbdesc->desc = entry_priv->desc;
1099 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1101 rt2x00_desc_read(entry_priv->desc, 1, &word);
1102 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1103 rt2x00_desc_write(entry_priv->desc, 1, word);
1106 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1107 const enum data_queue_qid queue)
1111 if (queue == QID_BEACON) {
1112 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
1113 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1114 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
1115 rt2x00_set_field32(®, CSR14_TBCN, 1);
1116 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
1117 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1122 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
1123 rt2x00_set_field32(®, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1124 rt2x00_set_field32(®, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1125 rt2x00_set_field32(®, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1126 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1130 * RX control handlers
1132 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1133 struct rxdone_entry_desc *rxdesc)
1135 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1136 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1145 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1146 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1147 rt2x00_desc_read(entry_priv->desc, 3, &word3);
1148 rt2x00_desc_read(entry_priv->desc, 4, &word4);
1150 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1151 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1152 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1153 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1156 * We only get the lower 32bits from the timestamp,
1157 * to get the full 64bits we must complement it with
1158 * the timestamp from get_tsf().
1159 * Note that when a wraparound of the lower 32bits
1160 * has occurred between the frame arrival and the get_tsf()
1161 * call, we must decrease the higher 32bits with 1 to get
1164 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1165 rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1166 rx_high = upper_32_bits(tsf);
1168 if ((u32)tsf <= rx_low)
1172 * Obtain the status about this packet.
1173 * The signal is the PLCP value, and needs to be stripped
1174 * of the preamble bit (0x08).
1176 rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1177 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1178 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1179 entry->queue->rt2x00dev->rssi_offset;
1180 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1182 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1183 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1184 rxdesc->dev_flags |= RXDONE_MY_BSS;
1188 * Interrupt functions.
1190 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1191 const enum data_queue_qid queue_idx)
1193 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1194 struct queue_entry_priv_pci *entry_priv;
1195 struct queue_entry *entry;
1196 struct txdone_entry_desc txdesc;
1199 while (!rt2x00queue_empty(queue)) {
1200 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1201 entry_priv = entry->priv_data;
1202 rt2x00_desc_read(entry_priv->desc, 0, &word);
1204 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1205 !rt2x00_get_field32(word, TXD_W0_VALID))
1209 * Obtain the status about this packet.
1212 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1213 case 0: /* Success */
1214 case 1: /* Success with retry */
1215 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1217 case 2: /* Failure, excessive retries */
1218 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1219 /* Don't break, this is a failed frame! */
1220 default: /* Failure */
1221 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1223 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1225 rt2x00lib_txdone(entry, &txdesc);
1229 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1231 struct rt2x00_dev *rt2x00dev = dev_instance;
1235 * Get the interrupt sources & saved to local variable.
1236 * Write register value back to clear pending interrupts.
1238 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
1239 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1244 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1248 * Handle interrupts, walk through all bits
1249 * and run the tasks, the bits are checked in order of
1254 * 1 - Beacon timer expired interrupt.
1256 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1257 rt2x00lib_beacondone(rt2x00dev);
1260 * 2 - Rx ring done interrupt.
1262 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1263 rt2x00pci_rxdone(rt2x00dev);
1266 * 3 - Atim ring transmit done interrupt.
1268 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1269 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1272 * 4 - Priority ring transmit done interrupt.
1274 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1275 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
1278 * 5 - Tx ring transmit done interrupt.
1280 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1281 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1287 * Device probe functions.
1289 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1291 struct eeprom_93cx6 eeprom;
1296 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
1298 eeprom.data = rt2x00dev;
1299 eeprom.register_read = rt2400pci_eepromregister_read;
1300 eeprom.register_write = rt2400pci_eepromregister_write;
1301 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1302 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1303 eeprom.reg_data_in = 0;
1304 eeprom.reg_data_out = 0;
1305 eeprom.reg_data_clock = 0;
1306 eeprom.reg_chip_select = 0;
1308 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1309 EEPROM_SIZE / sizeof(u16));
1312 * Start validation of the data that has been read.
1314 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1315 if (!is_valid_ether_addr(mac)) {
1316 DECLARE_MAC_BUF(macbuf);
1318 random_ether_addr(mac);
1319 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1322 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1323 if (word == 0xffff) {
1324 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1331 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1338 * Read EEPROM word for configuration.
1340 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1343 * Identify RF chipset.
1345 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1346 rt2x00pci_register_read(rt2x00dev, CSR0, ®);
1347 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1349 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1350 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1351 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1356 * Identify default antenna configuration.
1358 rt2x00dev->default_ant.tx =
1359 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1360 rt2x00dev->default_ant.rx =
1361 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1364 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1365 * I am not 100% sure about this, but the legacy drivers do not
1366 * indicate antenna swapping in software is required when
1367 * diversity is enabled.
1369 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1370 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1371 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1372 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1375 * Store led mode, for correct led behaviour.
1377 #ifdef CONFIG_RT2X00_LIB_LEDS
1378 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1380 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1381 if (value == LED_MODE_TXRX_ACTIVITY)
1382 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1384 #endif /* CONFIG_RT2X00_LIB_LEDS */
1387 * Detect if this device has an hardware controlled radio.
1389 #ifdef CONFIG_RT2X00_LIB_RFKILL
1390 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1391 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1392 #endif /* CONFIG_RT2X00_LIB_RFKILL */
1395 * Check if the BBP tuning should be enabled.
1397 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1398 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1404 * RF value list for RF2420 & RF2421
1407 static const struct rf_channel rf_vals_b[] = {
1408 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1409 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1410 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1411 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1412 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1413 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1414 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1415 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1416 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1417 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1418 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1419 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1420 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1421 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1424 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1426 struct hw_mode_spec *spec = &rt2x00dev->spec;
1427 struct channel_info *info;
1432 * Initialize all hw fields.
1434 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1435 IEEE80211_HW_SIGNAL_DBM;
1436 rt2x00dev->hw->extra_tx_headroom = 0;
1438 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1439 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1440 rt2x00_eeprom_addr(rt2x00dev,
1441 EEPROM_MAC_ADDR_0));
1444 * Initialize hw_mode information.
1446 spec->supported_bands = SUPPORT_BAND_2GHZ;
1447 spec->supported_rates = SUPPORT_RATE_CCK;
1449 spec->num_channels = ARRAY_SIZE(rf_vals_b);
1450 spec->channels = rf_vals_b;
1453 * Create channel information array
1455 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1459 spec->channels_info = info;
1461 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1462 for (i = 0; i < 14; i++)
1463 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1468 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1473 * Allocate eeprom data.
1475 retval = rt2400pci_validate_eeprom(rt2x00dev);
1479 retval = rt2400pci_init_eeprom(rt2x00dev);
1484 * Initialize hw specifications.
1486 retval = rt2400pci_probe_hw_mode(rt2x00dev);
1491 * This device requires the atim queue and DMA-mapped skbs.
1493 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1494 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1497 * Set the rssi offset.
1499 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1505 * IEEE80211 stack callback functions.
1507 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1508 u32 short_retry, u32 long_retry)
1510 struct rt2x00_dev *rt2x00dev = hw->priv;
1513 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
1514 rt2x00_set_field32(®, CSR11_LONG_RETRY, long_retry);
1515 rt2x00_set_field32(®, CSR11_SHORT_RETRY, short_retry);
1516 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1521 static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1522 const struct ieee80211_tx_queue_params *params)
1524 struct rt2x00_dev *rt2x00dev = hw->priv;
1527 * We don't support variating cw_min and cw_max variables
1528 * per queue. So by default we only configure the TX queue,
1529 * and ignore all other configurations.
1534 if (rt2x00mac_conf_tx(hw, queue, params))
1538 * Write configuration to register.
1540 rt2400pci_config_cw(rt2x00dev,
1541 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1546 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1548 struct rt2x00_dev *rt2x00dev = hw->priv;
1552 rt2x00pci_register_read(rt2x00dev, CSR17, ®);
1553 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1554 rt2x00pci_register_read(rt2x00dev, CSR16, ®);
1555 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1560 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1562 struct rt2x00_dev *rt2x00dev = hw->priv;
1565 rt2x00pci_register_read(rt2x00dev, CSR15, ®);
1566 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1569 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1571 .start = rt2x00mac_start,
1572 .stop = rt2x00mac_stop,
1573 .add_interface = rt2x00mac_add_interface,
1574 .remove_interface = rt2x00mac_remove_interface,
1575 .config = rt2x00mac_config,
1576 .config_interface = rt2x00mac_config_interface,
1577 .configure_filter = rt2x00mac_configure_filter,
1578 .get_stats = rt2x00mac_get_stats,
1579 .set_retry_limit = rt2400pci_set_retry_limit,
1580 .bss_info_changed = rt2x00mac_bss_info_changed,
1581 .conf_tx = rt2400pci_conf_tx,
1582 .get_tx_stats = rt2x00mac_get_tx_stats,
1583 .get_tsf = rt2400pci_get_tsf,
1584 .tx_last_beacon = rt2400pci_tx_last_beacon,
1587 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1588 .irq_handler = rt2400pci_interrupt,
1589 .probe_hw = rt2400pci_probe_hw,
1590 .initialize = rt2x00pci_initialize,
1591 .uninitialize = rt2x00pci_uninitialize,
1592 .init_rxentry = rt2400pci_init_rxentry,
1593 .init_txentry = rt2400pci_init_txentry,
1594 .set_device_state = rt2400pci_set_device_state,
1595 .rfkill_poll = rt2400pci_rfkill_poll,
1596 .link_stats = rt2400pci_link_stats,
1597 .reset_tuner = rt2400pci_reset_tuner,
1598 .link_tuner = rt2400pci_link_tuner,
1599 .write_tx_desc = rt2400pci_write_tx_desc,
1600 .write_tx_data = rt2x00pci_write_tx_data,
1601 .write_beacon = rt2400pci_write_beacon,
1602 .kick_tx_queue = rt2400pci_kick_tx_queue,
1603 .fill_rxdone = rt2400pci_fill_rxdone,
1604 .config_filter = rt2400pci_config_filter,
1605 .config_intf = rt2400pci_config_intf,
1606 .config_erp = rt2400pci_config_erp,
1607 .config = rt2400pci_config,
1610 static const struct data_queue_desc rt2400pci_queue_rx = {
1611 .entry_num = RX_ENTRIES,
1612 .data_size = DATA_FRAME_SIZE,
1613 .desc_size = RXD_DESC_SIZE,
1614 .priv_size = sizeof(struct queue_entry_priv_pci),
1617 static const struct data_queue_desc rt2400pci_queue_tx = {
1618 .entry_num = TX_ENTRIES,
1619 .data_size = DATA_FRAME_SIZE,
1620 .desc_size = TXD_DESC_SIZE,
1621 .priv_size = sizeof(struct queue_entry_priv_pci),
1624 static const struct data_queue_desc rt2400pci_queue_bcn = {
1625 .entry_num = BEACON_ENTRIES,
1626 .data_size = MGMT_FRAME_SIZE,
1627 .desc_size = TXD_DESC_SIZE,
1628 .priv_size = sizeof(struct queue_entry_priv_pci),
1631 static const struct data_queue_desc rt2400pci_queue_atim = {
1632 .entry_num = ATIM_ENTRIES,
1633 .data_size = DATA_FRAME_SIZE,
1634 .desc_size = TXD_DESC_SIZE,
1635 .priv_size = sizeof(struct queue_entry_priv_pci),
1638 static const struct rt2x00_ops rt2400pci_ops = {
1639 .name = KBUILD_MODNAME,
1642 .eeprom_size = EEPROM_SIZE,
1644 .tx_queues = NUM_TX_QUEUES,
1645 .rx = &rt2400pci_queue_rx,
1646 .tx = &rt2400pci_queue_tx,
1647 .bcn = &rt2400pci_queue_bcn,
1648 .atim = &rt2400pci_queue_atim,
1649 .lib = &rt2400pci_rt2x00_ops,
1650 .hw = &rt2400pci_mac80211_ops,
1651 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1652 .debugfs = &rt2400pci_rt2x00debug,
1653 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1657 * RT2400pci module information.
1659 static struct pci_device_id rt2400pci_device_table[] = {
1660 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1664 MODULE_AUTHOR(DRV_PROJECT);
1665 MODULE_VERSION(DRV_VERSION);
1666 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1667 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1668 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1669 MODULE_LICENSE("GPL");
1671 static struct pci_driver rt2400pci_driver = {
1672 .name = KBUILD_MODNAME,
1673 .id_table = rt2400pci_device_table,
1674 .probe = rt2x00pci_probe,
1675 .remove = __devexit_p(rt2x00pci_remove),
1676 .suspend = rt2x00pci_suspend,
1677 .resume = rt2x00pci_resume,
1680 static int __init rt2400pci_init(void)
1682 return pci_register_driver(&rt2400pci_driver);
1685 static void __exit rt2400pci_exit(void)
1687 pci_unregister_driver(&rt2400pci_driver);
1690 module_init(rt2400pci_init);
1691 module_exit(rt2400pci_exit);