2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/cpu.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
30 #include <linux/module.h>
31 #include <linux/dmi.h>
32 #include <linux/dmar.h>
34 #include <asm/atomic.h>
37 #include <asm/mpspec.h>
39 #include <asm/arch_hooks.h>
41 #include <asm/pgalloc.h>
42 #include <asm/i8253.h>
45 #include <asm/proto.h>
46 #include <asm/timex.h>
48 #include <asm/i8259.h>
50 #include <mach_apic.h>
51 #include <mach_apicdef.h>
57 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
58 # error SPURIOUS_APIC_VECTOR definition error
63 * Knob to control our willingness to enable the local APIC.
67 static int force_enable_local_apic;
69 * APIC command line parameters
71 static int __init parse_lapic(char *arg)
73 force_enable_local_apic = 1;
76 early_param("lapic", parse_lapic);
77 /* Local APIC was disabled by the BIOS and enabled by the kernel */
78 static int enabled_via_apicbase;
83 static int apic_calibrate_pmtmr __initdata;
84 static __init int setup_apicpmtimer(char *s)
86 apic_calibrate_pmtmr = 1;
90 __setup("apicpmtimer", setup_apicpmtimer);
99 /* x2apic enabled before OS handover */
100 int x2apic_preenabled;
102 static __init int setup_nox2apic(char *str)
105 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
108 early_param("nox2apic", setup_nox2apic);
111 unsigned long mp_lapic_addr;
113 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
114 static int disable_apic_timer __cpuinitdata;
115 /* Local APIC timer works in C2 */
116 int local_apic_timer_c2_ok;
117 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
119 int first_system_vector = 0xfe;
121 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
124 * Debug level, exported for io_apic.c
126 unsigned int apic_verbosity;
130 /* Have we found an MP table */
131 int smp_found_config;
133 static struct resource lapic_resource = {
134 .name = "Local APIC",
135 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
138 static unsigned int calibration_result;
140 static int lapic_next_event(unsigned long delta,
141 struct clock_event_device *evt);
142 static void lapic_timer_setup(enum clock_event_mode mode,
143 struct clock_event_device *evt);
144 static void lapic_timer_broadcast(cpumask_t mask);
145 static void apic_pm_activate(void);
148 * The local apic timer can be used for any function which is CPU local.
150 static struct clock_event_device lapic_clockevent = {
152 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
153 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
155 .set_mode = lapic_timer_setup,
156 .set_next_event = lapic_next_event,
157 .broadcast = lapic_timer_broadcast,
161 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
163 static unsigned long apic_phys;
166 * Get the LAPIC version
168 static inline int lapic_get_version(void)
170 return GET_APIC_VERSION(apic_read(APIC_LVR));
174 * Check, if the APIC is integrated or a separate chip
176 static inline int lapic_is_integrated(void)
181 return APIC_INTEGRATED(lapic_get_version());
186 * Check, whether this is a modern or a first generation APIC
188 static int modern_apic(void)
190 /* AMD systems use old APIC versions, so check the CPU */
191 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
192 boot_cpu_data.x86 >= 0xf)
194 return lapic_get_version() >= 0x14;
198 * Paravirt kernels also might be using these below ops. So we still
199 * use generic apic_read()/apic_write(), which might be pointing to different
200 * ops in PARAVIRT case.
202 void xapic_wait_icr_idle(void)
204 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
208 u32 safe_xapic_wait_icr_idle(void)
215 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
219 } while (timeout++ < 1000);
224 void xapic_icr_write(u32 low, u32 id)
226 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
227 apic_write(APIC_ICR, low);
230 u64 xapic_icr_read(void)
234 icr2 = apic_read(APIC_ICR2);
235 icr1 = apic_read(APIC_ICR);
237 return icr1 | ((u64)icr2 << 32);
240 static struct apic_ops xapic_ops = {
241 .read = native_apic_mem_read,
242 .write = native_apic_mem_write,
243 .icr_read = xapic_icr_read,
244 .icr_write = xapic_icr_write,
245 .wait_icr_idle = xapic_wait_icr_idle,
246 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
249 struct apic_ops __read_mostly *apic_ops = &xapic_ops;
250 EXPORT_SYMBOL_GPL(apic_ops);
253 static void x2apic_wait_icr_idle(void)
255 /* no need to wait for icr idle in x2apic */
259 static u32 safe_x2apic_wait_icr_idle(void)
261 /* no need to wait for icr idle in x2apic */
265 void x2apic_icr_write(u32 low, u32 id)
267 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
270 u64 x2apic_icr_read(void)
274 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
278 static struct apic_ops x2apic_ops = {
279 .read = native_apic_msr_read,
280 .write = native_apic_msr_write,
281 .icr_read = x2apic_icr_read,
282 .icr_write = x2apic_icr_write,
283 .wait_icr_idle = x2apic_wait_icr_idle,
284 .safe_wait_icr_idle = safe_x2apic_wait_icr_idle,
289 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
291 void __cpuinit enable_NMI_through_LVT0(void)
295 /* unmask and set to NMI */
298 /* Level triggered for 82489DX (32bit mode) */
299 if (!lapic_is_integrated())
300 v |= APIC_LVT_LEVEL_TRIGGER;
302 apic_write(APIC_LVT0, v);
307 * get_physical_broadcast - Get number of physical broadcast IDs
309 int get_physical_broadcast(void)
311 return modern_apic() ? 0xff : 0xf;
316 * lapic_get_maxlvt - get the maximum number of local vector table entries
318 int lapic_get_maxlvt(void)
322 v = apic_read(APIC_LVR);
324 * - we always have APIC integrated on 64bit mode
325 * - 82489DXs do not report # of LVT entries
327 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
336 #define APIC_DIVISOR 1
338 #define APIC_DIVISOR 16
342 * This function sets up the local APIC timer, with a timeout of
343 * 'clocks' APIC bus clock. During calibration we actually call
344 * this function twice on the boot CPU, once with a bogus timeout
345 * value, second time for real. The other (noncalibrating) CPUs
346 * call this function only once, with the real, calibrated value.
348 * We do reads before writes even if unnecessary, to get around the
349 * P5 APIC double write bug.
351 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
353 unsigned int lvtt_value, tmp_value;
355 lvtt_value = LOCAL_TIMER_VECTOR;
357 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
358 if (!lapic_is_integrated())
359 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
362 lvtt_value |= APIC_LVT_MASKED;
364 apic_write(APIC_LVTT, lvtt_value);
369 tmp_value = apic_read(APIC_TDCR);
370 apic_write(APIC_TDCR,
371 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
375 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
379 * Setup extended LVT, AMD specific (K8, family 10h)
381 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
382 * MCE interrupts are supported. Thus MCE offset must be set to 0.
384 * If mask=1, the LVT entry does not generate interrupts while mask=0
385 * enables the vector. See also the BKDGs.
388 #define APIC_EILVT_LVTOFF_MCE 0
389 #define APIC_EILVT_LVTOFF_IBS 1
391 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
393 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
394 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
399 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
401 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
402 return APIC_EILVT_LVTOFF_MCE;
405 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
407 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
408 return APIC_EILVT_LVTOFF_IBS;
410 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
413 * Program the next event, relative to now
415 static int lapic_next_event(unsigned long delta,
416 struct clock_event_device *evt)
418 apic_write(APIC_TMICT, delta);
423 * Setup the lapic timer in periodic or oneshot mode
425 static void lapic_timer_setup(enum clock_event_mode mode,
426 struct clock_event_device *evt)
431 /* Lapic used as dummy for broadcast ? */
432 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
435 local_irq_save(flags);
438 case CLOCK_EVT_MODE_PERIODIC:
439 case CLOCK_EVT_MODE_ONESHOT:
440 __setup_APIC_LVTT(calibration_result,
441 mode != CLOCK_EVT_MODE_PERIODIC, 1);
443 case CLOCK_EVT_MODE_UNUSED:
444 case CLOCK_EVT_MODE_SHUTDOWN:
445 v = apic_read(APIC_LVTT);
446 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
447 apic_write(APIC_LVTT, v);
449 case CLOCK_EVT_MODE_RESUME:
450 /* Nothing to do here */
454 local_irq_restore(flags);
458 * Local APIC timer broadcast function
460 static void lapic_timer_broadcast(cpumask_t mask)
463 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
468 * Setup the local APIC timer for this CPU. Copy the initilized values
469 * of the boot CPU and register the clock event in the framework.
471 static void __cpuinit setup_APIC_timer(void)
473 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
475 memcpy(levt, &lapic_clockevent, sizeof(*levt));
476 levt->cpumask = cpumask_of_cpu(smp_processor_id());
478 clockevents_register_device(levt);
482 * In this functions we calibrate APIC bus clocks to the external timer.
484 * We want to do the calibration only once since we want to have local timer
485 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
488 * This was previously done by reading the PIT/HPET and waiting for a wrap
489 * around to find out, that a tick has elapsed. I have a box, where the PIT
490 * readout is broken, so it never gets out of the wait loop again. This was
491 * also reported by others.
493 * Monitoring the jiffies value is inaccurate and the clockevents
494 * infrastructure allows us to do a simple substitution of the interrupt
497 * The calibration routine also uses the pm_timer when possible, as the PIT
498 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
499 * back to normal later in the boot process).
502 #define LAPIC_CAL_LOOPS (HZ/10)
504 static __initdata int lapic_cal_loops = -1;
505 static __initdata long lapic_cal_t1, lapic_cal_t2;
506 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
507 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
508 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
511 * Temporary interrupt handler.
513 static void __init lapic_cal_handler(struct clock_event_device *dev)
515 unsigned long long tsc = 0;
516 long tapic = apic_read(APIC_TMCCT);
517 unsigned long pm = acpi_pm_read_early();
522 switch (lapic_cal_loops++) {
524 lapic_cal_t1 = tapic;
525 lapic_cal_tsc1 = tsc;
527 lapic_cal_j1 = jiffies;
530 case LAPIC_CAL_LOOPS:
531 lapic_cal_t2 = tapic;
532 lapic_cal_tsc2 = tsc;
533 if (pm < lapic_cal_pm1)
534 pm += ACPI_PM_OVRRUN;
536 lapic_cal_j2 = jiffies;
541 static int __init calibrate_by_pmtimer(long deltapm, long *delta)
543 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
544 const long pm_thresh = pm_100ms / 100;
548 #ifndef CONFIG_X86_PM_TIMER
552 apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
554 /* Check, if the PM timer is available */
558 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
560 if (deltapm > (pm_100ms - pm_thresh) &&
561 deltapm < (pm_100ms + pm_thresh)) {
562 apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
564 res = (((u64)deltapm) * mult) >> 22;
565 do_div(res, 1000000);
566 printk(KERN_WARNING "APIC calibration not consistent "
567 "with PM Timer: %ldms instead of 100ms\n",
569 /* Correct the lapic counter value */
570 res = (((u64)(*delta)) * pm_100ms);
571 do_div(res, deltapm);
572 printk(KERN_INFO "APIC delta adjusted to PM-Timer: "
573 "%lu (%ld)\n", (unsigned long)res, *delta);
580 static int __init calibrate_APIC_clock(void)
582 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
583 void (*real_handler)(struct clock_event_device *dev);
584 unsigned long deltaj;
586 int pm_referenced = 0;
590 /* Replace the global interrupt handler */
591 real_handler = global_clock_event->event_handler;
592 global_clock_event->event_handler = lapic_cal_handler;
595 * Setup the APIC counter to 1e9. There is no way the lapic
596 * can underflow in the 100ms detection time frame
598 __setup_APIC_LVTT(1000000000, 0, 0);
600 /* Let the interrupts run */
603 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
608 /* Restore the real event handler */
609 global_clock_event->event_handler = real_handler;
611 /* Build delta t1-t2 as apic timer counts down */
612 delta = lapic_cal_t1 - lapic_cal_t2;
613 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
615 /* we trust the PM based calibration if possible */
616 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
619 /* Calculate the scaled math multiplication factor */
620 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
621 lapic_clockevent.shift);
622 lapic_clockevent.max_delta_ns =
623 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
624 lapic_clockevent.min_delta_ns =
625 clockevent_delta2ns(0xF, &lapic_clockevent);
627 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
629 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
630 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
631 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
635 delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
636 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
638 (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
639 (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
642 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
644 calibration_result / (1000000 / HZ),
645 calibration_result % (1000000 / HZ));
648 * Do a sanity check on the APIC calibration result
650 if (calibration_result < (1000000 / HZ)) {
653 "APIC frequency too slow, disabling apic timer\n");
657 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
660 * PM timer calibration failed or not turned on
661 * so lets try APIC timer based calibration
663 if (!pm_referenced) {
664 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
667 * Setup the apic timer manually
669 levt->event_handler = lapic_cal_handler;
670 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
671 lapic_cal_loops = -1;
673 /* Let the interrupts run */
676 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
681 /* Stop the lapic timer */
682 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
687 deltaj = lapic_cal_j2 - lapic_cal_j1;
688 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
690 /* Check, if the jiffies result is consistent */
691 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
692 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
694 levt->features |= CLOCK_EVT_FEAT_DUMMY;
698 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
700 "APIC timer disabled due to verification failure.\n");
708 * Setup the boot APIC
710 * Calibrate and verify the result.
712 void __init setup_boot_APIC_clock(void)
715 * The local apic timer can be disabled via the kernel
716 * commandline or from the CPU detection code. Register the lapic
717 * timer as a dummy clock event source on SMP systems, so the
718 * broadcast mechanism is used. On UP systems simply ignore it.
720 if (disable_apic_timer) {
721 printk(KERN_INFO "Disabling APIC timer\n");
722 /* No broadcast on UP ! */
723 if (num_possible_cpus() > 1) {
724 lapic_clockevent.mult = 1;
730 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
731 "calibrating APIC timer ...\n");
733 if (calibrate_APIC_clock()) {
734 /* No broadcast on UP ! */
735 if (num_possible_cpus() > 1)
741 * If nmi_watchdog is set to IO_APIC, we need the
742 * PIT/HPET going. Otherwise register lapic as a dummy
745 if (nmi_watchdog != NMI_IO_APIC)
746 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
748 printk(KERN_WARNING "APIC timer registered as dummy,"
749 " due to nmi_watchdog=%d!\n", nmi_watchdog);
751 /* Setup the lapic or request the broadcast */
755 void __cpuinit setup_secondary_APIC_clock(void)
761 * The guts of the apic timer interrupt
763 static void local_apic_timer_interrupt(void)
765 int cpu = smp_processor_id();
766 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
769 * Normally we should not be here till LAPIC has been initialized but
770 * in some cases like kdump, its possible that there is a pending LAPIC
771 * timer interrupt from previous kernel's context and is delivered in
772 * new kernel the moment interrupts are enabled.
774 * Interrupts are enabled early and LAPIC is setup much later, hence
775 * its possible that when we get here evt->event_handler is NULL.
776 * Check for event_handler being NULL and discard the interrupt as
779 if (!evt->event_handler) {
781 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
783 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
788 * the NMI deadlock-detector uses this.
791 add_pda(apic_timer_irqs, 1);
793 per_cpu(irq_stat, cpu).apic_timer_irqs++;
796 evt->event_handler(evt);
800 * Local APIC timer interrupt. This is the most natural way for doing
801 * local interrupts, but local timer interrupts can be emulated by
802 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
804 * [ if a single-CPU system runs an SMP kernel then we call the local
805 * interrupt as well. Thus we cannot inline the local irq ... ]
807 void smp_apic_timer_interrupt(struct pt_regs *regs)
809 struct pt_regs *old_regs = set_irq_regs(regs);
812 * NOTE! We'd better ACK the irq immediately,
813 * because timer handling can be slow.
817 * update_process_times() expects us to have done irq_enter().
818 * Besides, if we don't timer interrupts ignore the global
819 * interrupt lock, which is the WrongThing (tm) to do.
825 local_apic_timer_interrupt();
828 set_irq_regs(old_regs);
831 int setup_profiling_timer(unsigned int multiplier)
837 * Local APIC start and shutdown
841 * clear_local_APIC - shutdown the local APIC
843 * This is called, when a CPU is disabled and before rebooting, so the state of
844 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
845 * leftovers during boot.
847 void clear_local_APIC(void)
852 /* APIC hasn't been mapped yet */
856 maxlvt = lapic_get_maxlvt();
858 * Masking an LVT entry can trigger a local APIC error
859 * if the vector is zero. Mask LVTERR first to prevent this.
862 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
863 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
866 * Careful: we have to set masks only first to deassert
867 * any level-triggered sources.
869 v = apic_read(APIC_LVTT);
870 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
871 v = apic_read(APIC_LVT0);
872 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
873 v = apic_read(APIC_LVT1);
874 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
876 v = apic_read(APIC_LVTPC);
877 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
880 /* lets not touch this if we didn't frob it */
881 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
883 v = apic_read(APIC_LVTTHMR);
884 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
888 * Clean APIC state for other OSs:
890 apic_write(APIC_LVTT, APIC_LVT_MASKED);
891 apic_write(APIC_LVT0, APIC_LVT_MASKED);
892 apic_write(APIC_LVT1, APIC_LVT_MASKED);
894 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
896 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
898 /* Integrated APIC (!82489DX) ? */
899 if (lapic_is_integrated()) {
901 /* Clear ESR due to Pentium errata 3AP and 11AP */
902 apic_write(APIC_ESR, 0);
908 * disable_local_APIC - clear and disable the local APIC
910 void disable_local_APIC(void)
917 * Disable APIC (implies clearing of registers
920 value = apic_read(APIC_SPIV);
921 value &= ~APIC_SPIV_APIC_ENABLED;
922 apic_write(APIC_SPIV, value);
926 * When LAPIC was disabled by the BIOS and enabled by the kernel,
927 * restore the disabled state.
929 if (enabled_via_apicbase) {
932 rdmsr(MSR_IA32_APICBASE, l, h);
933 l &= ~MSR_IA32_APICBASE_ENABLE;
934 wrmsr(MSR_IA32_APICBASE, l, h);
940 * If Linux enabled the LAPIC against the BIOS default disable it down before
941 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
942 * not power-off. Additionally clear all LVT entries before disable_local_APIC
943 * for the case where Linux didn't enable the LAPIC.
945 void lapic_shutdown(void)
952 local_irq_save(flags);
955 if (!enabled_via_apicbase)
959 disable_local_APIC();
962 local_irq_restore(flags);
966 * This is to verify that we're looking at a real local APIC.
967 * Check these against your board if the CPUs aren't getting
968 * started for no apparent reason.
970 int __init verify_local_APIC(void)
972 unsigned int reg0, reg1;
975 * The version register is read-only in a real APIC.
977 reg0 = apic_read(APIC_LVR);
978 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
979 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
980 reg1 = apic_read(APIC_LVR);
981 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
984 * The two version reads above should print the same
985 * numbers. If the second one is different, then we
986 * poke at a non-APIC.
992 * Check if the version looks reasonably.
994 reg1 = GET_APIC_VERSION(reg0);
995 if (reg1 == 0x00 || reg1 == 0xff)
997 reg1 = lapic_get_maxlvt();
998 if (reg1 < 0x02 || reg1 == 0xff)
1002 * The ID register is read/write in a real APIC.
1004 reg0 = apic_read(APIC_ID);
1005 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1006 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
1007 reg1 = apic_read(APIC_ID);
1008 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1009 apic_write(APIC_ID, reg0);
1010 if (reg1 != (reg0 ^ APIC_ID_MASK))
1014 * The next two are just to see if we have sane values.
1015 * They're only really relevant if we're in Virtual Wire
1016 * compatibility mode, but most boxes are anymore.
1018 reg0 = apic_read(APIC_LVT0);
1019 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1020 reg1 = apic_read(APIC_LVT1);
1021 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1027 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1029 void __init sync_Arb_IDs(void)
1032 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1035 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1041 apic_wait_icr_idle();
1043 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1044 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1045 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1049 * An initial setup of the virtual wire mode.
1051 void __init init_bsp_APIC(void)
1056 * Don't do the setup now if we have a SMP BIOS as the
1057 * through-I/O-APIC virtual wire mode might be active.
1059 if (smp_found_config || !cpu_has_apic)
1063 * Do not trust the local APIC being empty at bootup.
1070 value = apic_read(APIC_SPIV);
1071 value &= ~APIC_VECTOR_MASK;
1072 value |= APIC_SPIV_APIC_ENABLED;
1074 #ifdef CONFIG_X86_32
1075 /* This bit is reserved on P4/Xeon and should be cleared */
1076 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1077 (boot_cpu_data.x86 == 15))
1078 value &= ~APIC_SPIV_FOCUS_DISABLED;
1081 value |= APIC_SPIV_FOCUS_DISABLED;
1082 value |= SPURIOUS_APIC_VECTOR;
1083 apic_write(APIC_SPIV, value);
1086 * Set up the virtual wire mode.
1088 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1089 value = APIC_DM_NMI;
1090 if (!lapic_is_integrated()) /* 82489DX */
1091 value |= APIC_LVT_LEVEL_TRIGGER;
1092 apic_write(APIC_LVT1, value);
1095 static void __cpuinit lapic_setup_esr(void)
1097 unsigned int oldvalue, value, maxlvt;
1099 if (!lapic_is_integrated()) {
1100 printk(KERN_INFO "No ESR for 82489DX.\n");
1106 * Something untraceable is creating bad interrupts on
1107 * secondary quads ... for the moment, just leave the
1108 * ESR disabled - we can't do anything useful with the
1109 * errors anyway - mbligh
1111 printk(KERN_INFO "Leaving ESR disabled.\n");
1115 maxlvt = lapic_get_maxlvt();
1116 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1117 apic_write(APIC_ESR, 0);
1118 oldvalue = apic_read(APIC_ESR);
1120 /* enables sending errors */
1121 value = ERROR_APIC_VECTOR;
1122 apic_write(APIC_LVTERR, value);
1125 * spec says clear errors after enabling vector.
1128 apic_write(APIC_ESR, 0);
1129 value = apic_read(APIC_ESR);
1130 if (value != oldvalue)
1131 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1132 "vector: 0x%08x after: 0x%08x\n",
1138 * setup_local_APIC - setup the local APIC
1140 void __cpuinit setup_local_APIC(void)
1145 #ifdef CONFIG_X86_32
1146 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1147 if (lapic_is_integrated() && esr_disable) {
1148 apic_write(APIC_ESR, 0);
1149 apic_write(APIC_ESR, 0);
1150 apic_write(APIC_ESR, 0);
1151 apic_write(APIC_ESR, 0);
1158 * Double-check whether this APIC is really registered.
1159 * This is meaningless in clustered apic mode, so we skip it.
1161 if (!apic_id_registered())
1165 * Intel recommends to set DFR, LDR and TPR before enabling
1166 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1167 * document number 292116). So here it goes...
1172 * Set Task Priority to 'accept all'. We never change this
1175 value = apic_read(APIC_TASKPRI);
1176 value &= ~APIC_TPRI_MASK;
1177 apic_write(APIC_TASKPRI, value);
1180 * After a crash, we no longer service the interrupts and a pending
1181 * interrupt from previous kernel might still have ISR bit set.
1183 * Most probably by now CPU has serviced that pending interrupt and
1184 * it might not have done the ack_APIC_irq() because it thought,
1185 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1186 * does not clear the ISR bit and cpu thinks it has already serivced
1187 * the interrupt. Hence a vector might get locked. It was noticed
1188 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1190 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1191 value = apic_read(APIC_ISR + i*0x10);
1192 for (j = 31; j >= 0; j--) {
1199 * Now that we are all set up, enable the APIC
1201 value = apic_read(APIC_SPIV);
1202 value &= ~APIC_VECTOR_MASK;
1206 value |= APIC_SPIV_APIC_ENABLED;
1208 #ifdef CONFIG_X86_32
1210 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1211 * certain networking cards. If high frequency interrupts are
1212 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1213 * entry is masked/unmasked at a high rate as well then sooner or
1214 * later IOAPIC line gets 'stuck', no more interrupts are received
1215 * from the device. If focus CPU is disabled then the hang goes
1218 * [ This bug can be reproduced easily with a level-triggered
1219 * PCI Ne2000 networking cards and PII/PIII processors, dual
1223 * Actually disabling the focus CPU check just makes the hang less
1224 * frequent as it makes the interrupt distributon model be more
1225 * like LRU than MRU (the short-term load is more even across CPUs).
1226 * See also the comment in end_level_ioapic_irq(). --macro
1230 * - enable focus processor (bit==0)
1231 * - 64bit mode always use processor focus
1232 * so no need to set it
1234 value &= ~APIC_SPIV_FOCUS_DISABLED;
1238 * Set spurious IRQ vector
1240 value |= SPURIOUS_APIC_VECTOR;
1241 apic_write(APIC_SPIV, value);
1244 * Set up LVT0, LVT1:
1246 * set up through-local-APIC on the BP's LINT0. This is not
1247 * strictly necessary in pure symmetric-IO mode, but sometimes
1248 * we delegate interrupts to the 8259A.
1251 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1253 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1254 if (!smp_processor_id() && (pic_mode || !value)) {
1255 value = APIC_DM_EXTINT;
1256 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1257 smp_processor_id());
1259 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1260 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1261 smp_processor_id());
1263 apic_write(APIC_LVT0, value);
1266 * only the BP should see the LINT1 NMI signal, obviously.
1268 if (!smp_processor_id())
1269 value = APIC_DM_NMI;
1271 value = APIC_DM_NMI | APIC_LVT_MASKED;
1272 if (!lapic_is_integrated()) /* 82489DX */
1273 value |= APIC_LVT_LEVEL_TRIGGER;
1274 apic_write(APIC_LVT1, value);
1279 void __cpuinit end_local_APIC_setup(void)
1283 #ifdef CONFIG_X86_32
1286 /* Disable the local apic timer */
1287 value = apic_read(APIC_LVTT);
1288 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1289 apic_write(APIC_LVTT, value);
1293 setup_apic_nmi_watchdog(NULL);
1298 void check_x2apic(void)
1302 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1304 if (msr & X2APIC_ENABLE) {
1305 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
1306 x2apic_preenabled = x2apic = 1;
1307 apic_ops = &x2apic_ops;
1311 void enable_x2apic(void)
1315 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1316 if (!(msr & X2APIC_ENABLE)) {
1317 printk("Enabling x2apic\n");
1318 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1322 void enable_IR_x2apic(void)
1324 #ifdef CONFIG_INTR_REMAP
1326 unsigned long flags;
1328 if (!cpu_has_x2apic)
1331 if (!x2apic_preenabled && disable_x2apic) {
1333 "Skipped enabling x2apic and Interrupt-remapping "
1334 "because of nox2apic\n");
1338 if (x2apic_preenabled && disable_x2apic)
1339 panic("Bios already enabled x2apic, can't enforce nox2apic");
1341 if (!x2apic_preenabled && skip_ioapic_setup) {
1343 "Skipped enabling x2apic and Interrupt-remapping "
1344 "because of skipping io-apic setup\n");
1348 ret = dmar_table_init();
1351 "dmar_table_init() failed with %d:\n", ret);
1353 if (x2apic_preenabled)
1354 panic("x2apic enabled by bios. But IR enabling failed");
1357 "Not enabling x2apic,Intr-remapping\n");
1361 local_irq_save(flags);
1364 ret = save_mask_IO_APIC_setup();
1366 printk(KERN_INFO "Saving IO-APIC state failed: %d\n", ret);
1370 ret = enable_intr_remapping(1);
1372 if (ret && x2apic_preenabled) {
1373 local_irq_restore(flags);
1374 panic("x2apic enabled by bios. But IR enabling failed");
1382 apic_ops = &x2apic_ops;
1389 * IR enabling failed
1391 restore_IO_APIC_setup();
1393 reinit_intr_remapped_IO_APIC(x2apic_preenabled);
1397 local_irq_restore(flags);
1400 if (!x2apic_preenabled)
1402 "Enabled x2apic and interrupt-remapping\n");
1405 "Enabled Interrupt-remapping\n");
1408 "Failed to enable Interrupt-remapping and x2apic\n");
1410 if (!cpu_has_x2apic)
1413 if (x2apic_preenabled)
1414 panic("x2apic enabled prior OS handover,"
1415 " enable CONFIG_INTR_REMAP");
1417 printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1423 #endif /* HAVE_X2APIC */
1425 #ifdef CONFIG_X86_64
1427 * Detect and enable local APICs on non-SMP boards.
1428 * Original code written by Keir Fraser.
1429 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1430 * not correctly set up (usually the APIC timer won't work etc.)
1432 static int __init detect_init_APIC(void)
1434 if (!cpu_has_apic) {
1435 printk(KERN_INFO "No local APIC present\n");
1439 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1440 boot_cpu_physical_apicid = 0;
1445 * Detect and initialize APIC
1447 static int __init detect_init_APIC(void)
1451 /* Disabled by kernel option? */
1455 switch (boot_cpu_data.x86_vendor) {
1456 case X86_VENDOR_AMD:
1457 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1458 (boot_cpu_data.x86 == 15))
1461 case X86_VENDOR_INTEL:
1462 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1463 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1470 if (!cpu_has_apic) {
1472 * Over-ride BIOS and try to enable the local APIC only if
1473 * "lapic" specified.
1475 if (!force_enable_local_apic) {
1476 printk(KERN_INFO "Local APIC disabled by BIOS -- "
1477 "you can enable it with \"lapic\"\n");
1481 * Some BIOSes disable the local APIC in the APIC_BASE
1482 * MSR. This can only be done in software for Intel P6 or later
1483 * and AMD K7 (Model > 1) or later.
1485 rdmsr(MSR_IA32_APICBASE, l, h);
1486 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1488 "Local APIC disabled by BIOS -- reenabling.\n");
1489 l &= ~MSR_IA32_APICBASE_BASE;
1490 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1491 wrmsr(MSR_IA32_APICBASE, l, h);
1492 enabled_via_apicbase = 1;
1496 * The APIC feature bit should now be enabled
1499 features = cpuid_edx(1);
1500 if (!(features & (1 << X86_FEATURE_APIC))) {
1501 printk(KERN_WARNING "Could not enable APIC!\n");
1504 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1505 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1507 /* The BIOS may have set up the APIC at some other address */
1508 rdmsr(MSR_IA32_APICBASE, l, h);
1509 if (l & MSR_IA32_APICBASE_ENABLE)
1510 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1512 printk(KERN_INFO "Found and enabled local APIC!\n");
1519 printk(KERN_INFO "No local APIC present or hardware disabled\n");
1524 #ifdef CONFIG_X86_64
1525 void __init early_init_lapic_mapping(void)
1527 unsigned long phys_addr;
1530 * If no local APIC can be found then go out
1531 * : it means there is no mpatable and MADT
1533 if (!smp_found_config)
1536 phys_addr = mp_lapic_addr;
1538 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
1539 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1540 APIC_BASE, phys_addr);
1543 * Fetch the APIC ID of the BSP in case we have a
1544 * default configuration (or the MP table is broken).
1546 boot_cpu_physical_apicid = read_apic_id();
1551 * init_apic_mappings - initialize APIC mappings
1553 void __init init_apic_mappings(void)
1557 boot_cpu_physical_apicid = read_apic_id();
1563 * If no local APIC can be found then set up a fake all
1564 * zeroes page to simulate the local APIC and another
1565 * one for the IO-APIC.
1567 if (!smp_found_config && detect_init_APIC()) {
1568 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1569 apic_phys = __pa(apic_phys);
1571 apic_phys = mp_lapic_addr;
1573 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1574 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
1575 APIC_BASE, apic_phys);
1578 * Fetch the APIC ID of the BSP in case we have a
1579 * default configuration (or the MP table is broken).
1581 if (boot_cpu_physical_apicid == -1U)
1582 boot_cpu_physical_apicid = read_apic_id();
1586 * This initializes the IO-APIC and APIC hardware if this is
1589 int apic_version[MAX_APICS];
1591 int __init APIC_init_uniprocessor(void)
1593 #ifdef CONFIG_X86_64
1595 printk(KERN_INFO "Apic disabled\n");
1598 if (!cpu_has_apic) {
1600 printk(KERN_INFO "Apic disabled by BIOS\n");
1604 if (!smp_found_config && !cpu_has_apic)
1608 * Complain if the BIOS pretends there is one.
1610 if (!cpu_has_apic &&
1611 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1612 printk(KERN_ERR "BIOS bug, local APIC 0x%x not detected!...\n",
1613 boot_cpu_physical_apicid);
1614 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1622 #ifdef CONFIG_X86_64
1623 setup_apic_routing();
1626 verify_local_APIC();
1629 #ifdef CONFIG_X86_64
1630 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1633 * Hack: In case of kdump, after a crash, kernel might be booting
1634 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1635 * might be zero if read from MP tables. Get it from LAPIC.
1637 # ifdef CONFIG_CRASH_DUMP
1638 boot_cpu_physical_apicid = read_apic_id();
1641 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1644 #ifdef CONFIG_X86_64
1646 * Now enable IO-APICs, actually call clear_IO_APIC
1647 * We need clear_IO_APIC before enabling vector on BP
1649 if (!skip_ioapic_setup && nr_ioapics)
1653 #ifdef CONFIG_X86_IO_APIC
1654 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
1656 localise_nmi_watchdog();
1657 end_local_APIC_setup();
1659 #ifdef CONFIG_X86_IO_APIC
1660 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1662 # ifdef CONFIG_X86_64
1668 #ifdef CONFIG_X86_64
1669 setup_boot_APIC_clock();
1670 check_nmi_watchdog();
1679 * Local APIC interrupts
1683 * This interrupt should _never_ happen with our APIC/SMP architecture
1685 void smp_spurious_interrupt(struct pt_regs *regs)
1689 #ifdef CONFIG_X86_64
1694 * Check if this really is a spurious interrupt and ACK it
1695 * if it is a vectored one. Just in case...
1696 * Spurious interrupts should not be ACKed.
1698 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1699 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1702 #ifdef CONFIG_X86_64
1703 add_pda(irq_spurious_count, 1);
1705 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1706 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, "
1707 "should never happen.\n", smp_processor_id());
1708 __get_cpu_var(irq_stat).irq_spurious_count++;
1714 * This interrupt should never happen with our APIC/SMP architecture
1716 void smp_error_interrupt(struct pt_regs *regs)
1720 #ifdef CONFIG_X86_64
1724 /* First tickle the hardware, only then report what went on. -- REW */
1725 v = apic_read(APIC_ESR);
1726 apic_write(APIC_ESR, 0);
1727 v1 = apic_read(APIC_ESR);
1729 atomic_inc(&irq_err_count);
1731 /* Here is what the APIC error bits mean:
1734 2: Send accept error
1735 3: Receive accept error
1737 5: Send illegal vector
1738 6: Received illegal vector
1739 7: Illegal register address
1741 printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1742 smp_processor_id(), v , v1);
1747 * connect_bsp_APIC - attach the APIC to the interrupt system
1749 void __init connect_bsp_APIC(void)
1751 #ifdef CONFIG_X86_32
1754 * Do not trust the local APIC being empty at bootup.
1758 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1759 * local APIC to INT and NMI lines.
1761 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1762 "enabling APIC mode.\n");
1771 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1772 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1774 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1777 void disconnect_bsp_APIC(int virt_wire_setup)
1781 #ifdef CONFIG_X86_32
1784 * Put the board back into PIC mode (has an effect only on
1785 * certain older boards). Note that APIC interrupts, including
1786 * IPIs, won't work beyond this point! The only exception are
1789 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1790 "entering PIC mode.\n");
1797 /* Go back to Virtual Wire compatibility mode */
1799 /* For the spurious interrupt use vector F, and enable it */
1800 value = apic_read(APIC_SPIV);
1801 value &= ~APIC_VECTOR_MASK;
1802 value |= APIC_SPIV_APIC_ENABLED;
1804 apic_write(APIC_SPIV, value);
1806 if (!virt_wire_setup) {
1808 * For LVT0 make it edge triggered, active high,
1809 * external and enabled
1811 value = apic_read(APIC_LVT0);
1812 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1813 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1814 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1815 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1816 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1817 apic_write(APIC_LVT0, value);
1820 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1824 * For LVT1 make it edge triggered, active high,
1827 value = apic_read(APIC_LVT1);
1828 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1829 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1830 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1831 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1832 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1833 apic_write(APIC_LVT1, value);
1836 void __cpuinit generic_processor_info(int apicid, int version)
1844 if (version == 0x0) {
1845 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
1846 "fixing up to 0x10. (tell your hw vendor)\n",
1850 apic_version[apicid] = version;
1852 if (num_processors >= NR_CPUS) {
1853 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1854 " Processor ignored.\n", NR_CPUS);
1859 cpus_complement(tmp_map, cpu_present_map);
1860 cpu = first_cpu(tmp_map);
1862 physid_set(apicid, phys_cpu_present_map);
1863 if (apicid == boot_cpu_physical_apicid) {
1865 * x86_bios_cpu_apicid is required to have processors listed
1866 * in same order as logical cpu numbers. Hence the first
1867 * entry is BSP, and so on.
1871 if (apicid > max_physical_apicid)
1872 max_physical_apicid = apicid;
1874 #ifdef CONFIG_X86_32
1876 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1877 * but we need to work other dependencies like SMP_SUSPEND etc
1878 * before this can be done without some confusion.
1879 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1880 * - Ashok Raj <ashok.raj@intel.com>
1882 if (max_physical_apicid >= 8) {
1883 switch (boot_cpu_data.x86_vendor) {
1884 case X86_VENDOR_INTEL:
1885 if (!APIC_XAPIC(version)) {
1889 /* If P4 and above fall through */
1890 case X86_VENDOR_AMD:
1896 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1897 /* are we being called early in kernel startup? */
1898 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1899 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1900 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1902 cpu_to_apicid[cpu] = apicid;
1903 bios_cpu_apicid[cpu] = apicid;
1905 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1906 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1910 cpu_set(cpu, cpu_possible_map);
1911 cpu_set(cpu, cpu_present_map);
1914 #ifdef CONFIG_X86_64
1915 int hard_smp_processor_id(void)
1917 return read_apic_id();
1928 * 'active' is true if the local APIC was enabled by us and
1929 * not the BIOS; this signifies that we are also responsible
1930 * for disabling it before entering apm/acpi suspend
1933 /* r/w apic fields */
1934 unsigned int apic_id;
1935 unsigned int apic_taskpri;
1936 unsigned int apic_ldr;
1937 unsigned int apic_dfr;
1938 unsigned int apic_spiv;
1939 unsigned int apic_lvtt;
1940 unsigned int apic_lvtpc;
1941 unsigned int apic_lvt0;
1942 unsigned int apic_lvt1;
1943 unsigned int apic_lvterr;
1944 unsigned int apic_tmict;
1945 unsigned int apic_tdcr;
1946 unsigned int apic_thmr;
1949 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1951 unsigned long flags;
1954 if (!apic_pm_state.active)
1957 maxlvt = lapic_get_maxlvt();
1959 apic_pm_state.apic_id = apic_read(APIC_ID);
1960 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1961 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1962 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1963 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1964 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1966 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1967 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1968 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1969 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1970 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1971 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1972 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1974 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1977 local_irq_save(flags);
1978 disable_local_APIC();
1979 local_irq_restore(flags);
1983 static int lapic_resume(struct sys_device *dev)
1986 unsigned long flags;
1989 if (!apic_pm_state.active)
1992 maxlvt = lapic_get_maxlvt();
1994 local_irq_save(flags);
2003 * Make sure the APICBASE points to the right address
2005 * FIXME! This will be wrong if we ever support suspend on
2006 * SMP! We'll need to do this as part of the CPU restore!
2008 rdmsr(MSR_IA32_APICBASE, l, h);
2009 l &= ~MSR_IA32_APICBASE_BASE;
2010 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2011 wrmsr(MSR_IA32_APICBASE, l, h);
2014 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2015 apic_write(APIC_ID, apic_pm_state.apic_id);
2016 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2017 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2018 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2019 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2020 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2021 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2022 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2024 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2027 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2028 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2029 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2030 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2031 apic_write(APIC_ESR, 0);
2032 apic_read(APIC_ESR);
2033 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2034 apic_write(APIC_ESR, 0);
2035 apic_read(APIC_ESR);
2037 local_irq_restore(flags);
2043 * This device has no shutdown method - fully functioning local APICs
2044 * are needed on every CPU up until machine_halt/restart/poweroff.
2047 static struct sysdev_class lapic_sysclass = {
2049 .resume = lapic_resume,
2050 .suspend = lapic_suspend,
2053 static struct sys_device device_lapic = {
2055 .cls = &lapic_sysclass,
2058 static void __cpuinit apic_pm_activate(void)
2060 apic_pm_state.active = 1;
2063 static int __init init_lapic_sysfs(void)
2069 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2071 error = sysdev_class_register(&lapic_sysclass);
2073 error = sysdev_register(&device_lapic);
2076 device_initcall(init_lapic_sysfs);
2078 #else /* CONFIG_PM */
2080 static void apic_pm_activate(void) { }
2082 #endif /* CONFIG_PM */
2084 #ifdef CONFIG_X86_64
2086 * apic_is_clustered_box() -- Check if we can expect good TSC
2088 * Thus far, the major user of this is IBM's Summit2 series:
2090 * Clustered boxes may have unsynced TSC problems if they are
2091 * multi-chassis. Use available data to take a good guess.
2092 * If in doubt, go HPET.
2094 __cpuinit int apic_is_clustered_box(void)
2096 int i, clusters, zeros;
2098 u16 *bios_cpu_apicid;
2099 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2102 * there is not this kind of box with AMD CPU yet.
2103 * Some AMD box with quadcore cpu and 8 sockets apicid
2104 * will be [4, 0x23] or [8, 0x27] could be thought to
2105 * vsmp box still need checking...
2107 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
2110 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2111 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2113 for (i = 0; i < NR_CPUS; i++) {
2114 /* are we being called early in kernel startup? */
2115 if (bios_cpu_apicid) {
2116 id = bios_cpu_apicid[i];
2118 else if (i < nr_cpu_ids) {
2120 id = per_cpu(x86_bios_cpu_apicid, i);
2127 if (id != BAD_APICID)
2128 __set_bit(APIC_CLUSTERID(id), clustermap);
2131 /* Problem: Partially populated chassis may not have CPUs in some of
2132 * the APIC clusters they have been allocated. Only present CPUs have
2133 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2134 * Since clusters are allocated sequentially, count zeros only if
2135 * they are bounded by ones.
2139 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2140 if (test_bit(i, clustermap)) {
2141 clusters += 1 + zeros;
2147 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2148 * not guaranteed to be synced between boards
2150 if (is_vsmp_box() && clusters > 1)
2154 * If clusters > 2, then should be multi-chassis.
2155 * May have to revisit this when multi-core + hyperthreaded CPUs come
2156 * out, but AFAIK this will work even for them.
2158 return (clusters > 2);
2163 * APIC command line parameters
2165 static int __init setup_disableapic(char *arg)
2168 setup_clear_cpu_cap(X86_FEATURE_APIC);
2171 early_param("disableapic", setup_disableapic);
2173 /* same as disableapic, for compatibility */
2174 static int __init setup_nolapic(char *arg)
2176 return setup_disableapic(arg);
2178 early_param("nolapic", setup_nolapic);
2180 static int __init parse_lapic_timer_c2_ok(char *arg)
2182 local_apic_timer_c2_ok = 1;
2185 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2187 static int __init parse_disable_apic_timer(char *arg)
2189 disable_apic_timer = 1;
2192 early_param("noapictimer", parse_disable_apic_timer);
2194 static int __init parse_nolapic_timer(char *arg)
2196 disable_apic_timer = 1;
2199 early_param("nolapic_timer", parse_nolapic_timer);
2201 static int __init apic_set_verbosity(char *arg)
2204 #ifdef CONFIG_X86_64
2205 skip_ioapic_setup = 0;
2211 if (strcmp("debug", arg) == 0)
2212 apic_verbosity = APIC_DEBUG;
2213 else if (strcmp("verbose", arg) == 0)
2214 apic_verbosity = APIC_VERBOSE;
2216 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
2217 " use apic=verbose or apic=debug\n", arg);
2223 early_param("apic", apic_set_verbosity);
2225 static int __init lapic_insert_resource(void)
2230 /* Put local APIC into the resource map. */
2231 lapic_resource.start = apic_phys;
2232 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2233 insert_resource(&iomem_resource, &lapic_resource);
2239 * need call insert after e820_reserve_resources()
2240 * that is using request_resource
2242 late_initcall(lapic_insert_resource);