2 * sata_inic162x.c - Driver for Initio 162x SATA controllers
4 * Copyright 2006 SUSE Linux Products GmbH
5 * Copyright 2006 Tejun Heo <teheo@novell.com>
7 * This file is released under GPL v2.
9 * This controller is eccentric and easily locks up if something isn't
10 * right. Documentation is available at initio's website but it only
11 * documents registers (not programming model).
15 * - ATAPI read works but burning doesn't. This thing is really
16 * peculiar about ATAPI and I couldn't figure out how ATAPI PIO and
17 * ATAPI DMA WRITE should be programmed. If you've got a clue, be
19 * - Both STR and STD work.
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <scsi/scsi_host.h>
26 #include <linux/libata.h>
27 #include <linux/blkdev.h>
28 #include <scsi/scsi_device.h>
30 #define DRV_NAME "sata_inic162x"
31 #define DRV_VERSION "0.1"
45 /* registers for ATA TF operation */
52 PORT_PRD_XFERLEN = 0x10,
60 HCTL_IRQOFF = (1 << 8), /* global IRQ off */
61 HCTL_PWRDWN = (1 << 13), /* power down PHYs */
62 HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */
63 HCTL_RPGSEL = (1 << 15), /* register page select */
65 HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST |
68 /* HOST_IRQ_(STAT|MASK) bits */
69 HIRQ_PORT0 = (1 << 0),
70 HIRQ_PORT1 = (1 << 1),
71 HIRQ_SOFT = (1 << 14),
72 HIRQ_GLOBAL = (1 << 15), /* STAT only */
74 /* PORT_IRQ_(STAT|MASK) bits */
75 PIRQ_OFFLINE = (1 << 0), /* device unplugged */
76 PIRQ_ONLINE = (1 << 1), /* device plugged */
77 PIRQ_COMPLETE = (1 << 2), /* completion interrupt */
78 PIRQ_FATAL = (1 << 3), /* fatal error */
79 PIRQ_ATA = (1 << 4), /* ATA interrupt */
80 PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */
81 PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */
83 PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL,
85 PIRQ_MASK_DMA_READ = PIRQ_REPLY | PIRQ_ATA,
86 PIRQ_MASK_OTHER = PIRQ_REPLY | PIRQ_COMPLETE,
87 PIRQ_MASK_FREEZE = 0xff,
89 /* PORT_PRD_CTL bits */
90 PRD_CTL_START = (1 << 0),
91 PRD_CTL_WR = (1 << 3),
92 PRD_CTL_DMAEN = (1 << 7), /* DMA enable */
94 /* PORT_IDMA_CTL bits */
95 IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */
96 IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinary */
97 IDMA_CTL_GO = (1 << 7), /* IDMA mode go */
98 IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */
101 struct inic_host_priv {
105 struct inic_port_priv {
111 static int inic_slave_config(struct scsi_device *sdev)
113 /* This controller is braindamaged. dma_boundary is 0xffff
114 * like others but it will lock up the whole machine HARD if
115 * 65536 byte PRD entry is fed. Reduce maximum segment size.
117 blk_queue_max_segment_size(sdev->request_queue, 65536 - 512);
119 return ata_scsi_slave_config(sdev);
122 static struct scsi_host_template inic_sht = {
123 .module = THIS_MODULE,
125 .ioctl = ata_scsi_ioctl,
126 .queuecommand = ata_scsi_queuecmd,
127 .can_queue = ATA_DEF_QUEUE,
128 .this_id = ATA_SHT_THIS_ID,
129 .sg_tablesize = LIBATA_MAX_PRD,
130 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
131 .emulated = ATA_SHT_EMULATED,
132 .use_clustering = ATA_SHT_USE_CLUSTERING,
133 .proc_name = DRV_NAME,
134 .dma_boundary = ATA_DMA_BOUNDARY,
135 .slave_configure = inic_slave_config,
136 .slave_destroy = ata_scsi_slave_destroy,
137 .bios_param = ata_std_bios_param,
139 .suspend = ata_scsi_device_suspend,
140 .resume = ata_scsi_device_resume,
144 static const int scr_map[] = {
150 static void __iomem * inic_port_base(struct ata_port *ap)
152 return ap->host->iomap[MMIO_BAR] + ap->port_no * PORT_SIZE;
155 static void __inic_set_pirq_mask(struct ata_port *ap, u8 mask)
157 void __iomem *port_base = inic_port_base(ap);
158 struct inic_port_priv *pp = ap->private_data;
160 writeb(mask, port_base + PORT_IRQ_MASK);
161 pp->cached_pirq_mask = mask;
164 static void inic_set_pirq_mask(struct ata_port *ap, u8 mask)
166 struct inic_port_priv *pp = ap->private_data;
168 if (pp->cached_pirq_mask != mask)
169 __inic_set_pirq_mask(ap, mask);
172 static void inic_reset_port(void __iomem *port_base)
174 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
177 ctl = readw(idma_ctl);
178 ctl &= ~(IDMA_CTL_RST_IDMA | IDMA_CTL_ATA_NIEN | IDMA_CTL_GO);
180 /* mask IRQ and assert reset */
181 writew(ctl | IDMA_CTL_RST_IDMA | IDMA_CTL_ATA_NIEN, idma_ctl);
182 readw(idma_ctl); /* flush */
184 /* give it some time */
188 writew(ctl | IDMA_CTL_ATA_NIEN, idma_ctl);
191 writeb(0xff, port_base + PORT_IRQ_STAT);
193 /* reenable ATA IRQ, turn off IDMA mode */
194 writew(ctl, idma_ctl);
197 static u32 inic_scr_read(struct ata_port *ap, unsigned sc_reg)
199 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
203 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
206 addr = scr_addr + scr_map[sc_reg] * 4;
207 val = readl(scr_addr + scr_map[sc_reg] * 4);
209 /* this controller has stuck DIAG.N, ignore it */
210 if (sc_reg == SCR_ERROR)
211 val &= ~SERR_PHYRDY_CHG;
215 static void inic_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
217 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
220 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
223 addr = scr_addr + scr_map[sc_reg] * 4;
224 writel(val, scr_addr + scr_map[sc_reg] * 4);
228 * In TF mode, inic162x is very similar to SFF device. TF registers
229 * function the same. DMA engine behaves similary using the same PRD
230 * format as BMDMA but different command register, interrupt and event
231 * notification methods are used. The following inic_bmdma_*()
232 * functions do the impedance matching.
234 static void inic_bmdma_setup(struct ata_queued_cmd *qc)
236 struct ata_port *ap = qc->ap;
237 struct inic_port_priv *pp = ap->private_data;
238 void __iomem *port_base = inic_port_base(ap);
239 int rw = qc->tf.flags & ATA_TFLAG_WRITE;
241 /* make sure device sees PRD table writes */
244 /* load transfer length */
245 writel(qc->nbytes, port_base + PORT_PRD_XFERLEN);
247 /* turn on DMA and specify data direction */
248 pp->cached_prdctl = pp->dfl_prdctl | PRD_CTL_DMAEN;
250 pp->cached_prdctl |= PRD_CTL_WR;
251 writeb(pp->cached_prdctl, port_base + PORT_PRD_CTL);
253 /* issue r/w command */
254 ap->ops->exec_command(ap, &qc->tf);
257 static void inic_bmdma_start(struct ata_queued_cmd *qc)
259 struct ata_port *ap = qc->ap;
260 struct inic_port_priv *pp = ap->private_data;
261 void __iomem *port_base = inic_port_base(ap);
263 /* start host DMA transaction */
264 pp->cached_prdctl |= PRD_CTL_START;
265 writeb(pp->cached_prdctl, port_base + PORT_PRD_CTL);
268 static void inic_bmdma_stop(struct ata_queued_cmd *qc)
270 struct ata_port *ap = qc->ap;
271 struct inic_port_priv *pp = ap->private_data;
272 void __iomem *port_base = inic_port_base(ap);
274 /* stop DMA engine */
275 writeb(pp->dfl_prdctl, port_base + PORT_PRD_CTL);
278 static u8 inic_bmdma_status(struct ata_port *ap)
280 /* event is already verified by the interrupt handler */
284 static void inic_irq_clear(struct ata_port *ap)
289 static void inic_host_intr(struct ata_port *ap)
291 void __iomem *port_base = inic_port_base(ap);
292 struct ata_eh_info *ehi = &ap->eh_info;
295 /* fetch and clear irq */
296 irq_stat = readb(port_base + PORT_IRQ_STAT);
297 writeb(irq_stat, port_base + PORT_IRQ_STAT);
299 if (likely(!(irq_stat & PIRQ_ERR))) {
300 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
302 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
303 ata_chk_status(ap); /* clear ATA interrupt */
307 if (likely(ata_host_intr(ap, qc)))
310 ata_chk_status(ap); /* clear ATA interrupt */
311 ata_port_printk(ap, KERN_WARNING, "unhandled "
312 "interrupt, irq_stat=%x\n", irq_stat);
317 ata_ehi_push_desc(ehi, "irq_stat=0x%x", irq_stat);
319 if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) {
320 ata_ehi_hotplugged(ehi);
326 static irqreturn_t inic_interrupt(int irq, void *dev_instance)
328 struct ata_host *host = dev_instance;
329 void __iomem *mmio_base = host->iomap[MMIO_BAR];
333 host_irq_stat = readw(mmio_base + HOST_IRQ_STAT);
335 if (unlikely(!(host_irq_stat & HIRQ_GLOBAL)))
338 spin_lock(&host->lock);
340 for (i = 0; i < NR_PORTS; i++) {
341 struct ata_port *ap = host->ports[i];
343 if (!(host_irq_stat & (HIRQ_PORT0 << i)))
346 if (likely(ap && !(ap->flags & ATA_FLAG_DISABLED))) {
351 dev_printk(KERN_ERR, host->dev, "interrupt "
352 "from disabled port %d (0x%x)\n",
357 spin_unlock(&host->lock);
360 return IRQ_RETVAL(handled);
363 static unsigned int inic_qc_issue(struct ata_queued_cmd *qc)
365 struct ata_port *ap = qc->ap;
367 /* ATA IRQ doesn't wait for DMA transfer completion and vice
368 * versa. Mask IRQ selectively to detect command completion.
369 * Without it, ATA DMA read command can cause data corruption.
371 * Something similar might be needed for ATAPI writes. I
372 * tried a lot of combinations but couldn't find the solution.
374 if (qc->tf.protocol == ATA_PROT_DMA &&
375 !(qc->tf.flags & ATA_TFLAG_WRITE))
376 inic_set_pirq_mask(ap, PIRQ_MASK_DMA_READ);
378 inic_set_pirq_mask(ap, PIRQ_MASK_OTHER);
380 /* Issuing a command to yet uninitialized port locks up the
381 * controller. Most of the time, this happens for the first
382 * command after reset which are ATA and ATAPI IDENTIFYs.
383 * Fast fail if stat is 0x7f or 0xff for those commands.
385 if (unlikely(qc->tf.command == ATA_CMD_ID_ATA ||
386 qc->tf.command == ATA_CMD_ID_ATAPI)) {
387 u8 stat = ata_chk_status(ap);
388 if (stat == 0x7f || stat == 0xff)
392 return ata_qc_issue_prot(qc);
395 static void inic_freeze(struct ata_port *ap)
397 void __iomem *port_base = inic_port_base(ap);
399 __inic_set_pirq_mask(ap, PIRQ_MASK_FREEZE);
402 writeb(0xff, port_base + PORT_IRQ_STAT);
404 readb(port_base + PORT_IRQ_STAT); /* flush */
407 static void inic_thaw(struct ata_port *ap)
409 void __iomem *port_base = inic_port_base(ap);
412 writeb(0xff, port_base + PORT_IRQ_STAT);
414 __inic_set_pirq_mask(ap, PIRQ_MASK_OTHER);
416 readb(port_base + PORT_IRQ_STAT); /* flush */
420 * SRST and SControl hardreset don't give valid signature on this
421 * controller. Only controller specific hardreset mechanism works.
423 static int inic_hardreset(struct ata_port *ap, unsigned int *class)
425 void __iomem *port_base = inic_port_base(ap);
426 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
427 const unsigned long *timing = sata_ehc_deb_timing(&ap->eh_context);
431 /* hammer it into sane state */
432 inic_reset_port(port_base);
434 val = readw(idma_ctl);
435 writew(val | IDMA_CTL_RST_ATA, idma_ctl);
436 readw(idma_ctl); /* flush */
438 writew(val & ~IDMA_CTL_RST_ATA, idma_ctl);
440 rc = sata_phy_resume(ap, timing);
442 ata_port_printk(ap, KERN_WARNING, "failed to resume "
443 "link after reset (errno=%d)\n", rc);
447 *class = ATA_DEV_NONE;
448 if (ata_port_online(ap)) {
449 struct ata_taskfile tf;
451 /* wait a while before checking status */
454 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
455 ata_port_printk(ap, KERN_WARNING,
456 "device busy after hardreset\n");
460 ata_tf_read(ap, &tf);
461 *class = ata_dev_classify(&tf);
462 if (*class == ATA_DEV_UNKNOWN)
463 *class = ATA_DEV_NONE;
469 static void inic_error_handler(struct ata_port *ap)
471 void __iomem *port_base = inic_port_base(ap);
472 struct inic_port_priv *pp = ap->private_data;
475 /* reset PIO HSM and stop DMA engine */
476 inic_reset_port(port_base);
478 spin_lock_irqsave(ap->lock, flags);
479 ap->hsm_task_state = HSM_ST_IDLE;
480 writeb(pp->dfl_prdctl, port_base + PORT_PRD_CTL);
481 spin_unlock_irqrestore(ap->lock, flags);
483 /* PIO and DMA engines have been stopped, perform recovery */
484 ata_do_eh(ap, ata_std_prereset, NULL, inic_hardreset,
488 static void inic_post_internal_cmd(struct ata_queued_cmd *qc)
490 /* make DMA engine forget about the failed command */
491 if (qc->flags & ATA_QCFLAG_FAILED)
492 inic_reset_port(inic_port_base(qc->ap));
495 static void inic_dev_config(struct ata_device *dev)
497 /* inic can only handle upto LBA28 max sectors */
498 if (dev->max_sectors > ATA_MAX_SECTORS)
499 dev->max_sectors = ATA_MAX_SECTORS;
502 static void init_port(struct ata_port *ap)
504 void __iomem *port_base = inic_port_base(ap);
506 /* Setup PRD address */
507 writel(ap->prd_dma, port_base + PORT_PRD_ADDR);
510 static int inic_port_resume(struct ata_port *ap)
516 static int inic_port_start(struct ata_port *ap)
518 void __iomem *port_base = inic_port_base(ap);
519 struct inic_port_priv *pp;
523 /* alloc and initialize private data */
524 pp = devm_kzalloc(ap->host->dev, sizeof(*pp), GFP_KERNEL);
527 ap->private_data = pp;
529 /* default PRD_CTL value, DMAEN, WR and START off */
530 tmp = readb(port_base + PORT_PRD_CTL);
531 tmp &= ~(PRD_CTL_DMAEN | PRD_CTL_WR | PRD_CTL_START);
532 pp->dfl_prdctl = tmp;
534 /* Alloc resources */
535 rc = ata_port_start(ap);
546 static struct ata_port_operations inic_port_ops = {
547 .port_disable = ata_port_disable,
548 .tf_load = ata_tf_load,
549 .tf_read = ata_tf_read,
550 .check_status = ata_check_status,
551 .exec_command = ata_exec_command,
552 .dev_select = ata_std_dev_select,
554 .scr_read = inic_scr_read,
555 .scr_write = inic_scr_write,
557 .bmdma_setup = inic_bmdma_setup,
558 .bmdma_start = inic_bmdma_start,
559 .bmdma_stop = inic_bmdma_stop,
560 .bmdma_status = inic_bmdma_status,
562 .irq_clear = inic_irq_clear,
563 .irq_on = ata_irq_on,
564 .irq_ack = ata_irq_ack,
566 .qc_prep = ata_qc_prep,
567 .qc_issue = inic_qc_issue,
568 .data_xfer = ata_data_xfer,
570 .freeze = inic_freeze,
572 .error_handler = inic_error_handler,
573 .post_internal_cmd = inic_post_internal_cmd,
574 .dev_config = inic_dev_config,
576 .port_resume = inic_port_resume,
578 .port_start = inic_port_start,
581 static struct ata_port_info inic_port_info = {
582 /* For some reason, ATA_PROT_ATAPI is broken on this
583 * controller, and no, PIO_POLLING does't fix it. It somehow
584 * manages to report the wrong ireason and ignoring ireason
585 * results in machine lock up. Tell libata to always prefer
588 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
589 .pio_mask = 0x1f, /* pio0-4 */
590 .mwdma_mask = 0x07, /* mwdma0-2 */
591 .udma_mask = 0x7f, /* udma0-6 */
592 .port_ops = &inic_port_ops
595 static int init_controller(void __iomem *mmio_base, u16 hctl)
600 hctl &= ~HCTL_KNOWN_BITS;
602 /* Soft reset whole controller. Spec says reset duration is 3
603 * PCI clocks, be generous and give it 10ms.
605 writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL);
606 readw(mmio_base + HOST_CTL); /* flush */
608 for (i = 0; i < 10; i++) {
610 val = readw(mmio_base + HOST_CTL);
611 if (!(val & HCTL_SOFTRST))
615 if (val & HCTL_SOFTRST)
618 /* mask all interrupts and reset ports */
619 for (i = 0; i < NR_PORTS; i++) {
620 void __iomem *port_base = mmio_base + i * PORT_SIZE;
622 writeb(0xff, port_base + PORT_IRQ_MASK);
623 inic_reset_port(port_base);
626 /* port IRQ is masked now, unmask global IRQ */
627 writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL);
628 val = readw(mmio_base + HOST_IRQ_MASK);
629 val &= ~(HIRQ_PORT0 | HIRQ_PORT1);
630 writew(val, mmio_base + HOST_IRQ_MASK);
636 static int inic_pci_device_resume(struct pci_dev *pdev)
638 struct ata_host *host = dev_get_drvdata(&pdev->dev);
639 struct inic_host_priv *hpriv = host->private_data;
640 void __iomem *mmio_base = host->iomap[MMIO_BAR];
643 rc = ata_pci_device_do_resume(pdev);
647 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
648 rc = init_controller(mmio_base, hpriv->cached_hctl);
653 ata_host_resume(host);
659 static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
661 static int printed_version;
662 const struct ata_port_info *ppi[] = { &inic_port_info, NULL };
663 struct ata_host *host;
664 struct inic_host_priv *hpriv;
665 void __iomem * const *iomap;
668 if (!printed_version++)
669 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
672 host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS);
673 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
677 host->private_data = hpriv;
679 /* acquire resources and fill host */
680 rc = pcim_enable_device(pdev);
684 rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME);
687 host->iomap = iomap = pcim_iomap_table(pdev);
689 for (i = 0; i < NR_PORTS; i++) {
690 struct ata_ioports *port = &host->ports[i]->ioaddr;
691 void __iomem *port_base = iomap[MMIO_BAR] + i * PORT_SIZE;
693 port->cmd_addr = iomap[2 * i];
694 port->altstatus_addr =
695 port->ctl_addr = (void __iomem *)
696 ((unsigned long)iomap[2 * i + 1] | ATA_PCI_CTL_OFS);
697 port->scr_addr = port_base + PORT_SCR;
702 hpriv->cached_hctl = readw(iomap[MMIO_BAR] + HOST_CTL);
704 /* Set dma_mask. This devices doesn't support 64bit addressing. */
705 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
707 dev_printk(KERN_ERR, &pdev->dev,
708 "32-bit DMA enable failed\n");
712 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
714 dev_printk(KERN_ERR, &pdev->dev,
715 "32-bit consistent DMA enable failed\n");
719 rc = init_controller(iomap[MMIO_BAR], hpriv->cached_hctl);
721 dev_printk(KERN_ERR, &pdev->dev,
722 "failed to initialize controller\n");
726 pci_set_master(pdev);
727 return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED,
731 static const struct pci_device_id inic_pci_tbl[] = {
732 { PCI_VDEVICE(INIT, 0x1622), },
736 static struct pci_driver inic_pci_driver = {
738 .id_table = inic_pci_tbl,
740 .suspend = ata_pci_device_suspend,
741 .resume = inic_pci_device_resume,
743 .probe = inic_init_one,
744 .remove = ata_pci_remove_one,
747 static int __init inic_init(void)
749 return pci_register_driver(&inic_pci_driver);
752 static void __exit inic_exit(void)
754 pci_unregister_driver(&inic_pci_driver);
757 MODULE_AUTHOR("Tejun Heo");
758 MODULE_DESCRIPTION("low-level driver for Initio 162x SATA");
759 MODULE_LICENSE("GPL v2");
760 MODULE_DEVICE_TABLE(pci, inic_pci_tbl);
761 MODULE_VERSION(DRV_VERSION);
763 module_init(inic_init);
764 module_exit(inic_exit);