2 * Product specific probe and attach routines for:
3 * 3940, 2940, aic7895, aic7890, aic7880,
4 * aic7870, aic7860 and aic7850 SCSI controllers
6 * Copyright (c) 1994-2001 Justin T. Gibbs.
7 * Copyright (c) 2000-2001 Adaptec Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#69 $
48 #include "aic7xxx_osm.h"
49 #include "aic7xxx_inline.h"
50 #include "aic7xxx_93cx6.h"
52 #include <dev/aic7xxx/aic7xxx_osm.h>
53 #include <dev/aic7xxx/aic7xxx_inline.h>
54 #include <dev/aic7xxx/aic7xxx_93cx6.h>
57 #include "aic7xxx_pci.h"
59 static __inline uint64_t
60 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
66 | ((uint64_t)vendor << 32)
67 | ((uint64_t)device << 48);
72 #define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */
73 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */
75 #define DEVID_9005_TYPE(id) ((id) & 0xF)
76 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
77 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */
78 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */
79 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
81 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
82 #define DEVID_9005_MAXRATE_U160 0x0
83 #define DEVID_9005_MAXRATE_ULTRA2 0x1
84 #define DEVID_9005_MAXRATE_ULTRA 0x2
85 #define DEVID_9005_MAXRATE_FAST 0x3
87 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
89 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
90 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */
92 #define SUBID_9005_TYPE(id) ((id) & 0xF)
93 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
94 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */
95 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */
96 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */
98 #define SUBID_9005_TYPE_KNOWN(id) \
99 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \
100 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \
101 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \
102 || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
104 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
105 #define SUBID_9005_MAXRATE_ULTRA2 0x0
106 #define SUBID_9005_MAXRATE_ULTRA 0x1
107 #define SUBID_9005_MAXRATE_U160 0x2
108 #define SUBID_9005_MAXRATE_RESERVED 0x3
110 #define SUBID_9005_SEEPTYPE(id) \
111 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
112 ? ((id) & 0xC0) >> 6 \
113 : ((id) & 0x300) >> 8)
114 #define SUBID_9005_SEEPTYPE_NONE 0x0
115 #define SUBID_9005_SEEPTYPE_1K 0x1
116 #define SUBID_9005_SEEPTYPE_2K_4K 0x2
117 #define SUBID_9005_SEEPTYPE_RESERVED 0x3
118 #define SUBID_9005_AUTOTERM(id) \
119 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
120 ? (((id) & 0x400) >> 10) == 0 \
121 : (((id) & 0x40) >> 6) == 0)
123 #define SUBID_9005_NUMCHAN(id) \
124 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
125 ? ((id) & 0x300) >> 8 \
126 : ((id) & 0xC00) >> 10)
128 #define SUBID_9005_LEGACYCONN(id) \
129 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
131 : ((id) & 0x80) >> 7)
133 #define SUBID_9005_MFUNCENB(id) \
134 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
135 ? ((id) & 0x800) >> 11 \
136 : ((id) & 0x1000) >> 12)
138 * Informational only. Should use chip register to be
139 * certain, but may be use in identification strings.
141 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000
142 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000
143 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000
145 static ahc_device_setup_t ahc_aic785X_setup;
146 static ahc_device_setup_t ahc_aic7860_setup;
147 static ahc_device_setup_t ahc_apa1480_setup;
148 static ahc_device_setup_t ahc_aic7870_setup;
149 static ahc_device_setup_t ahc_aha394X_setup;
150 static ahc_device_setup_t ahc_aha494X_setup;
151 static ahc_device_setup_t ahc_aha398X_setup;
152 static ahc_device_setup_t ahc_aic7880_setup;
153 static ahc_device_setup_t ahc_aha2940Pro_setup;
154 static ahc_device_setup_t ahc_aha394XU_setup;
155 static ahc_device_setup_t ahc_aha398XU_setup;
156 static ahc_device_setup_t ahc_aic7890_setup;
157 static ahc_device_setup_t ahc_aic7892_setup;
158 static ahc_device_setup_t ahc_aic7895_setup;
159 static ahc_device_setup_t ahc_aic7896_setup;
160 static ahc_device_setup_t ahc_aic7899_setup;
161 static ahc_device_setup_t ahc_aha29160C_setup;
162 static ahc_device_setup_t ahc_raid_setup;
163 static ahc_device_setup_t ahc_aha394XX_setup;
164 static ahc_device_setup_t ahc_aha494XX_setup;
165 static ahc_device_setup_t ahc_aha398XX_setup;
167 struct ahc_pci_identity ahc_pci_ident_table [] =
169 /* aic7850 based controllers */
171 ID_AHA_2902_04_10_15_20C_30C,
173 "Adaptec 2902/04/10/15/20C/30C SCSI adapter",
176 /* aic7860 based controllers */
180 "Adaptec 2930CU SCSI adapter",
184 ID_AHA_1480A & ID_DEV_VENDOR_MASK,
186 "Adaptec 1480A Ultra SCSI adapter",
190 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
192 "Adaptec 2940A Ultra SCSI adapter",
196 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
198 "Adaptec 2940A/CN Ultra SCSI adapter",
202 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
204 "Adaptec 2930C Ultra SCSI adapter (VAR)",
207 /* aic7870 based controllers */
211 "Adaptec 2940 SCSI adapter",
217 "Adaptec 3940 SCSI adapter",
223 "Adaptec 398X SCSI RAID adapter",
229 "Adaptec 2944 SCSI adapter",
235 "Adaptec 3944 SCSI adapter",
241 "Adaptec 4944 SCSI adapter",
244 /* aic7880 based controllers */
246 ID_AHA_2940U & ID_DEV_VENDOR_MASK,
248 "Adaptec 2940 Ultra SCSI adapter",
252 ID_AHA_3940U & ID_DEV_VENDOR_MASK,
254 "Adaptec 3940 Ultra SCSI adapter",
258 ID_AHA_2944U & ID_DEV_VENDOR_MASK,
260 "Adaptec 2944 Ultra SCSI adapter",
264 ID_AHA_3944U & ID_DEV_VENDOR_MASK,
266 "Adaptec 3944 Ultra SCSI adapter",
270 ID_AHA_398XU & ID_DEV_VENDOR_MASK,
272 "Adaptec 398X Ultra SCSI RAID adapter",
277 * XXX Don't know the slot numbers
278 * so we can't identify channels
280 ID_AHA_4944U & ID_DEV_VENDOR_MASK,
282 "Adaptec 4944 Ultra SCSI adapter",
286 ID_AHA_2930U & ID_DEV_VENDOR_MASK,
288 "Adaptec 2930 Ultra SCSI adapter",
292 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
294 "Adaptec 2940 Pro Ultra SCSI adapter",
298 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
300 "Adaptec 2940/CN Ultra SCSI adapter",
303 /* Ignore all SISL (AAC on MB) based controllers. */
310 /* aic7890 based controllers */
314 "Adaptec 2930 Ultra2 SCSI adapter",
320 "Adaptec 2940B Ultra2 SCSI adapter",
326 "Adaptec 2940 Ultra2 SCSI adapter (OEM)",
332 "Adaptec 2940 Ultra2 SCSI adapter",
338 "Adaptec 2950 Ultra2 SCSI adapter",
344 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)",
350 "Adaptec AAA-131 Ultra2 RAID adapter",
353 /* aic7892 based controllers */
357 "Adaptec 29160 Ultra160 SCSI adapter",
363 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter",
369 "Adaptec 29160N Ultra160 SCSI adapter",
375 "Adaptec 29160C Ultra160 SCSI adapter",
381 "Adaptec 29160B Ultra160 SCSI adapter",
387 "Adaptec 19160B Ultra160 SCSI adapter",
393 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)",
396 /* aic7895 based controllers */
400 "Adaptec 2940/DUAL Ultra SCSI adapter",
406 "Adaptec 3940A Ultra SCSI adapter",
412 "Adaptec 3944A Ultra SCSI adapter",
418 "Adaptec aic7895 Ultra SCSI adapter (ARO)",
421 /* aic7896/97 based controllers */
425 "Adaptec 3950B Ultra2 SCSI adapter",
431 "Adaptec 3950B Ultra2 SCSI adapter",
437 "Adaptec 3950D Ultra2 SCSI adapter",
443 "Adaptec 3950D Ultra2 SCSI adapter",
449 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)",
452 /* aic7899 based controllers */
456 "Adaptec 3960D Ultra160 SCSI adapter",
462 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter",
468 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
471 /* Generic chip probes for devices we don't know 'exactly' */
473 ID_AIC7850 & ID_DEV_VENDOR_MASK,
475 "Adaptec aic7850 SCSI adapter",
479 ID_AIC7855 & ID_DEV_VENDOR_MASK,
481 "Adaptec aic7855 SCSI adapter",
485 ID_AIC7859 & ID_DEV_VENDOR_MASK,
487 "Adaptec aic7859 SCSI adapter",
491 ID_AIC7860 & ID_DEV_VENDOR_MASK,
493 "Adaptec aic7860 Ultra SCSI adapter",
497 ID_AIC7870 & ID_DEV_VENDOR_MASK,
499 "Adaptec aic7870 SCSI adapter",
503 ID_AIC7880 & ID_DEV_VENDOR_MASK,
505 "Adaptec aic7880 Ultra SCSI adapter",
509 ID_AIC7890 & ID_9005_GENERIC_MASK,
510 ID_9005_GENERIC_MASK,
511 "Adaptec aic7890/91 Ultra2 SCSI adapter",
515 ID_AIC7892 & ID_9005_GENERIC_MASK,
516 ID_9005_GENERIC_MASK,
517 "Adaptec aic7892 Ultra160 SCSI adapter",
521 ID_AIC7895 & ID_DEV_VENDOR_MASK,
523 "Adaptec aic7895 Ultra SCSI adapter",
527 ID_AIC7896 & ID_9005_GENERIC_MASK,
528 ID_9005_GENERIC_MASK,
529 "Adaptec aic7896/97 Ultra2 SCSI adapter",
533 ID_AIC7899 & ID_9005_GENERIC_MASK,
534 ID_9005_GENERIC_MASK,
535 "Adaptec aic7899 Ultra160 SCSI adapter",
539 ID_AIC7810 & ID_DEV_VENDOR_MASK,
541 "Adaptec aic7810 RAID memory controller",
545 ID_AIC7815 & ID_DEV_VENDOR_MASK,
547 "Adaptec aic7815 RAID memory controller",
552 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table);
554 #define AHC_394X_SLOT_CHANNEL_A 4
555 #define AHC_394X_SLOT_CHANNEL_B 5
557 #define AHC_398X_SLOT_CHANNEL_A 4
558 #define AHC_398X_SLOT_CHANNEL_B 8
559 #define AHC_398X_SLOT_CHANNEL_C 12
561 #define AHC_494X_SLOT_CHANNEL_A 4
562 #define AHC_494X_SLOT_CHANNEL_B 5
563 #define AHC_494X_SLOT_CHANNEL_C 6
564 #define AHC_494X_SLOT_CHANNEL_D 7
566 #define DEVCONFIG 0x40
567 #define PCIERRGENDIS 0x80000000ul
568 #define SCBSIZE32 0x00010000ul /* aic789X only */
569 #define REXTVALID 0x00001000ul /* ultra cards only */
570 #define MPORTMODE 0x00000400ul /* aic7870+ only */
571 #define RAMPSM 0x00000200ul /* aic7870+ only */
572 #define VOLSENSE 0x00000100ul
573 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/
574 #define SCBRAMSEL 0x00000080ul
575 #define MRDCEN 0x00000040ul
576 #define EXTSCBTIME 0x00000020ul /* aic7870 only */
577 #define EXTSCBPEN 0x00000010ul /* aic7870 only */
578 #define BERREN 0x00000008ul
579 #define DACEN 0x00000004ul
580 #define STPWLEVEL 0x00000002ul
581 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */
583 #define CSIZE_LATTIME 0x0c
584 #define CACHESIZE 0x0000003ful /* only 5 bits */
585 #define LATTIME 0x0000ff00ul
587 /* PCI STATUS definitions */
595 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device,
596 uint16_t subvendor, uint16_t subdevice);
597 static int ahc_ext_scbram_present(struct ahc_softc *ahc);
598 static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
599 int pcheck, int fast, int large);
600 static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
601 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
602 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc,
603 struct seeprom_config *sc);
604 static void configure_termination(struct ahc_softc *ahc,
605 struct seeprom_descriptor *sd,
606 u_int adapter_control,
609 static void ahc_new_term_detect(struct ahc_softc *ahc,
614 int *eeprom_present);
615 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
616 int *internal68_present,
617 int *externalcable_present,
618 int *eeprom_present);
619 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
620 int *externalcable_present,
621 int *eeprom_present);
622 static void write_brdctl(struct ahc_softc *ahc, uint8_t value);
623 static uint8_t read_brdctl(struct ahc_softc *ahc);
624 static void ahc_pci_intr(struct ahc_softc *ahc);
625 static int ahc_pci_chip_init(struct ahc_softc *ahc);
626 static int ahc_pci_suspend(struct ahc_softc *ahc);
627 static int ahc_pci_resume(struct ahc_softc *ahc);
630 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
631 uint16_t subdevice, uint16_t subvendor)
635 /* Default to invalid. */
638 && subvendor == 0x9005
639 && subdevice != device
640 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
642 switch (SUBID_9005_TYPE(subdevice)) {
643 case SUBID_9005_TYPE_MB:
645 case SUBID_9005_TYPE_CARD:
646 case SUBID_9005_TYPE_LCCARD:
648 * Currently only trust Adaptec cards to
649 * get the sub device info correct.
651 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
654 case SUBID_9005_TYPE_RAID:
663 struct ahc_pci_identity *
664 ahc_find_pci_device(ahc_dev_softc_t pci)
671 struct ahc_pci_identity *entry;
674 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
675 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
676 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
677 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
678 full_id = ahc_compose_id(device, vendor, subdevice, subvendor);
681 * If the second function is not hooked up, ignore it.
682 * Unfortunately, not all MB vendors implement the
683 * subdevice ID as per the Adaptec spec, so do our best
684 * to sanity check it prior to accepting the subdevice
687 if (ahc_get_pci_function(pci) > 0
688 && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice)
689 && SUBID_9005_MFUNCENB(subdevice) == 0)
692 for (i = 0; i < ahc_num_pci_devs; i++) {
693 entry = &ahc_pci_ident_table[i];
694 if (entry->full_id == (full_id & entry->id_mask)) {
695 /* Honor exclusion entries. */
696 if (entry->name == NULL)
705 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
718 error = entry->setup(ahc);
721 ahc->chip |= AHC_PCI;
722 ahc->description = entry->name;
724 pci_set_power_state(ahc->dev_softc, AHC_POWER_STATE_D0);
726 error = ahc_pci_map_registers(ahc);
731 * Before we continue probing the card, ensure that
732 * its interrupts are *disabled*. We don't want
733 * a misstep to hang the machine in an interrupt
736 ahc_intr_enable(ahc, FALSE);
738 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
741 * If we need to support high memory, enable dual
742 * address cycles. This bit must be set to enable
743 * high address bit generation even if we are on a
744 * 64bit bus (PCI64BIT set in devconfig).
746 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
749 printf("%s: Enabling 39Bit Addressing\n",
754 /* Ensure that pci error generation, a test feature, is disabled. */
755 devconfig |= PCIERRGENDIS;
757 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
759 /* Ensure busmastering is enabled */
760 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
761 command |= PCIM_CMD_BUSMASTEREN;
763 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
765 /* On all PCI adapters, we allow SCB paging */
766 ahc->flags |= AHC_PAGESCBS;
768 error = ahc_softc_init(ahc);
773 * Disable PCI parity error checking. Users typically
774 * do this to work around broken PCI chipsets that get
775 * the parity timing wrong and thus generate lots of spurious
776 * errors. The chip only allows us to disable *all* parity
777 * error reporting when doing this, so CIO bus, scb ram, and
778 * scratch ram parity errors will be ignored too.
780 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0)
781 ahc->seqctl |= FAILDIS;
783 ahc->bus_intr = ahc_pci_intr;
784 ahc->bus_chip_init = ahc_pci_chip_init;
785 ahc->bus_suspend = ahc_pci_suspend;
786 ahc->bus_resume = ahc_pci_resume;
788 /* Remeber how the card was setup in case there is no SEEPROM */
789 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
791 if ((ahc->features & AHC_ULTRA2) != 0)
792 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
794 our_id = ahc_inb(ahc, SCSIID) & OID;
795 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
796 scsiseq = ahc_inb(ahc, SCSISEQ);
803 error = ahc_reset(ahc, /*reinit*/FALSE);
807 if ((ahc->features & AHC_DT) != 0) {
810 /* Perform ALT-Mode Setup */
811 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
812 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
813 ahc_outb(ahc, OPTIONMODE,
814 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
815 ahc_outb(ahc, SFUNCT, sfunct);
817 /* Normal mode setup */
818 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
822 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
823 dscommand0 |= MPARCKEN|CACHETHEN;
824 if ((ahc->features & AHC_ULTRA2) != 0) {
827 * DPARCKEN doesn't work correctly on
828 * some MBs so don't use it.
830 dscommand0 &= ~DPARCKEN;
834 * Handle chips that must have cache line
835 * streaming (dis/en)abled.
837 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
838 dscommand0 |= CACHETHEN;
840 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
841 dscommand0 &= ~CACHETHEN;
843 ahc_outb(ahc, DSCOMMAND0, dscommand0);
846 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME,
847 /*bytes*/1) & CACHESIZE;
848 ahc->pci_cachesize *= 4;
850 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
851 && ahc->pci_cachesize == 4) {
853 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
855 ahc->pci_cachesize = 0;
859 * We cannot perform ULTRA speeds without the presense
860 * of the external precision resistor.
862 if ((ahc->features & AHC_ULTRA) != 0) {
865 devconfig = ahc_pci_read_config(ahc->dev_softc,
866 DEVCONFIG, /*bytes*/4);
867 if ((devconfig & REXTVALID) == 0)
868 ahc->features &= ~AHC_ULTRA;
871 /* See if we have a SEEPROM and perform auto-term */
872 check_extport(ahc, &sxfrctl1);
875 * Take the LED out of diagnostic mode
877 sblkctl = ahc_inb(ahc, SBLKCTL);
878 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
880 if ((ahc->features & AHC_ULTRA2) != 0) {
881 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
883 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
886 if (ahc->flags & AHC_USEDEFAULTS) {
888 * PCI Adapter default setup
889 * Should only be used if the adapter does not have
892 /* See if someone else set us up already */
893 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
895 printf("%s: Using left over BIOS settings\n",
897 ahc->flags &= ~AHC_USEDEFAULTS;
898 ahc->flags |= AHC_BIOS_ENABLED;
901 * Assume only one connector and always turn
907 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
909 ahc->our_id = our_id;
913 * Take a look to see if we have external SRAM.
914 * We currently do not attempt to use SRAM that is
915 * shared among multiple controllers.
917 ahc_probe_ext_scbram(ahc);
920 * Record our termination setting for the
921 * generic initialization routine.
923 if ((sxfrctl1 & STPWEN) != 0)
924 ahc->flags |= AHC_TERM_ENB_A;
927 * Save chip register configuration data for chip resets
928 * that occur during runtime and resume events.
930 ahc->bus_softc.pci_softc.devconfig =
931 ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
932 ahc->bus_softc.pci_softc.command =
933 ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
934 ahc->bus_softc.pci_softc.csize_lattime =
935 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1);
936 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
937 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
938 if ((ahc->features & AHC_DT) != 0) {
941 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
942 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
943 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE);
944 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT);
945 ahc_outb(ahc, SFUNCT, sfunct);
946 ahc->bus_softc.pci_softc.crccontrol1 =
947 ahc_inb(ahc, CRCCONTROL1);
949 if ((ahc->features & AHC_MULTI_FUNC) != 0)
950 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR);
952 if ((ahc->features & AHC_ULTRA2) != 0)
953 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
955 /* Core initialization */
956 error = ahc_init(ahc);
961 * Allow interrupts now that we are completely setup.
963 error = ahc_pci_map_int(ahc);
969 * Link this softc in with all other ahc instances.
971 ahc_softc_insert(ahc);
977 * Test for the presense of external sram in an
978 * "unshared" configuration.
981 ahc_ext_scbram_present(struct ahc_softc *ahc)
988 chip = ahc->chip & AHC_CHIPID_MASK;
989 devconfig = ahc_pci_read_config(ahc->dev_softc,
990 DEVCONFIG, /*bytes*/4);
991 single_user = (devconfig & MPORTMODE) != 0;
993 if ((ahc->features & AHC_ULTRA2) != 0)
994 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
995 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
997 * External SCBRAM arbitration is flakey
998 * on these chips. Unfortunately this means
999 * we don't use the extra SCB ram space on the
1003 else if (chip >= AHC_AIC7870)
1004 ramps = (devconfig & RAMPSM) != 0;
1008 if (ramps && single_user)
1014 * Enable external scbram.
1017 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
1018 int fast, int large)
1022 if (ahc->features & AHC_MULTI_FUNC) {
1024 * Set the SCB Base addr (highest address bit)
1025 * depending on which channel we are.
1027 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc));
1030 ahc->flags &= ~AHC_LSCBS_ENABLED;
1032 ahc->flags |= AHC_LSCBS_ENABLED;
1033 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1034 if ((ahc->features & AHC_ULTRA2) != 0) {
1037 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1039 dscommand0 &= ~INTSCBRAMSEL;
1041 dscommand0 |= INTSCBRAMSEL;
1043 dscommand0 &= ~USCBSIZE32;
1045 dscommand0 |= USCBSIZE32;
1046 ahc_outb(ahc, DSCOMMAND0, dscommand0);
1049 devconfig &= ~EXTSCBTIME;
1051 devconfig |= EXTSCBTIME;
1053 devconfig &= ~SCBRAMSEL;
1055 devconfig |= SCBRAMSEL;
1057 devconfig &= ~SCBSIZE32;
1059 devconfig |= SCBSIZE32;
1062 devconfig |= EXTSCBPEN;
1064 devconfig &= ~EXTSCBPEN;
1066 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
1070 * Take a look to see if we have external SRAM.
1071 * We currently do not attempt to use SRAM that is
1072 * shared among multiple controllers.
1075 ahc_probe_ext_scbram(struct ahc_softc *ahc)
1090 if (ahc_ext_scbram_present(ahc) == 0)
1094 * Probe for the best parameters to use.
1096 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
1097 num_scbs = ahc_probe_scbs(ahc);
1098 if (num_scbs == 0) {
1099 /* The SRAM wasn't really present. */
1105 * Clear any outstanding parity error
1106 * and ensure that parity error reporting
1109 ahc_outb(ahc, SEQCTL, 0);
1110 ahc_outb(ahc, CLRINT, CLRPARERR);
1111 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1113 /* Now see if we can do parity */
1114 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
1115 num_scbs = ahc_probe_scbs(ahc);
1116 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1117 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
1120 /* Clear any resulting parity error */
1121 ahc_outb(ahc, CLRINT, CLRPARERR);
1122 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1124 /* Now see if we can do fast timing */
1125 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
1126 test_num_scbs = ahc_probe_scbs(ahc);
1127 if (test_num_scbs == num_scbs
1128 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1129 || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
1133 * See if we can use large SCBs and still maintain
1134 * the same overall count of SCBs.
1136 if ((ahc->features & AHC_LARGE_SCBS) != 0) {
1137 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
1138 test_num_scbs = ahc_probe_scbs(ahc);
1139 if (test_num_scbs >= num_scbs) {
1141 num_scbs = test_num_scbs;
1142 if (num_scbs >= 64) {
1144 * We have enough space to move the
1145 * "busy targets table" into SCB space
1146 * and make it qualify all the way to the
1149 ahc->flags |= AHC_SCB_BTT;
1155 * Disable parity error reporting until we
1156 * can load instruction ram.
1158 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1159 /* Clear any latched parity error */
1160 ahc_outb(ahc, CLRINT, CLRPARERR);
1161 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1162 if (bootverbose && enable) {
1163 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n",
1164 ahc_name(ahc), fast ? "fast" : "slow",
1165 pcheck ? ", parity checking enabled" : "",
1168 ahc_scbram_config(ahc, enable, pcheck, fast, large);
1172 * Perform some simple tests that should catch situations where
1173 * our registers are invalidly mapped.
1176 ahc_pci_test_register_access(struct ahc_softc *ahc)
1186 * Enable PCI error interrupt status, but suppress NMIs
1187 * generated by SERR raised due to target aborts.
1189 cmd = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
1190 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
1191 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
1194 * First a simple test to see if any
1195 * registers can be read. Reading
1196 * HCNTRL has no side effects and has
1197 * at least one bit that is guaranteed to
1198 * be zero so it is a good register to
1199 * use for this test.
1201 hcntrl = ahc_inb(ahc, HCNTRL);
1206 * Next create a situation where write combining
1207 * or read prefetching could be initiated by the
1208 * CPU or host bridge. Our device does not support
1209 * either, so look for data corruption and/or flagged
1210 * PCI errors. First pause without causing another
1214 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
1215 while (ahc_is_paused(ahc) == 0)
1218 /* Clear any PCI errors that occurred before our driver attached. */
1219 status1 = ahc_pci_read_config(ahc->dev_softc,
1220 PCIR_STATUS + 1, /*bytes*/1);
1221 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1222 status1, /*bytes*/1);
1223 ahc_outb(ahc, CLRINT, CLRPARERR);
1225 ahc_outb(ahc, SEQCTL, PERRORDIS);
1226 ahc_outb(ahc, SCBPTR, 0);
1227 ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
1228 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
1231 status1 = ahc_pci_read_config(ahc->dev_softc,
1232 PCIR_STATUS + 1, /*bytes*/1);
1233 if ((status1 & STA) != 0)
1239 /* Silently clear any latched errors. */
1240 status1 = ahc_pci_read_config(ahc->dev_softc,
1241 PCIR_STATUS + 1, /*bytes*/1);
1242 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1243 status1, /*bytes*/1);
1244 ahc_outb(ahc, CLRINT, CLRPARERR);
1245 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1246 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
1251 * Check the external port logic for a serial eeprom
1252 * and termination/cable detection contrls.
1255 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
1257 struct seeprom_descriptor sd;
1258 struct seeprom_config *sc;
1263 sd.sd_control_offset = SEECTL;
1264 sd.sd_status_offset = SEECTL;
1265 sd.sd_dataout_offset = SEECTL;
1266 sc = ahc->seep_config;
1269 * For some multi-channel devices, the c46 is simply too
1270 * small to work. For the other controller types, we can
1271 * get our information from either SEEPROM type. Set the
1272 * type to start our probe with accordingly.
1274 if (ahc->flags & AHC_LARGE_SEEPROM)
1275 sd.sd_chip = C56_66;
1286 have_seeprom = ahc_acquire_seeprom(ahc, &sd);
1290 printf("%s: Reading SEEPROM...", ahc_name(ahc));
1295 start_addr = 32 * (ahc->channel - 'A');
1297 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
1302 have_seeprom = ahc_verify_cksum(sc);
1304 if (have_seeprom != 0 || sd.sd_chip == C56_66) {
1306 if (have_seeprom == 0)
1307 printf ("checksum error\n");
1313 sd.sd_chip = C56_66;
1315 ahc_release_seeprom(&sd);
1318 if (!have_seeprom) {
1320 * Pull scratch ram settings and treat them as
1321 * if they are the contents of an seeprom if
1322 * the 'ADPT' signature is found in SCB2.
1323 * We manually compose the data as 16bit values
1324 * to avoid endian issues.
1326 ahc_outb(ahc, SCBPTR, 2);
1327 if (ahc_inb(ahc, SCB_BASE) == 'A'
1328 && ahc_inb(ahc, SCB_BASE + 1) == 'D'
1329 && ahc_inb(ahc, SCB_BASE + 2) == 'P'
1330 && ahc_inb(ahc, SCB_BASE + 3) == 'T') {
1334 sc_data = (uint16_t *)sc;
1335 for (i = 0; i < 32; i++, sc_data++) {
1339 *sc_data = ahc_inb(ahc, SRAM_BASE + j)
1340 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
1342 have_seeprom = ahc_verify_cksum(sc);
1344 ahc->flags |= AHC_SCB_CONFIG_USED;
1347 * Clear any SCB parity errors in case this data and
1348 * its associated parity was not initialized by the BIOS
1350 ahc_outb(ahc, CLRINT, CLRPARERR);
1351 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1354 if (!have_seeprom) {
1356 printf("%s: No SEEPROM available.\n", ahc_name(ahc));
1357 ahc->flags |= AHC_USEDEFAULTS;
1358 free(ahc->seep_config, M_DEVBUF);
1359 ahc->seep_config = NULL;
1362 ahc_parse_pci_eeprom(ahc, sc);
1366 * Cards that have the external logic necessary to talk to
1367 * a SEEPROM, are almost certain to have the remaining logic
1368 * necessary for auto-termination control. This assumption
1369 * hasn't failed yet...
1371 have_autoterm = have_seeprom;
1374 * Some low-cost chips have SEEPROM and auto-term control built
1375 * in, instead of using a GAL. They can tell us directly
1376 * if the termination logic is enabled.
1378 if ((ahc->features & AHC_SPIOCAP) != 0) {
1379 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0)
1380 have_autoterm = FALSE;
1383 if (have_autoterm) {
1384 ahc->flags |= AHC_HAS_TERM_LOGIC;
1385 ahc_acquire_seeprom(ahc, &sd);
1386 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1);
1387 ahc_release_seeprom(&sd);
1388 } else if (have_seeprom) {
1389 *sxfrctl1 &= ~STPWEN;
1390 if ((sc->adapter_control & CFSTERM) != 0)
1391 *sxfrctl1 |= STPWEN;
1393 printf("%s: Low byte termination %sabled\n",
1395 (*sxfrctl1 & STPWEN) ? "en" : "dis");
1400 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc)
1403 * Put the data we've collected down into SRAM
1404 * where ahc_init will find it.
1407 int max_targ = sc->max_targets & CFMAXTARG;
1409 uint16_t discenable;
1414 if ((sc->adapter_control & CFULTRAEN) != 0) {
1416 * Determine if this adapter has a "newstyle"
1419 for (i = 0; i < max_targ; i++) {
1420 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) {
1421 ahc->flags |= AHC_NEWEEPROM_FMT;
1427 for (i = 0; i < max_targ; i++) {
1429 uint16_t target_mask;
1431 target_mask = 0x01 << i;
1432 if (sc->device_flags[i] & CFDISC)
1433 discenable |= target_mask;
1434 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
1435 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0)
1436 ultraenb |= target_mask;
1437 } else if ((sc->adapter_control & CFULTRAEN) != 0) {
1438 ultraenb |= target_mask;
1440 if ((sc->device_flags[i] & CFXFER) == 0x04
1441 && (ultraenb & target_mask) != 0) {
1442 /* Treat 10MHz as a non-ultra speed */
1443 sc->device_flags[i] &= ~CFXFER;
1444 ultraenb &= ~target_mask;
1446 if ((ahc->features & AHC_ULTRA2) != 0) {
1449 if (sc->device_flags[i] & CFSYNCH)
1450 offset = MAX_OFFSET_ULTRA2;
1453 ahc_outb(ahc, TARG_OFFSET + i, offset);
1456 * The ultra enable bits contain the
1457 * high bit of the ultra2 sync rate
1460 scsirate = (sc->device_flags[i] & CFXFER)
1461 | ((ultraenb & target_mask) ? 0x8 : 0x0);
1462 if (sc->device_flags[i] & CFWIDEB)
1463 scsirate |= WIDEXFER;
1465 scsirate = (sc->device_flags[i] & CFXFER) << 4;
1466 if (sc->device_flags[i] & CFSYNCH)
1468 if (sc->device_flags[i] & CFWIDEB)
1469 scsirate |= WIDEXFER;
1471 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
1473 ahc->our_id = sc->brtime_id & CFSCSIID;
1475 scsi_conf = (ahc->our_id & 0x7);
1476 if (sc->adapter_control & CFSPARITY)
1477 scsi_conf |= ENSPCHK;
1478 if (sc->adapter_control & CFRESETB)
1479 scsi_conf |= RESET_SCSI;
1481 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
1483 if (sc->bios_control & CFEXTEND)
1484 ahc->flags |= AHC_EXTENDED_TRANS_A;
1486 if (sc->bios_control & CFBIOSEN)
1487 ahc->flags |= AHC_BIOS_ENABLED;
1488 if (ahc->features & AHC_ULTRA
1489 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
1490 /* Should we enable Ultra mode? */
1491 if (!(sc->adapter_control & CFULTRAEN))
1492 /* Treat us as a non-ultra card */
1496 if (sc->signature == CFSIGNATURE
1497 || sc->signature == CFSIGNATURE2) {
1500 /* Honor the STPWLEVEL settings */
1501 devconfig = ahc_pci_read_config(ahc->dev_softc,
1502 DEVCONFIG, /*bytes*/4);
1503 devconfig &= ~STPWLEVEL;
1504 if ((sc->bios_control & CFSTPWLEVEL) != 0)
1505 devconfig |= STPWLEVEL;
1506 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG,
1507 devconfig, /*bytes*/4);
1509 /* Set SCSICONF info */
1510 ahc_outb(ahc, SCSICONF, scsi_conf);
1511 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
1512 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
1513 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
1514 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
1518 configure_termination(struct ahc_softc *ahc,
1519 struct seeprom_descriptor *sd,
1520 u_int adapter_control,
1528 * Update the settings in sxfrctl1 to match the
1529 * termination settings
1534 * SEECS must be on for the GALS to latch
1535 * the data properly. Be sure to leave MS
1536 * on or we will release the seeprom.
1538 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS);
1539 if ((adapter_control & CFAUTOTERM) != 0
1540 || (ahc->features & AHC_NEW_TERMCTL) != 0) {
1541 int internal50_present;
1542 int internal68_present;
1543 int externalcable_present;
1555 if ((ahc->features & AHC_NEW_TERMCTL) != 0) {
1556 ahc_new_term_detect(ahc, &enableSEC_low,
1561 if ((adapter_control & CFSEAUTOTERM) == 0) {
1563 printf("%s: Manual SE Termination\n",
1565 enableSEC_low = (adapter_control & CFSELOWTERM);
1567 (adapter_control & CFSEHIGHTERM);
1569 if ((adapter_control & CFAUTOTERM) == 0) {
1571 printf("%s: Manual LVD Termination\n",
1573 enablePRI_low = (adapter_control & CFSTERM);
1574 enablePRI_high = (adapter_control & CFWSTERM);
1576 /* Make the table calculations below happy */
1577 internal50_present = 0;
1578 internal68_present = 1;
1579 externalcable_present = 1;
1580 } else if ((ahc->features & AHC_SPIOCAP) != 0) {
1581 aic785X_cable_detect(ahc, &internal50_present,
1582 &externalcable_present,
1584 /* Can never support a wide connector. */
1585 internal68_present = 0;
1587 aic787X_cable_detect(ahc, &internal50_present,
1588 &internal68_present,
1589 &externalcable_present,
1593 if ((ahc->features & AHC_WIDE) == 0)
1594 internal68_present = 0;
1597 && (ahc->features & AHC_ULTRA2) == 0) {
1598 printf("%s: internal 50 cable %s present",
1600 internal50_present ? "is":"not");
1602 if ((ahc->features & AHC_WIDE) != 0)
1603 printf(", internal 68 cable %s present",
1604 internal68_present ? "is":"not");
1605 printf("\n%s: external cable %s present\n",
1607 externalcable_present ? "is":"not");
1610 printf("%s: BIOS eeprom %s present\n",
1611 ahc_name(ahc), eeprom_present ? "is" : "not");
1613 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) {
1615 * The 50 pin connector is a separate bus,
1616 * so force it to always be terminated.
1617 * In the future, perform current sensing
1618 * to determine if we are in the middle of
1619 * a properly terminated bus.
1621 internal50_present = 0;
1625 * Now set the termination based on what
1627 * Flash Enable = BRDDAT7
1628 * Secondary High Term Enable = BRDDAT6
1629 * Secondary Low Term Enable = BRDDAT5 (7890)
1630 * Primary High Term Enable = BRDDAT4 (7890)
1632 if ((ahc->features & AHC_ULTRA2) == 0
1633 && (internal50_present != 0)
1634 && (internal68_present != 0)
1635 && (externalcable_present != 0)) {
1636 printf("%s: Illegal cable configuration!!. "
1637 "Only two connectors on the "
1638 "adapter may be used at a "
1639 "time!\n", ahc_name(ahc));
1642 * Pretend there are no cables in the hope
1643 * that having all of the termination on
1644 * gives us a more stable bus.
1646 internal50_present = 0;
1647 internal68_present = 0;
1648 externalcable_present = 0;
1651 if ((ahc->features & AHC_WIDE) != 0
1652 && ((externalcable_present == 0)
1653 || (internal68_present == 0)
1654 || (enableSEC_high != 0))) {
1657 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1658 printf("%s: 68 pin termination "
1659 "Enabled\n", ahc_name(ahc));
1661 printf("%s: %sHigh byte termination "
1662 "Enabled\n", ahc_name(ahc),
1663 enableSEC_high ? "Secondary "
1668 sum = internal50_present + internal68_present
1669 + externalcable_present;
1670 if (sum < 2 || (enableSEC_low != 0)) {
1671 if ((ahc->features & AHC_ULTRA2) != 0)
1674 *sxfrctl1 |= STPWEN;
1676 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1677 printf("%s: 50 pin termination "
1678 "Enabled\n", ahc_name(ahc));
1680 printf("%s: %sLow byte termination "
1681 "Enabled\n", ahc_name(ahc),
1682 enableSEC_low ? "Secondary "
1687 if (enablePRI_low != 0) {
1688 *sxfrctl1 |= STPWEN;
1690 printf("%s: Primary Low Byte termination "
1691 "Enabled\n", ahc_name(ahc));
1695 * Setup STPWEN before setting up the rest of
1696 * the termination per the tech note on the U160 cards.
1698 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1700 if (enablePRI_high != 0) {
1703 printf("%s: Primary High Byte "
1704 "termination Enabled\n",
1708 write_brdctl(ahc, brddat);
1711 if ((adapter_control & CFSTERM) != 0) {
1712 *sxfrctl1 |= STPWEN;
1715 printf("%s: %sLow byte termination Enabled\n",
1717 (ahc->features & AHC_ULTRA2) ? "Primary "
1721 if ((adapter_control & CFWSTERM) != 0
1722 && (ahc->features & AHC_WIDE) != 0) {
1725 printf("%s: %sHigh byte termination Enabled\n",
1727 (ahc->features & AHC_ULTRA2)
1728 ? "Secondary " : "");
1732 * Setup STPWEN before setting up the rest of
1733 * the termination per the tech note on the U160 cards.
1735 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1737 if ((ahc->features & AHC_WIDE) != 0)
1738 write_brdctl(ahc, brddat);
1740 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */
1744 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low,
1745 int *enableSEC_high, int *enablePRI_low,
1746 int *enablePRI_high, int *eeprom_present)
1752 * BRDDAT6 = Enable Secondary High Byte termination
1753 * BRDDAT5 = Enable Secondary Low Byte termination
1754 * BRDDAT4 = Enable Primary high byte termination
1755 * BRDDAT3 = Enable Primary low byte termination
1757 brdctl = read_brdctl(ahc);
1758 *eeprom_present = brdctl & BRDDAT7;
1759 *enableSEC_high = (brdctl & BRDDAT6);
1760 *enableSEC_low = (brdctl & BRDDAT5);
1761 *enablePRI_high = (brdctl & BRDDAT4);
1762 *enablePRI_low = (brdctl & BRDDAT3);
1766 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1767 int *internal68_present, int *externalcable_present,
1768 int *eeprom_present)
1773 * First read the status of our cables.
1774 * Set the rom bank to 0 since the
1775 * bank setting serves as a multiplexor
1776 * for the cable detection logic.
1777 * BRDDAT5 controls the bank switch.
1779 write_brdctl(ahc, 0);
1782 * Now read the state of the internal
1783 * connectors. BRDDAT6 is INT50 and
1786 brdctl = read_brdctl(ahc);
1787 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1;
1788 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1;
1791 * Set the rom bank to 1 and determine
1792 * the other signals.
1794 write_brdctl(ahc, BRDDAT5);
1797 * Now read the state of the external
1798 * connectors. BRDDAT6 is EXT68 and
1799 * BRDDAT7 is EPROMPS.
1801 brdctl = read_brdctl(ahc);
1802 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1803 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0;
1807 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1808 int *externalcable_present, int *eeprom_present)
1813 spiocap = ahc_inb(ahc, SPIOCAP);
1814 spiocap &= ~SOFTCMDEN;
1815 spiocap |= EXT_BRDCTL;
1816 ahc_outb(ahc, SPIOCAP, spiocap);
1817 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS);
1818 ahc_flush_device_writes(ahc);
1820 ahc_outb(ahc, BRDCTL, 0);
1821 ahc_flush_device_writes(ahc);
1823 brdctl = ahc_inb(ahc, BRDCTL);
1824 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1;
1825 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1826 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0;
1830 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd)
1834 if ((ahc->features & AHC_SPIOCAP) != 0
1835 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0)
1839 * Request access of the memory port. When access is
1840 * granted, SEERDY will go high. We use a 1 second
1841 * timeout which should be near 1 second more than
1842 * is needed. Reason: after the chip reset, there
1843 * should be no contention.
1845 SEEPROM_OUTB(sd, sd->sd_MS);
1846 wait = 1000; /* 1 second timeout in msec */
1847 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) {
1848 ahc_delay(1000); /* delay 1 msec */
1850 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) {
1851 SEEPROM_OUTB(sd, 0);
1858 ahc_release_seeprom(struct seeprom_descriptor *sd)
1860 /* Release access to the memory port and the serial EEPROM. */
1861 SEEPROM_OUTB(sd, 0);
1865 write_brdctl(struct ahc_softc *ahc, uint8_t value)
1869 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1871 if (ahc->channel == 'B')
1873 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1876 brdctl = BRDSTB|BRDCS;
1878 ahc_outb(ahc, BRDCTL, brdctl);
1879 ahc_flush_device_writes(ahc);
1881 ahc_outb(ahc, BRDCTL, brdctl);
1882 ahc_flush_device_writes(ahc);
1883 if ((ahc->features & AHC_ULTRA2) != 0)
1884 brdctl |= BRDSTB_ULTRA2;
1887 ahc_outb(ahc, BRDCTL, brdctl);
1888 ahc_flush_device_writes(ahc);
1889 if ((ahc->features & AHC_ULTRA2) != 0)
1893 ahc_outb(ahc, BRDCTL, brdctl);
1897 read_brdctl(struct ahc_softc *ahc)
1902 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1904 if (ahc->channel == 'B')
1906 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1907 brdctl = BRDRW_ULTRA2;
1909 brdctl = BRDRW|BRDCS;
1911 ahc_outb(ahc, BRDCTL, brdctl);
1912 ahc_flush_device_writes(ahc);
1913 value = ahc_inb(ahc, BRDCTL);
1914 ahc_outb(ahc, BRDCTL, 0);
1919 ahc_pci_intr(struct ahc_softc *ahc)
1924 error = ahc_inb(ahc, ERROR);
1925 if ((error & PCIERRSTAT) == 0)
1928 status1 = ahc_pci_read_config(ahc->dev_softc,
1929 PCIR_STATUS + 1, /*bytes*/1);
1931 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n",
1933 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
1935 if (status1 & DPE) {
1936 ahc->pci_target_perr_count++;
1937 printf("%s: Data Parity Error Detected during address "
1938 "or write data phase\n", ahc_name(ahc));
1940 if (status1 & SSE) {
1941 printf("%s: Signal System Error Detected\n", ahc_name(ahc));
1943 if (status1 & RMA) {
1944 printf("%s: Received a Master Abort\n", ahc_name(ahc));
1946 if (status1 & RTA) {
1947 printf("%s: Received a Target Abort\n", ahc_name(ahc));
1949 if (status1 & STA) {
1950 printf("%s: Signaled a Target Abort\n", ahc_name(ahc));
1952 if (status1 & DPR) {
1953 printf("%s: Data Parity Error has been reported via PERR#\n",
1957 /* Clear latched errors. */
1958 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1959 status1, /*bytes*/1);
1961 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
1962 printf("%s: Latched PCIERR interrupt with "
1963 "no status bits set\n", ahc_name(ahc));
1965 ahc_outb(ahc, CLRINT, CLRPARERR);
1968 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH) {
1970 "%s: WARNING WARNING WARNING WARNING\n"
1971 "%s: Too many PCI parity errors observed as a target.\n"
1972 "%s: Some device on this bus is generating bad parity.\n"
1973 "%s: This is an error *observed by*, not *generated by*, this controller.\n"
1974 "%s: PCI parity error checking has been disabled.\n"
1975 "%s: WARNING WARNING WARNING WARNING\n",
1976 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
1977 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc));
1978 ahc->seqctl |= FAILDIS;
1979 ahc_outb(ahc, SEQCTL, ahc->seqctl);
1985 ahc_pci_chip_init(struct ahc_softc *ahc)
1987 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0);
1988 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus);
1989 if ((ahc->features & AHC_DT) != 0) {
1992 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
1993 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
1994 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode);
1995 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt);
1996 ahc_outb(ahc, SFUNCT, sfunct);
1997 ahc_outb(ahc, CRCCONTROL1,
1998 ahc->bus_softc.pci_softc.crccontrol1);
2000 if ((ahc->features & AHC_MULTI_FUNC) != 0)
2001 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr);
2003 if ((ahc->features & AHC_ULTRA2) != 0)
2004 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh);
2006 return (ahc_chip_init(ahc));
2010 ahc_pci_suspend(struct ahc_softc *ahc)
2012 return (ahc_suspend(ahc));
2016 ahc_pci_resume(struct ahc_softc *ahc)
2019 pci_set_power_state(ahc->dev_softc, AHC_POWER_STATE_D0);
2022 * We assume that the OS has restored our register
2023 * mappings, etc. Just update the config space registers
2024 * that the OS doesn't know about and rely on our chip
2025 * reset handler to handle the rest.
2027 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4,
2028 ahc->bus_softc.pci_softc.devconfig);
2029 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1,
2030 ahc->bus_softc.pci_softc.command);
2031 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1,
2032 ahc->bus_softc.pci_softc.csize_lattime);
2033 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) {
2034 struct seeprom_descriptor sd;
2038 sd.sd_control_offset = SEECTL;
2039 sd.sd_status_offset = SEECTL;
2040 sd.sd_dataout_offset = SEECTL;
2042 ahc_acquire_seeprom(ahc, &sd);
2043 configure_termination(ahc, &sd,
2044 ahc->seep_config->adapter_control,
2046 ahc_release_seeprom(&sd);
2048 return (ahc_resume(ahc));
2052 ahc_aic785X_setup(struct ahc_softc *ahc)
2054 ahc_dev_softc_t pci;
2057 pci = ahc->dev_softc;
2059 ahc->chip = AHC_AIC7850;
2060 ahc->features = AHC_AIC7850_FE;
2061 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2062 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2064 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2065 ahc->instruction_ram_size = 512;
2070 ahc_aic7860_setup(struct ahc_softc *ahc)
2072 ahc_dev_softc_t pci;
2075 pci = ahc->dev_softc;
2077 ahc->chip = AHC_AIC7860;
2078 ahc->features = AHC_AIC7860_FE;
2079 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2080 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2082 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2083 ahc->instruction_ram_size = 512;
2088 ahc_apa1480_setup(struct ahc_softc *ahc)
2092 error = ahc_aic7860_setup(ahc);
2095 ahc->features |= AHC_REMOVABLE;
2100 ahc_aic7870_setup(struct ahc_softc *ahc)
2104 ahc->chip = AHC_AIC7870;
2105 ahc->features = AHC_AIC7870_FE;
2106 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2107 ahc->instruction_ram_size = 512;
2112 ahc_aha394X_setup(struct ahc_softc *ahc)
2116 error = ahc_aic7870_setup(ahc);
2118 error = ahc_aha394XX_setup(ahc);
2123 ahc_aha398X_setup(struct ahc_softc *ahc)
2127 error = ahc_aic7870_setup(ahc);
2129 error = ahc_aha398XX_setup(ahc);
2134 ahc_aha494X_setup(struct ahc_softc *ahc)
2138 error = ahc_aic7870_setup(ahc);
2140 error = ahc_aha494XX_setup(ahc);
2145 ahc_aic7880_setup(struct ahc_softc *ahc)
2147 ahc_dev_softc_t pci;
2150 pci = ahc->dev_softc;
2152 ahc->chip = AHC_AIC7880;
2153 ahc->features = AHC_AIC7880_FE;
2154 ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
2155 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2157 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2159 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2161 ahc->instruction_ram_size = 512;
2166 ahc_aha2940Pro_setup(struct ahc_softc *ahc)
2169 ahc->flags |= AHC_INT50_SPEEDFLEX;
2170 return (ahc_aic7880_setup(ahc));
2174 ahc_aha394XU_setup(struct ahc_softc *ahc)
2178 error = ahc_aic7880_setup(ahc);
2180 error = ahc_aha394XX_setup(ahc);
2185 ahc_aha398XU_setup(struct ahc_softc *ahc)
2189 error = ahc_aic7880_setup(ahc);
2191 error = ahc_aha398XX_setup(ahc);
2196 ahc_aic7890_setup(struct ahc_softc *ahc)
2198 ahc_dev_softc_t pci;
2201 pci = ahc->dev_softc;
2203 ahc->chip = AHC_AIC7890;
2204 ahc->features = AHC_AIC7890_FE;
2205 ahc->flags |= AHC_NEWEEPROM_FMT;
2206 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2208 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
2209 ahc->instruction_ram_size = 768;
2214 ahc_aic7892_setup(struct ahc_softc *ahc)
2218 ahc->chip = AHC_AIC7892;
2219 ahc->features = AHC_AIC7892_FE;
2220 ahc->flags |= AHC_NEWEEPROM_FMT;
2221 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2222 ahc->instruction_ram_size = 1024;
2227 ahc_aic7895_setup(struct ahc_softc *ahc)
2229 ahc_dev_softc_t pci;
2232 pci = ahc->dev_softc;
2233 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2235 * The 'C' revision of the aic7895 has a few additional features.
2237 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2239 ahc->chip = AHC_AIC7895C;
2240 ahc->features = AHC_AIC7895C_FE;
2244 ahc->chip = AHC_AIC7895;
2245 ahc->features = AHC_AIC7895_FE;
2248 * The BIOS disables the use of MWI transactions
2249 * since it does not have the MWI bug work around
2250 * we have. Disabling MWI reduces performance, so
2253 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1);
2254 command |= PCIM_CMD_MWRICEN;
2255 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1);
2256 ahc->bugs |= AHC_PCI_MWI_BUG;
2259 * XXX Does CACHETHEN really not work??? What about PCI retry?
2260 * on C level chips. Need to test, but for now, play it safe.
2262 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
2263 | AHC_CACHETHEN_BUG;
2269 * Cachesize must also be zero due to stray DAC
2270 * problem when sitting behind some bridges.
2272 ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1);
2273 devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1);
2274 devconfig |= MRDCEN;
2275 ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1);
2277 ahc->flags |= AHC_NEWEEPROM_FMT;
2278 ahc->instruction_ram_size = 512;
2283 ahc_aic7896_setup(struct ahc_softc *ahc)
2285 ahc_dev_softc_t pci;
2287 pci = ahc->dev_softc;
2288 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2289 ahc->chip = AHC_AIC7896;
2290 ahc->features = AHC_AIC7896_FE;
2291 ahc->flags |= AHC_NEWEEPROM_FMT;
2292 ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
2293 ahc->instruction_ram_size = 768;
2298 ahc_aic7899_setup(struct ahc_softc *ahc)
2300 ahc_dev_softc_t pci;
2302 pci = ahc->dev_softc;
2303 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2304 ahc->chip = AHC_AIC7899;
2305 ahc->features = AHC_AIC7899_FE;
2306 ahc->flags |= AHC_NEWEEPROM_FMT;
2307 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2308 ahc->instruction_ram_size = 1024;
2313 ahc_aha29160C_setup(struct ahc_softc *ahc)
2317 error = ahc_aic7899_setup(ahc);
2320 ahc->features |= AHC_REMOVABLE;
2325 ahc_raid_setup(struct ahc_softc *ahc)
2327 printf("RAID functionality unsupported\n");
2332 ahc_aha394XX_setup(struct ahc_softc *ahc)
2334 ahc_dev_softc_t pci;
2336 pci = ahc->dev_softc;
2337 switch (ahc_get_pci_slot(pci)) {
2338 case AHC_394X_SLOT_CHANNEL_A:
2341 case AHC_394X_SLOT_CHANNEL_B:
2345 printf("adapter at unexpected slot %d\n"
2346 "unable to map to a channel\n",
2347 ahc_get_pci_slot(pci));
2354 ahc_aha398XX_setup(struct ahc_softc *ahc)
2356 ahc_dev_softc_t pci;
2358 pci = ahc->dev_softc;
2359 switch (ahc_get_pci_slot(pci)) {
2360 case AHC_398X_SLOT_CHANNEL_A:
2363 case AHC_398X_SLOT_CHANNEL_B:
2366 case AHC_398X_SLOT_CHANNEL_C:
2370 printf("adapter at unexpected slot %d\n"
2371 "unable to map to a channel\n",
2372 ahc_get_pci_slot(pci));
2376 ahc->flags |= AHC_LARGE_SEEPROM;
2381 ahc_aha494XX_setup(struct ahc_softc *ahc)
2383 ahc_dev_softc_t pci;
2385 pci = ahc->dev_softc;
2386 switch (ahc_get_pci_slot(pci)) {
2387 case AHC_494X_SLOT_CHANNEL_A:
2390 case AHC_494X_SLOT_CHANNEL_B:
2393 case AHC_494X_SLOT_CHANNEL_C:
2396 case AHC_494X_SLOT_CHANNEL_D:
2400 printf("adapter at unexpected slot %d\n"
2401 "unable to map to a channel\n",
2402 ahc_get_pci_slot(pci));
2405 ahc->flags |= AHC_LARGE_SEEPROM;