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   1 /* linux/arch/arm/mach-s3c2440/mach-osiris.c
   2  *
   3  * Copyright (c) 2005,2008 Simtec Electronics
   4  *      http://armlinux.simtec.co.uk/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/timer.h>
  17 #include <linux/init.h>
  18 #include <linux/device.h>
  19 #include <linux/sysdev.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/clk.h>
  22 #include <linux/i2c.h>
  23 #include <linux/io.h>
  24
  25 #include <asm/mach/arch.h>
  26 #include <asm/mach/map.h>
  27 #include <asm/mach/irq.h>
  28
  29 #include <mach/osiris-map.h>
  30 #include <mach/osiris-cpld.h>
  31
  32 #include <mach/hardware.h>
  33 #include <asm/irq.h>
  34 #include <asm/mach-types.h>
  35
  36 #include <plat/regs-serial.h>
  37 #include <mach/regs-gpio.h>
  38 #include <mach/regs-mem.h>
  39 #include <mach/regs-lcd.h>
  40 #include <plat/nand.h>
  41 #include <plat/iic.h>
  42
  43 #include <linux/mtd/mtd.h>
  44 #include <linux/mtd/nand.h>
  45 #include <linux/mtd/nand_ecc.h>
  46 #include <linux/mtd/partitions.h>
  47
  48 #include <plat/clock.h>
  49 #include <plat/devs.h>
  50 #include <plat/cpu.h>
  51
  52 /* onboard perihperal map */
  53
  54 static struct map_desc osiris_iodesc[] __initdata = {
  55   /* ISA IO areas (may be over-written later) */
  56
  57   {
  58           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
  59           .pfn          = __phys_to_pfn(S3C2410_CS5),
  60           .length       = SZ_16M,
  61           .type         = MT_DEVICE,
  62   }, {
  63           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
  64           .pfn          = __phys_to_pfn(S3C2410_CS5),
  65           .length       = SZ_16M,
  66           .type         = MT_DEVICE,
  67   },
  68
  69   /* CPLD control registers */
  70
  71   {
  72           .virtual      = (u32)OSIRIS_VA_CTRL0,
  73           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL0),
  74           .length       = SZ_16K,
  75           .type         = MT_DEVICE,
  76   }, {
  77           .virtual      = (u32)OSIRIS_VA_CTRL1,
  78           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL1),
  79           .length       = SZ_16K,
  80           .type         = MT_DEVICE,
  81   }, {
  82           .virtual      = (u32)OSIRIS_VA_CTRL2,
  83           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL2),
  84           .length       = SZ_16K,
  85           .type         = MT_DEVICE,
  86   }, {
  87           .virtual      = (u32)OSIRIS_VA_IDREG,
  88           .pfn          = __phys_to_pfn(OSIRIS_PA_IDREG),
  89           .length       = SZ_16K,
  90           .type         = MT_DEVICE,
  91   },
  92 };
  93
  94 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
  95 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  96 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  97
  98 static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
  99         [0] = {
 100                 .name           = "uclk",
 101                 .divisor        = 1,
 102                 .min_baud       = 0,
 103                 .max_baud       = 0,
 104         },
 105         [1] = {
 106                 .name           = "pclk",
 107                 .divisor        = 1,
 108                 .min_baud       = 0,
 109                 .max_baud       = 0,
 110         }
 111 };
 112
 113 static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
 114         [0] = {
 115                 .hwport      = 0,
 116                 .flags       = 0,
 117                 .ucon        = UCON,
 118                 .ulcon       = ULCON,
 119                 .ufcon       = UFCON,
 120                 .clocks      = osiris_serial_clocks,
 121                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 122         },
 123         [1] = {
 124                 .hwport      = 1,
 125                 .flags       = 0,
 126                 .ucon        = UCON,
 127                 .ulcon       = ULCON,
 128                 .ufcon       = UFCON,
 129                 .clocks      = osiris_serial_clocks,
 130                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 131         },
 132         [2] = {
 133                 .hwport      = 2,
 134                 .flags       = 0,
 135                 .ucon        = UCON,
 136                 .ulcon       = ULCON,
 137                 .ufcon       = UFCON,
 138                 .clocks      = osiris_serial_clocks,
 139                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 140         }
 141 };
 142
 143 /* NAND Flash on Osiris board */
 144
 145 static int external_map[]   = { 2 };
 146 static int chip0_map[]      = { 0 };
 147 static int chip1_map[]      = { 1 };
 148
 149 static struct mtd_partition osiris_default_nand_part[] = {
 150         [0] = {
 151                 .name   = "Boot Agent",
 152                 .size   = SZ_16K,
 153                 .offset = 0,
 154         },
 155         [1] = {
 156                 .name   = "/boot",
 157                 .size   = SZ_4M - SZ_16K,
 158                 .offset = SZ_16K,
 159         },
 160         [2] = {
 161                 .name   = "user1",
 162                 .offset = SZ_4M,
 163                 .size   = SZ_32M - SZ_4M,
 164         },
 165         [3] = {
 166                 .name   = "user2",
 167                 .offset = SZ_32M,
 168                 .size   = MTDPART_SIZ_FULL,
 169         }
 170 };
 171
 172 static struct mtd_partition osiris_default_nand_part_large[] = {
 173         [0] = {
 174                 .name   = "Boot Agent",
 175                 .size   = SZ_128K,
 176                 .offset = 0,
 177         },
 178         [1] = {
 179                 .name   = "/boot",
 180                 .size   = SZ_4M - SZ_128K,
 181                 .offset = SZ_128K,
 182         },
 183         [2] = {
 184                 .name   = "user1",
 185                 .offset = SZ_4M,
 186                 .size   = SZ_32M - SZ_4M,
 187         },
 188         [3] = {
 189                 .name   = "user2",
 190                 .offset = SZ_32M,
 191                 .size   = MTDPART_SIZ_FULL,
 192         }
 193 };
 194
 195 /* the Osiris has 3 selectable slots for nand-flash, the two
 196  * on-board chip areas, as well as the external slot.
 197  *
 198  * Note, there is no current hot-plug support for the External
 199  * socket.
 200 */
 201
 202 static struct s3c2410_nand_set osiris_nand_sets[] = {
 203         [1] = {
 204                 .name           = "External",
 205                 .nr_chips       = 1,
 206                 .nr_map         = external_map,
 207                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 208                 .partitions     = osiris_default_nand_part,
 209         },
 210         [0] = {
 211                 .name           = "chip0",
 212                 .nr_chips       = 1,
 213                 .nr_map         = chip0_map,
 214                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 215                 .partitions     = osiris_default_nand_part,
 216         },
 217         [2] = {
 218                 .name           = "chip1",
 219                 .nr_chips       = 1,
 220                 .nr_map         = chip1_map,
 221                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 222                 .partitions     = osiris_default_nand_part,
 223         },
 224 };
 225
 226 static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
 227 {
 228         unsigned int tmp;
 229
 230         slot = set->nr_map[slot] & 3;
 231
 232         pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
 233                  slot, set, set->nr_map);
 234
 235         tmp = __raw_readb(OSIRIS_VA_CTRL0);
 236         tmp &= ~OSIRIS_CTRL0_NANDSEL;
 237         tmp |= slot;
 238
 239         pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
 240
 241         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 242 }
 243
 244 static struct s3c2410_platform_nand osiris_nand_info = {
 245         .tacls          = 25,
 246         .twrph0         = 60,
 247         .twrph1         = 60,
 248         .nr_sets        = ARRAY_SIZE(osiris_nand_sets),
 249         .sets           = osiris_nand_sets,
 250         .select_chip    = osiris_nand_select,
 251 };
 252
 253 /* PCMCIA control and configuration */
 254
 255 static struct resource osiris_pcmcia_resource[] = {
 256         [0] = {
 257                 .start  = 0x0f000000,
 258                 .end    = 0x0f100000,
 259                 .flags  = IORESOURCE_MEM,
 260         },
 261         [1] = {
 262                 .start  = 0x0c000000,
 263                 .end    = 0x0c100000,
 264                 .flags  = IORESOURCE_MEM,
 265         }
 266 };
 267
 268 static struct platform_device osiris_pcmcia = {
 269         .name           = "osiris-pcmcia",
 270         .id             = -1,
 271         .num_resources  = ARRAY_SIZE(osiris_pcmcia_resource),
 272         .resource       = osiris_pcmcia_resource,
 273 };
 274
 275 /* Osiris power management device */
 276
 277 #ifdef CONFIG_PM
 278 static unsigned char pm_osiris_ctrl0;
 279
 280 static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
 281 {
 282         unsigned int tmp;
 283
 284         pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
 285         tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
 286
 287         /* ensure correct NAND slot is selected on resume */
 288         if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
 289                 tmp |= 2;
 290
 291         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 292
 293         /* ensure that an nRESET is not generated on resume. */
 294         s3c2410_gpio_setpin(S3C2410_GPA21, 1);
 295         s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);
 296
 297         return 0;
 298 }
 299
 300 static int osiris_pm_resume(struct sys_device *sd)
 301 {
 302         if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
 303                 __raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
 304
 305         __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
 306
 307         s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
 308
 309         return 0;
 310 }
 311
 312 #else
 313 #define osiris_pm_suspend NULL
 314 #define osiris_pm_resume NULL
 315 #endif
 316
 317 static struct sysdev_class osiris_pm_sysclass = {
 318         .name           = "mach-osiris",
 319         .suspend        = osiris_pm_suspend,
 320         .resume         = osiris_pm_resume,
 321 };
 322
 323 static struct sys_device osiris_pm_sysdev = {
 324         .cls            = &osiris_pm_sysclass,
 325 };
 326
 327 /* I2C devices fitted. */
 328
 329 static struct i2c_board_info osiris_i2c_devs[] __initdata = {
 330         {
 331                 I2C_BOARD_INFO("tps65011", 0x48),
 332                 .irq    = IRQ_EINT20,
 333         },
 334 };
 335
 336 /* Standard Osiris devices */
 337
 338 static struct platform_device *osiris_devices[] __initdata = {
 339         &s3c_device_i2c0,
 340         &s3c_device_wdt,
 341         &s3c_device_nand,
 342         &osiris_pcmcia,
 343 };
 344
 345 static struct clk *osiris_clocks[] __initdata = {
 346         &s3c24xx_dclk0,
 347         &s3c24xx_dclk1,
 348         &s3c24xx_clkout0,
 349         &s3c24xx_clkout1,
 350         &s3c24xx_uclk,
 351 };
 352
 353 static void __init osiris_map_io(void)
 354 {
 355         unsigned long flags;
 356
 357         /* initialise the clocks */
 358
 359         s3c24xx_dclk0.parent = &clk_upll;
 360         s3c24xx_dclk0.rate   = 12*1000*1000;
 361
 362         s3c24xx_dclk1.parent = &clk_upll;
 363         s3c24xx_dclk1.rate   = 24*1000*1000;
 364
 365         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
 366         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
 367
 368         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 369
 370         s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
 371
 372         s3c_device_nand.dev.platform_data = &osiris_nand_info;
 373
 374         s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
 375         s3c24xx_init_clocks(0);
 376         s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
 377
 378         /* check for the newer revision boards with large page nand */
 379
 380         if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
 381                 printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
 382                        __raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
 383                 osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
 384                 osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
 385         } else {
 386                 /* write-protect line to the NAND */
 387                 s3c2410_gpio_setpin(S3C2410_GPA0, 1);
 388         }
 389
 390         /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
 391
 392         local_irq_save(flags);
 393         __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
 394         local_irq_restore(flags);
 395 }
 396
 397 static void __init osiris_init(void)
 398 {
 399         sysdev_class_register(&osiris_pm_sysclass);
 400         sysdev_register(&osiris_pm_sysdev);
 401
 402         s3c_i2c0_set_platdata(NULL);
 403
 404         i2c_register_board_info(0, osiris_i2c_devs,
 405                                 ARRAY_SIZE(osiris_i2c_devs));
 406
 407         platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
 408 };
 409
 410 MACHINE_START(OSIRIS, "Simtec-OSIRIS")
 411         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 412         .phys_io        = S3C2410_PA_UART,
 413         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
 414         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 415         .map_io         = osiris_map_io,
 416         .init_irq       = s3c24xx_init_irq,
 417         .init_machine   = osiris_init,
 418         .timer          = &s3c24xx_timer,
 419 MACHINE_END