git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/rt2x00/rt2500pci.c

   1 /*
   2         Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500pci
  23         Abstract: rt2500pci device specific routines.
  24         Supported chipsets: RT2560.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2500pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00pci_register_read and rt2x00pci_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 #define WAIT_FOR_BBP(__dev, __reg) \
  53         rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
  54 #define WAIT_FOR_RF(__dev, __reg) \
  55         rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
  56
  57 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  58                                 const unsigned int word, const u8 value)
  59 {
  60         u32 reg;
  61
  62         mutex_lock(&rt2x00dev->csr_mutex);
  63
  64         /*
  65          * Wait until the BBP becomes available, afterwards we
  66          * can safely write the new data into the register.
  67          */
  68         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  69                 reg = 0;
  70                 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  71                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  72                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  73                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  74
  75                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  76         }
  77
  78         mutex_unlock(&rt2x00dev->csr_mutex);
  79 }
  80
  81 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  82                                const unsigned int word, u8 *value)
  83 {
  84         u32 reg;
  85
  86         mutex_lock(&rt2x00dev->csr_mutex);
  87
  88         /*
  89          * Wait until the BBP becomes available, afterwards we
  90          * can safely write the read request into the register.
  91          * After the data has been written, we wait until hardware
  92          * returns the correct value, if at any time the register
  93          * doesn't become available in time, reg will be 0xffffffff
  94          * which means we return 0xff to the caller.
  95          */
  96         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  97                 reg = 0;
  98                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  99                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 100                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 101
 102                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 103
 104                 WAIT_FOR_BBP(rt2x00dev, &reg);
 105         }
 106
 107         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
 113                                const unsigned int word, const u32 value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the RF becomes available, afterwards we
 121          * can safely write the new data into the register.
 122          */
 123         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 124                 reg = 0;
 125                 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 126                 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 127                 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 128                 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 129
 130                 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 131                 rt2x00_rf_write(rt2x00dev, word, value);
 132         }
 133
 134         mutex_unlock(&rt2x00dev->csr_mutex);
 135 }
 136
 137 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 138 {
 139         struct rt2x00_dev *rt2x00dev = eeprom->data;
 140         u32 reg;
 141
 142         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 143
 144         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 145         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 146         eeprom->reg_data_clock =
 147             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 148         eeprom->reg_chip_select =
 149             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 150 }
 151
 152 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 153 {
 154         struct rt2x00_dev *rt2x00dev = eeprom->data;
 155         u32 reg = 0;
 156
 157         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 158         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 159         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 160                            !!eeprom->reg_data_clock);
 161         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 162                            !!eeprom->reg_chip_select);
 163
 164         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 165 }
 166
 167 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 168 static const struct rt2x00debug rt2500pci_rt2x00debug = {
 169         .owner  = THIS_MODULE,
 170         .csr    = {
 171                 .read           = rt2x00pci_register_read,
 172                 .write          = rt2x00pci_register_write,
 173                 .flags          = RT2X00DEBUGFS_OFFSET,
 174                 .word_base      = CSR_REG_BASE,
 175                 .word_size      = sizeof(u32),
 176                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 177         },
 178         .eeprom = {
 179                 .read           = rt2x00_eeprom_read,
 180                 .write          = rt2x00_eeprom_write,
 181                 .word_base      = EEPROM_BASE,
 182                 .word_size      = sizeof(u16),
 183                 .word_count     = EEPROM_SIZE / sizeof(u16),
 184         },
 185         .bbp    = {
 186                 .read           = rt2500pci_bbp_read,
 187                 .write          = rt2500pci_bbp_write,
 188                 .word_base      = BBP_BASE,
 189                 .word_size      = sizeof(u8),
 190                 .word_count     = BBP_SIZE / sizeof(u8),
 191         },
 192         .rf     = {
 193                 .read           = rt2x00_rf_read,
 194                 .write          = rt2500pci_rf_write,
 195                 .word_base      = RF_BASE,
 196                 .word_size      = sizeof(u32),
 197                 .word_count     = RF_SIZE / sizeof(u32),
 198         },
 199 };
 200 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 201
 202 #ifdef CONFIG_RT2X00_LIB_RFKILL
 203 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 204 {
 205         u32 reg;
 206
 207         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 208         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 209 }
 210 #else
 211 #define rt2500pci_rfkill_poll   NULL
 212 #endif /* CONFIG_RT2X00_LIB_RFKILL */
 213
 214 #ifdef CONFIG_RT2X00_LIB_LEDS
 215 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
 216                                      enum led_brightness brightness)
 217 {
 218         struct rt2x00_led *led =
 219             container_of(led_cdev, struct rt2x00_led, led_dev);
 220         unsigned int enabled = brightness != LED_OFF;
 221         u32 reg;
 222
 223         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 224
 225         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 226                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 227         else if (led->type == LED_TYPE_ACTIVITY)
 228                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 229
 230         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 231 }
 232
 233 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
 234                                unsigned long *delay_on,
 235                                unsigned long *delay_off)
 236 {
 237         struct rt2x00_led *led =
 238             container_of(led_cdev, struct rt2x00_led, led_dev);
 239         u32 reg;
 240
 241         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 242         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 243         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 244         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 245
 246         return 0;
 247 }
 248
 249 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
 250                                struct rt2x00_led *led,
 251                                enum led_type type)
 252 {
 253         led->rt2x00dev = rt2x00dev;
 254         led->type = type;
 255         led->led_dev.brightness_set = rt2500pci_brightness_set;
 256         led->led_dev.blink_set = rt2500pci_blink_set;
 257         led->flags = LED_INITIALIZED;
 258 }
 259 #endif /* CONFIG_RT2X00_LIB_LEDS */
 260
 261 /*
 262  * Configuration handlers.
 263  */
 264 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
 265                                     const unsigned int filter_flags)
 266 {
 267         u32 reg;
 268
 269         /*
 270          * Start configuration steps.
 271          * Note that the version error will always be dropped
 272          * and broadcast frames will always be accepted since
 273          * there is no filter for it at this time.
 274          */
 275         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 276         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 277                            !(filter_flags & FIF_FCSFAIL));
 278         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 279                            !(filter_flags & FIF_PLCPFAIL));
 280         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 281                            !(filter_flags & FIF_CONTROL));
 282         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 283                            !(filter_flags & FIF_PROMISC_IN_BSS));
 284         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 285                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 286                            !rt2x00dev->intf_ap_count);
 287         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 288         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
 289                            !(filter_flags & FIF_ALLMULTI));
 290         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
 291         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 292 }
 293
 294 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
 295                                   struct rt2x00_intf *intf,
 296                                   struct rt2x00intf_conf *conf,
 297                                   const unsigned int flags)
 298 {
 299         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
 300         unsigned int bcn_preload;
 301         u32 reg;
 302
 303         if (flags & CONFIG_UPDATE_TYPE) {
 304                 /*
 305                  * Enable beacon config
 306                  */
 307                 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
 308                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 309                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 310                 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
 311                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 312
 313                 /*
 314                  * Enable synchronisation.
 315                  */
 316                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 317                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 318                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 319                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 320                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 321         }
 322
 323         if (flags & CONFIG_UPDATE_MAC)
 324                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 325                                               conf->mac, sizeof(conf->mac));
 326
 327         if (flags & CONFIG_UPDATE_BSSID)
 328                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 329                                               conf->bssid, sizeof(conf->bssid));
 330 }
 331
 332 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
 333                                  struct rt2x00lib_erp *erp)
 334 {
 335         int preamble_mask;
 336         u32 reg;
 337
 338         /*
 339          * When short preamble is enabled, we should set bit 0x08
 340          */
 341         preamble_mask = erp->short_preamble << 3;
 342
 343         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 344         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, erp->ack_timeout);
 345         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
 346                            erp->ack_consume_time);
 347         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 348         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 349         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 350
 351         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 352         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 353         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 354         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
 355         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 356
 357         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 358         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 359         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 360         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
 361         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 362
 363         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 364         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 365         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 366         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
 367         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 368
 369         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 370         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 371         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 372         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
 373         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 374
 375         rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
 376
 377         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 378         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
 379         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 380
 381         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 382         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);
 383         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);
 384         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 385
 386         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 387         rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
 388         rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
 389         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 390
 391         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 392         rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
 393         rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
 394         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 395 }
 396
 397 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
 398                                  struct antenna_setup *ant)
 399 {
 400         u32 reg;
 401         u8 r14;
 402         u8 r2;
 403
 404         /*
 405          * We should never come here because rt2x00lib is supposed
 406          * to catch this and send us the correct antenna explicitely.
 407          */
 408         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 409                ant->tx == ANTENNA_SW_DIVERSITY);
 410
 411         rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
 412         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
 413         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
 414
 415         /*
 416          * Configure the TX antenna.
 417          */
 418         switch (ant->tx) {
 419         case ANTENNA_A:
 420                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
 421                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
 422                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
 423                 break;
 424         case ANTENNA_B:
 425         default:
 426                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 427                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 428                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 429                 break;
 430         }
 431
 432         /*
 433          * Configure the RX antenna.
 434          */
 435         switch (ant->rx) {
 436         case ANTENNA_A:
 437                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
 438                 break;
 439         case ANTENNA_B:
 440         default:
 441                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 442                 break;
 443         }
 444
 445         /*
 446          * RT2525E and RT5222 need to flip TX I/Q
 447          */
 448         if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
 449             rt2x00_rf(&rt2x00dev->chip, RF5222)) {
 450                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
 451                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
 452                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
 453
 454                 /*
 455                  * RT2525E does not need RX I/Q Flip.
 456                  */
 457                 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
 458                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
 459         } else {
 460                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
 461                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
 462         }
 463
 464         rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
 465         rt2500pci_bbp_write(rt2x00dev, 14, r14);
 466         rt2500pci_bbp_write(rt2x00dev, 2, r2);
 467 }
 468
 469 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
 470                                      struct rf_channel *rf, const int txpower)
 471 {
 472         u8 r70;
 473
 474         /*
 475          * Set TXpower.
 476          */
 477         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 478
 479         /*
 480          * Switch on tuning bits.
 481          * For RT2523 devices we do not need to update the R1 register.
 482          */
 483         if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
 484                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 485         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 486
 487         /*
 488          * For RT2525 we should first set the channel to half band higher.
 489          */
 490         if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
 491                 static const u32 vals[] = {
 492                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
 493                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
 494                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
 495                         0x00080d2e, 0x00080d3a
 496                 };
 497
 498                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 499                 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
 500                 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 501                 if (rf->rf4)
 502                         rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 503         }
 504
 505         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 506         rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
 507         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 508         if (rf->rf4)
 509                 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 510
 511         /*
 512          * Channel 14 requires the Japan filter bit to be set.
 513          */
 514         r70 = 0x46;
 515         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
 516         rt2500pci_bbp_write(rt2x00dev, 70, r70);
 517
 518         msleep(1);
 519
 520         /*
 521          * Switch off tuning bits.
 522          * For RT2523 devices we do not need to update the R1 register.
 523          */
 524         if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
 525                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 526                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 527         }
 528
 529         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 530         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 531
 532         /*
 533          * Clear false CRC during channel switch.
 534          */
 535         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 536 }
 537
 538 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 539                                      const int txpower)
 540 {
 541         u32 rf3;
 542
 543         rt2x00_rf_read(rt2x00dev, 3, &rf3);
 544         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 545         rt2500pci_rf_write(rt2x00dev, 3, rf3);
 546 }
 547
 548 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 549                                          struct rt2x00lib_conf *libconf)
 550 {
 551         u32 reg;
 552
 553         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 554         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
 555                            libconf->conf->long_frame_max_tx_count);
 556         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
 557                            libconf->conf->short_frame_max_tx_count);
 558         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 559 }
 560
 561 static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
 562                                 struct rt2x00lib_conf *libconf)
 563 {
 564         enum dev_state state =
 565             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 566                 STATE_SLEEP : STATE_AWAKE;
 567         u32 reg;
 568
 569         if (state == STATE_SLEEP) {
 570                 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
 571                 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
 572                                    (rt2x00dev->beacon_int - 20) * 16);
 573                 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
 574                                    libconf->conf->listen_interval - 1);
 575
 576                 /* We must first disable autowake before it can be enabled */
 577                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
 578                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
 579
 580                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
 581                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
 582         }
 583
 584         rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 585 }
 586
 587 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
 588                              struct rt2x00lib_conf *libconf,
 589                              const unsigned int flags)
 590 {
 591         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 592                 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
 593                                          libconf->conf->power_level);
 594         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
 595             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
 596                 rt2500pci_config_txpower(rt2x00dev,
 597                                          libconf->conf->power_level);
 598         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 599                 rt2500pci_config_retry_limit(rt2x00dev, libconf);
 600         if (flags & IEEE80211_CONF_CHANGE_PS)
 601                 rt2500pci_config_ps(rt2x00dev, libconf);
 602 }
 603
 604 /*
 605  * Link tuning
 606  */
 607 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
 608                                  struct link_qual *qual)
 609 {
 610         u32 reg;
 611
 612         /*
 613          * Update FCS error count from register.
 614          */
 615         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 616         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 617
 618         /*
 619          * Update False CCA count from register.
 620          */
 621         rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
 622         qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
 623 }
 624
 625 static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev,
 626                                      struct link_qual *qual, u8 vgc_level)
 627 {
 628         if (qual->vgc_level_reg != vgc_level) {
 629                 rt2500pci_bbp_write(rt2x00dev, 17, vgc_level);
 630                 qual->vgc_level_reg = vgc_level;
 631         }
 632 }
 633
 634 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
 635                                   struct link_qual *qual)
 636 {
 637         rt2500pci_set_vgc(rt2x00dev, qual, 0x48);
 638 }
 639
 640 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev,
 641                                  struct link_qual *qual, const u32 count)
 642 {
 643         /*
 644          * To prevent collisions with MAC ASIC on chipsets
 645          * up to version C the link tuning should halt after 20
 646          * seconds while being associated.
 647          */
 648         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
 649             rt2x00dev->intf_associated && count > 20)
 650                 return;
 651
 652         /*
 653          * Chipset versions C and lower should directly continue
 654          * to the dynamic CCA tuning. Chipset version D and higher
 655          * should go straight to dynamic CCA tuning when they
 656          * are not associated.
 657          */
 658         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
 659             !rt2x00dev->intf_associated)
 660                 goto dynamic_cca_tune;
 661
 662         /*
 663          * A too low RSSI will cause too much false CCA which will
 664          * then corrupt the R17 tuning. To remidy this the tuning should
 665          * be stopped (While making sure the R17 value will not exceed limits)
 666          */
 667         if (qual->rssi < -80 && count > 20) {
 668                 if (qual->vgc_level_reg >= 0x41)
 669                         rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
 670                 return;
 671         }
 672
 673         /*
 674          * Special big-R17 for short distance
 675          */
 676         if (qual->rssi >= -58) {
 677                 rt2500pci_set_vgc(rt2x00dev, qual, 0x50);
 678                 return;
 679         }
 680
 681         /*
 682          * Special mid-R17 for middle distance
 683          */
 684         if (qual->rssi >= -74) {
 685                 rt2500pci_set_vgc(rt2x00dev, qual, 0x41);
 686                 return;
 687         }
 688
 689         /*
 690          * Leave short or middle distance condition, restore r17
 691          * to the dynamic tuning range.
 692          */
 693         if (qual->vgc_level_reg >= 0x41) {
 694                 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
 695                 return;
 696         }
 697
 698 dynamic_cca_tune:
 699
 700         /*
 701          * R17 is inside the dynamic tuning range,
 702          * start tuning the link based on the false cca counter.
 703          */
 704         if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40) {
 705                 rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg);
 706                 qual->vgc_level = qual->vgc_level_reg;
 707         } else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32) {
 708                 rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg);
 709                 qual->vgc_level = qual->vgc_level_reg;
 710         }
 711 }
 712
 713 /*
 714  * Initialization functions.
 715  */
 716 static bool rt2500pci_get_entry_state(struct queue_entry *entry)
 717 {
 718         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 719         u32 word;
 720
 721         if (entry->queue->qid == QID_RX) {
 722                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 723
 724                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
 725         } else {
 726                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 727
 728                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
 729                         rt2x00_get_field32(word, TXD_W0_VALID));
 730         }
 731 }
 732
 733 static void rt2500pci_clear_entry(struct queue_entry *entry)
 734 {
 735         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 736         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 737         u32 word;
 738
 739         if (entry->queue->qid == QID_RX) {
 740                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 741                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
 742                 rt2x00_desc_write(entry_priv->desc, 1, word);
 743
 744                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 745                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 746                 rt2x00_desc_write(entry_priv->desc, 0, word);
 747         } else {
 748                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 749                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 750                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 751                 rt2x00_desc_write(entry_priv->desc, 0, word);
 752         }
 753 }
 754
 755 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
 756 {
 757         struct queue_entry_priv_pci *entry_priv;
 758         u32 reg;
 759
 760         /*
 761          * Initialize registers.
 762          */
 763         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 764         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 765         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 766         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 767         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 768         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 769
 770         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 771         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 772         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 773                            entry_priv->desc_dma);
 774         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 775
 776         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 777         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 778         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 779                            entry_priv->desc_dma);
 780         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 781
 782         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
 783         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 784         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 785                            entry_priv->desc_dma);
 786         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 787
 788         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
 789         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 790         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 791                            entry_priv->desc_dma);
 792         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 793
 794         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 795         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 796         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 797         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 798
 799         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 800         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 801         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 802                            entry_priv->desc_dma);
 803         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 804
 805         return 0;
 806 }
 807
 808 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
 809 {
 810         u32 reg;
 811
 812         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 813         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 814         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
 815         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 816
 817         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 818         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 819         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 820         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 821         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 822
 823         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 824         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 825                            rt2x00dev->rx->data_size / 128);
 826         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 827
 828         /*
 829          * Always use CWmin and CWmax set in descriptor.
 830          */
 831         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 832         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
 833         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 834
 835         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 836         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 837         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 838         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 839         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
 840         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
 841         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 842         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
 843         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
 844         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 845
 846         rt2x00pci_register_write(rt2x00dev, CNT3, 0);
 847
 848         rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
 849         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
 850         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
 851         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
 852         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
 853         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
 854         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
 855         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
 856         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
 857         rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
 858
 859         rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
 860         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
 861         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
 862         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
 863         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
 864         rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
 865
 866         rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
 867         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
 868         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
 869         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
 870         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
 871         rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
 872
 873         rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
 874         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
 875         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
 876         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
 877         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
 878         rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
 879
 880         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 881         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
 882         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 883         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
 884         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 885         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
 886         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 887         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
 888         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
 889         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 890
 891         rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
 892         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
 893         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
 894         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
 895         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
 896         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
 897         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
 898         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
 899         rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
 900
 901         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 902
 903         rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
 904         rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
 905
 906         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 907                 return -EBUSY;
 908
 909         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
 910         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 911
 912         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 913         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 914         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 915
 916         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 917         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 918         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
 919         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
 920         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 921         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
 922         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
 923         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 924
 925         rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
 926
 927         rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
 928
 929         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 930         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 931         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 932         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 933         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 934
 935         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 936         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 937         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 938         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 939
 940         /*
 941          * We must clear the FCS and FIFO error count.
 942          * These registers are cleared on read,
 943          * so we may pass a useless variable to store the value.
 944          */
 945         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 946         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 947
 948         return 0;
 949 }
 950
 951 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
 952 {
 953         unsigned int i;
 954         u8 value;
 955
 956         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 957                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
 958                 if ((value != 0xff) && (value != 0x00))
 959                         return 0;
 960                 udelay(REGISTER_BUSY_DELAY);
 961         }
 962
 963         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 964         return -EACCES;
 965 }
 966
 967 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 968 {
 969         unsigned int i;
 970         u16 eeprom;
 971         u8 reg_id;
 972         u8 value;
 973
 974         if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
 975                 return -EACCES;
 976
 977         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
 978         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
 979         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
 980         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
 981         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
 982         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
 983         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
 984         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
 985         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
 986         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
 987         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
 988         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
 989         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
 990         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
 991         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
 992         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
 993         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
 994         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
 995         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
 996         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
 997         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
 998         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
 999         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
1000         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1001         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1002         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1003         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1004         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1005         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1006         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1007
1008         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1009                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1010
1011                 if (eeprom != 0xffff && eeprom != 0x0000) {
1012                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1013                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1014                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1015                 }
1016         }
1017
1018         return 0;
1019 }
1020
1021 /*
1022  * Device state switch handlers.
1023  */
1024 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1025                                 enum dev_state state)
1026 {
1027         u32 reg;
1028
1029         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1030         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1031                            (state == STATE_RADIO_RX_OFF) ||
1032                            (state == STATE_RADIO_RX_OFF_LINK));
1033         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1034 }
1035
1036 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1037                                  enum dev_state state)
1038 {
1039         int mask = (state == STATE_RADIO_IRQ_OFF);
1040         u32 reg;
1041
1042         /*
1043          * When interrupts are being enabled, the interrupt registers
1044          * should clear the register to assure a clean state.
1045          */
1046         if (state == STATE_RADIO_IRQ_ON) {
1047                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1048                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1049         }
1050
1051         /*
1052          * Only toggle the interrupts bits we are going to use.
1053          * Non-checked interrupt bits are disabled by default.
1054          */
1055         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1056         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1057         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1058         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1059         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1060         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1061         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1062 }
1063
1064 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1065 {
1066         /*
1067          * Initialize all registers.
1068          */
1069         if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1070                      rt2500pci_init_registers(rt2x00dev) ||
1071                      rt2500pci_init_bbp(rt2x00dev)))
1072                 return -EIO;
1073
1074         return 0;
1075 }
1076
1077 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1078 {
1079         /*
1080          * Disable power
1081          */
1082         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1083 }
1084
1085 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1086                                enum dev_state state)
1087 {
1088         u32 reg;
1089         unsigned int i;
1090         char put_to_sleep;
1091         char bbp_state;
1092         char rf_state;
1093
1094         put_to_sleep = (state != STATE_AWAKE);
1095
1096         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1097         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1098         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1099         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1100         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1101         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1102
1103         /*
1104          * Device is not guaranteed to be in the requested state yet.
1105          * We must wait until the register indicates that the
1106          * device has entered the correct state.
1107          */
1108         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1109                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1110                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1111                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1112                 if (bbp_state == state && rf_state == state)
1113                         return 0;
1114                 msleep(10);
1115         }
1116
1117         return -EBUSY;
1118 }
1119
1120 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1121                                       enum dev_state state)
1122 {
1123         int retval = 0;
1124
1125         switch (state) {
1126         case STATE_RADIO_ON:
1127                 retval = rt2500pci_enable_radio(rt2x00dev);
1128                 break;
1129         case STATE_RADIO_OFF:
1130                 rt2500pci_disable_radio(rt2x00dev);
1131                 break;
1132         case STATE_RADIO_RX_ON:
1133         case STATE_RADIO_RX_ON_LINK:
1134         case STATE_RADIO_RX_OFF:
1135         case STATE_RADIO_RX_OFF_LINK:
1136                 rt2500pci_toggle_rx(rt2x00dev, state);
1137                 break;
1138         case STATE_RADIO_IRQ_ON:
1139         case STATE_RADIO_IRQ_OFF:
1140                 rt2500pci_toggle_irq(rt2x00dev, state);
1141                 break;
1142         case STATE_DEEP_SLEEP:
1143         case STATE_SLEEP:
1144         case STATE_STANDBY:
1145         case STATE_AWAKE:
1146                 retval = rt2500pci_set_state(rt2x00dev, state);
1147                 break;
1148         default:
1149                 retval = -ENOTSUPP;
1150                 break;
1151         }
1152
1153         if (unlikely(retval))
1154                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1155                       state, retval);
1156
1157         return retval;
1158 }
1159
1160 /*
1161  * TX descriptor initialization
1162  */
1163 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1164                                     struct sk_buff *skb,
1165                                     struct txentry_desc *txdesc)
1166 {
1167         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1168         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1169         __le32 *txd = skbdesc->desc;
1170         u32 word;
1171
1172         /*
1173          * Start writing the descriptor words.
1174          */
1175         rt2x00_desc_read(entry_priv->desc, 1, &word);
1176         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1177         rt2x00_desc_write(entry_priv->desc, 1, word);
1178
1179         rt2x00_desc_read(txd, 2, &word);
1180         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1181         rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1182         rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1183         rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1184         rt2x00_desc_write(txd, 2, word);
1185
1186         rt2x00_desc_read(txd, 3, &word);
1187         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1188         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1189         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1190         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1191         rt2x00_desc_write(txd, 3, word);
1192
1193         rt2x00_desc_read(txd, 10, &word);
1194         rt2x00_set_field32(&word, TXD_W10_RTS,
1195                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1196         rt2x00_desc_write(txd, 10, word);
1197
1198         rt2x00_desc_read(txd, 0, &word);
1199         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1200         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1201         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1202                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1203         rt2x00_set_field32(&word, TXD_W0_ACK,
1204                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1205         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1206                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1207         rt2x00_set_field32(&word, TXD_W0_OFDM,
1208                            (txdesc->rate_mode == RATE_MODE_OFDM));
1209         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1210         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1211         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1212                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1213         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1214         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1215         rt2x00_desc_write(txd, 0, word);
1216 }
1217
1218 /*
1219  * TX data initialization
1220  */
1221 static void rt2500pci_write_beacon(struct queue_entry *entry)
1222 {
1223         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1224         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1225         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1226         u32 word;
1227         u32 reg;
1228
1229         /*
1230          * Disable beaconing while we are reloading the beacon data,
1231          * otherwise we might be sending out invalid data.
1232          */
1233         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1234         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1235         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1236         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1237         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1238
1239         /*
1240          * Replace rt2x00lib allocated descriptor with the
1241          * pointer to the _real_ hardware descriptor.
1242          * After that, map the beacon to DMA and update the
1243          * descriptor.
1244          */
1245         memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1246         skbdesc->desc = entry_priv->desc;
1247
1248         rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1249
1250         rt2x00_desc_read(entry_priv->desc, 1, &word);
1251         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1252         rt2x00_desc_write(entry_priv->desc, 1, word);
1253 }
1254
1255 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1256                                     const enum data_queue_qid queue)
1257 {
1258         u32 reg;
1259
1260         if (queue == QID_BEACON) {
1261                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1262                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1263                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1264                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1265                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1266                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1267                 }
1268                 return;
1269         }
1270
1271         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1272         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1273         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1274         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1275         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1276 }
1277
1278 static void rt2500pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1279                                     const enum data_queue_qid qid)
1280 {
1281         u32 reg;
1282
1283         if (qid == QID_BEACON) {
1284                 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1285         } else {
1286                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1287                 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1288                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1289         }
1290 }
1291
1292 /*
1293  * RX control handlers
1294  */
1295 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1296                                   struct rxdone_entry_desc *rxdesc)
1297 {
1298         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1299         u32 word0;
1300         u32 word2;
1301
1302         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1303         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1304
1305         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1306                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1307         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1308                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1309
1310         /*
1311          * Obtain the status about this packet.
1312          * When frame was received with an OFDM bitrate,
1313          * the signal is the PLCP value. If it was received with
1314          * a CCK bitrate the signal is the rate in 100kbit/s.
1315          */
1316         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1317         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1318             entry->queue->rt2x00dev->rssi_offset;
1319         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1320
1321         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1322                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1323         else
1324                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1325         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1326                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1327 }
1328
1329 /*
1330  * Interrupt functions.
1331  */
1332 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1333                              const enum data_queue_qid queue_idx)
1334 {
1335         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1336         struct queue_entry_priv_pci *entry_priv;
1337         struct queue_entry *entry;
1338         struct txdone_entry_desc txdesc;
1339         u32 word;
1340
1341         while (!rt2x00queue_empty(queue)) {
1342                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1343                 entry_priv = entry->priv_data;
1344                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1345
1346                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1347                     !rt2x00_get_field32(word, TXD_W0_VALID))
1348                         break;
1349
1350                 /*
1351                  * Obtain the status about this packet.
1352                  */
1353                 txdesc.flags = 0;
1354                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1355                 case 0: /* Success */
1356                 case 1: /* Success with retry */
1357                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1358                         break;
1359                 case 2: /* Failure, excessive retries */
1360                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1361                         /* Don't break, this is a failed frame! */
1362                 default: /* Failure */
1363                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1364                 }
1365                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1366
1367                 rt2x00lib_txdone(entry, &txdesc);
1368         }
1369 }
1370
1371 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1372 {
1373         struct rt2x00_dev *rt2x00dev = dev_instance;
1374         u32 reg;
1375
1376         /*
1377          * Get the interrupt sources & saved to local variable.
1378          * Write register value back to clear pending interrupts.
1379          */
1380         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1381         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1382
1383         if (!reg)
1384                 return IRQ_NONE;
1385
1386         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1387                 return IRQ_HANDLED;
1388
1389         /*
1390          * Handle interrupts, walk through all bits
1391          * and run the tasks, the bits are checked in order of
1392          * priority.
1393          */
1394
1395         /*
1396          * 1 - Beacon timer expired interrupt.
1397          */
1398         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1399                 rt2x00lib_beacondone(rt2x00dev);
1400
1401         /*
1402          * 2 - Rx ring done interrupt.
1403          */
1404         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1405                 rt2x00pci_rxdone(rt2x00dev);
1406
1407         /*
1408          * 3 - Atim ring transmit done interrupt.
1409          */
1410         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1411                 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1412
1413         /*
1414          * 4 - Priority ring transmit done interrupt.
1415          */
1416         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1417                 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
1418
1419         /*
1420          * 5 - Tx ring transmit done interrupt.
1421          */
1422         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1423                 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1424
1425         return IRQ_HANDLED;
1426 }
1427
1428 /*
1429  * Device probe functions.
1430  */
1431 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1432 {
1433         struct eeprom_93cx6 eeprom;
1434         u32 reg;
1435         u16 word;
1436         u8 *mac;
1437
1438         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1439
1440         eeprom.data = rt2x00dev;
1441         eeprom.register_read = rt2500pci_eepromregister_read;
1442         eeprom.register_write = rt2500pci_eepromregister_write;
1443         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1444             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1445         eeprom.reg_data_in = 0;
1446         eeprom.reg_data_out = 0;
1447         eeprom.reg_data_clock = 0;
1448         eeprom.reg_chip_select = 0;
1449
1450         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1451                                EEPROM_SIZE / sizeof(u16));
1452
1453         /*
1454          * Start validation of the data that has been read.
1455          */
1456         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1457         if (!is_valid_ether_addr(mac)) {
1458                 random_ether_addr(mac);
1459                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1460         }
1461
1462         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1463         if (word == 0xffff) {
1464                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1465                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1466                                    ANTENNA_SW_DIVERSITY);
1467                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1468                                    ANTENNA_SW_DIVERSITY);
1469                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1470                                    LED_MODE_DEFAULT);
1471                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1472                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1473                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1474                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1475                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1476         }
1477
1478         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1479         if (word == 0xffff) {
1480                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1481                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1482                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1483                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1484                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1485         }
1486
1487         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1488         if (word == 0xffff) {
1489                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1490                                    DEFAULT_RSSI_OFFSET);
1491                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1492                 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1493         }
1494
1495         return 0;
1496 }
1497
1498 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1499 {
1500         u32 reg;
1501         u16 value;
1502         u16 eeprom;
1503
1504         /*
1505          * Read EEPROM word for configuration.
1506          */
1507         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1508
1509         /*
1510          * Identify RF chipset.
1511          */
1512         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1513         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1514         rt2x00_set_chip_rf(rt2x00dev, value, reg);
1515
1516         if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1517             !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1518             !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1519             !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1520             !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1521             !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1522                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1523                 return -ENODEV;
1524         }
1525
1526         /*
1527          * Identify default antenna configuration.
1528          */
1529         rt2x00dev->default_ant.tx =
1530             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1531         rt2x00dev->default_ant.rx =
1532             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1533
1534         /*
1535          * Store led mode, for correct led behaviour.
1536          */
1537 #ifdef CONFIG_RT2X00_LIB_LEDS
1538         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1539
1540         rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1541         if (value == LED_MODE_TXRX_ACTIVITY ||
1542             value == LED_MODE_DEFAULT ||
1543             value == LED_MODE_ASUS)
1544                 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1545                                    LED_TYPE_ACTIVITY);
1546 #endif /* CONFIG_RT2X00_LIB_LEDS */
1547
1548         /*
1549          * Detect if this device has an hardware controlled radio.
1550          */
1551 #ifdef CONFIG_RT2X00_LIB_RFKILL
1552         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1553                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1554 #endif /* CONFIG_RT2X00_LIB_RFKILL */
1555
1556         /*
1557          * Check if the BBP tuning should be enabled.
1558          */
1559         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1560
1561         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1562                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1563
1564         /*
1565          * Read the RSSI <-> dBm offset information.
1566          */
1567         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1568         rt2x00dev->rssi_offset =
1569             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1570
1571         return 0;
1572 }
1573
1574 /*
1575  * RF value list for RF2522
1576  * Supports: 2.4 GHz
1577  */
1578 static const struct rf_channel rf_vals_bg_2522[] = {
1579         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1580         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1581         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1582         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1583         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1584         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1585         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1586         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1587         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1588         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1589         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1590         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1591         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1592         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1593 };
1594
1595 /*
1596  * RF value list for RF2523
1597  * Supports: 2.4 GHz
1598  */
1599 static const struct rf_channel rf_vals_bg_2523[] = {
1600         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1601         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1602         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1603         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1604         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1605         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1606         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1607         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1608         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1609         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1610         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1611         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1612         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1613         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1614 };
1615
1616 /*
1617  * RF value list for RF2524
1618  * Supports: 2.4 GHz
1619  */
1620 static const struct rf_channel rf_vals_bg_2524[] = {
1621         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1622         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1623         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1624         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1625         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1626         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1627         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1628         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1629         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1630         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1631         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1632         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1633         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1634         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1635 };
1636
1637 /*
1638  * RF value list for RF2525
1639  * Supports: 2.4 GHz
1640  */
1641 static const struct rf_channel rf_vals_bg_2525[] = {
1642         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1643         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1644         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1645         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1646         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1647         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1648         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1649         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1650         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1651         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1652         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1653         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1654         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1655         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1656 };
1657
1658 /*
1659  * RF value list for RF2525e
1660  * Supports: 2.4 GHz
1661  */
1662 static const struct rf_channel rf_vals_bg_2525e[] = {
1663         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1664         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1665         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1666         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1667         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1668         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1669         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1670         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1671         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1672         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1673         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1674         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1675         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1676         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1677 };
1678
1679 /*
1680  * RF value list for RF5222
1681  * Supports: 2.4 GHz & 5.2 GHz
1682  */
1683 static const struct rf_channel rf_vals_5222[] = {
1684         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1685         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1686         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1687         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1688         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1689         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1690         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1691         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1692         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1693         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1694         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1695         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1696         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1697         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1698
1699         /* 802.11 UNI / HyperLan 2 */
1700         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1701         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1702         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1703         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1704         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1705         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1706         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1707         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1708
1709         /* 802.11 HyperLan 2 */
1710         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1711         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1712         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1713         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1714         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1715         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1716         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1717         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1718         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1719         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1720
1721         /* 802.11 UNII */
1722         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1723         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1724         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1725         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1726         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1727 };
1728
1729 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1730 {
1731         struct hw_mode_spec *spec = &rt2x00dev->spec;
1732         struct channel_info *info;
1733         char *tx_power;
1734         unsigned int i;
1735
1736         /*
1737          * Initialize all hw fields.
1738          */
1739         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1740                                IEEE80211_HW_SIGNAL_DBM |
1741                                IEEE80211_HW_SUPPORTS_PS |
1742                                IEEE80211_HW_PS_NULLFUNC_STACK;
1743
1744         rt2x00dev->hw->extra_tx_headroom = 0;
1745
1746         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1747         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1748                                 rt2x00_eeprom_addr(rt2x00dev,
1749                                                    EEPROM_MAC_ADDR_0));
1750
1751         /*
1752          * Initialize hw_mode information.
1753          */
1754         spec->supported_bands = SUPPORT_BAND_2GHZ;
1755         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1756
1757         if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1758                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1759                 spec->channels = rf_vals_bg_2522;
1760         } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1761                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1762                 spec->channels = rf_vals_bg_2523;
1763         } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1764                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1765                 spec->channels = rf_vals_bg_2524;
1766         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1767                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1768                 spec->channels = rf_vals_bg_2525;
1769         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1770                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1771                 spec->channels = rf_vals_bg_2525e;
1772         } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1773                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1774                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1775                 spec->channels = rf_vals_5222;
1776         }
1777
1778         /*
1779          * Create channel information array
1780          */
1781         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1782         if (!info)
1783                 return -ENOMEM;
1784
1785         spec->channels_info = info;
1786
1787         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1788         for (i = 0; i < 14; i++)
1789                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1790
1791         if (spec->num_channels > 14) {
1792                 for (i = 14; i < spec->num_channels; i++)
1793                         info[i].tx_power1 = DEFAULT_TXPOWER;
1794         }
1795
1796         return 0;
1797 }
1798
1799 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1800 {
1801         int retval;
1802
1803         /*
1804          * Allocate eeprom data.
1805          */
1806         retval = rt2500pci_validate_eeprom(rt2x00dev);
1807         if (retval)
1808                 return retval;
1809
1810         retval = rt2500pci_init_eeprom(rt2x00dev);
1811         if (retval)
1812                 return retval;
1813
1814         /*
1815          * Initialize hw specifications.
1816          */
1817         retval = rt2500pci_probe_hw_mode(rt2x00dev);
1818         if (retval)
1819                 return retval;
1820
1821         /*
1822          * This device requires the atim queue and DMA-mapped skbs.
1823          */
1824         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1825         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1826
1827         /*
1828          * Set the rssi offset.
1829          */
1830         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1831
1832         return 0;
1833 }
1834
1835 /*
1836  * IEEE80211 stack callback functions.
1837  */
1838 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1839 {
1840         struct rt2x00_dev *rt2x00dev = hw->priv;
1841         u64 tsf;
1842         u32 reg;
1843
1844         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1845         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1846         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1847         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1848
1849         return tsf;
1850 }
1851
1852 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1853 {
1854         struct rt2x00_dev *rt2x00dev = hw->priv;
1855         u32 reg;
1856
1857         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1858         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1859 }
1860
1861 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1862         .tx                     = rt2x00mac_tx,
1863         .start                  = rt2x00mac_start,
1864         .stop                   = rt2x00mac_stop,
1865         .add_interface          = rt2x00mac_add_interface,
1866         .remove_interface       = rt2x00mac_remove_interface,
1867         .config                 = rt2x00mac_config,
1868         .configure_filter       = rt2x00mac_configure_filter,
1869         .get_stats              = rt2x00mac_get_stats,
1870         .bss_info_changed       = rt2x00mac_bss_info_changed,
1871         .conf_tx                = rt2x00mac_conf_tx,
1872         .get_tx_stats           = rt2x00mac_get_tx_stats,
1873         .get_tsf                = rt2500pci_get_tsf,
1874         .tx_last_beacon         = rt2500pci_tx_last_beacon,
1875 };
1876
1877 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1878         .irq_handler            = rt2500pci_interrupt,
1879         .probe_hw               = rt2500pci_probe_hw,
1880         .initialize             = rt2x00pci_initialize,
1881         .uninitialize           = rt2x00pci_uninitialize,
1882         .get_entry_state        = rt2500pci_get_entry_state,
1883         .clear_entry            = rt2500pci_clear_entry,
1884         .set_device_state       = rt2500pci_set_device_state,
1885         .rfkill_poll            = rt2500pci_rfkill_poll,
1886         .link_stats             = rt2500pci_link_stats,
1887         .reset_tuner            = rt2500pci_reset_tuner,
1888         .link_tuner             = rt2500pci_link_tuner,
1889         .write_tx_desc          = rt2500pci_write_tx_desc,
1890         .write_tx_data          = rt2x00pci_write_tx_data,
1891         .write_beacon           = rt2500pci_write_beacon,
1892         .kick_tx_queue          = rt2500pci_kick_tx_queue,
1893         .kill_tx_queue          = rt2500pci_kill_tx_queue,
1894         .fill_rxdone            = rt2500pci_fill_rxdone,
1895         .config_filter          = rt2500pci_config_filter,
1896         .config_intf            = rt2500pci_config_intf,
1897         .config_erp             = rt2500pci_config_erp,
1898         .config_ant             = rt2500pci_config_ant,
1899         .config                 = rt2500pci_config,
1900 };
1901
1902 static const struct data_queue_desc rt2500pci_queue_rx = {
1903         .entry_num              = RX_ENTRIES,
1904         .data_size              = DATA_FRAME_SIZE,
1905         .desc_size              = RXD_DESC_SIZE,
1906         .priv_size              = sizeof(struct queue_entry_priv_pci),
1907 };
1908
1909 static const struct data_queue_desc rt2500pci_queue_tx = {
1910         .entry_num              = TX_ENTRIES,
1911         .data_size              = DATA_FRAME_SIZE,
1912         .desc_size              = TXD_DESC_SIZE,
1913         .priv_size              = sizeof(struct queue_entry_priv_pci),
1914 };
1915
1916 static const struct data_queue_desc rt2500pci_queue_bcn = {
1917         .entry_num              = BEACON_ENTRIES,
1918         .data_size              = MGMT_FRAME_SIZE,
1919         .desc_size              = TXD_DESC_SIZE,
1920         .priv_size              = sizeof(struct queue_entry_priv_pci),
1921 };
1922
1923 static const struct data_queue_desc rt2500pci_queue_atim = {
1924         .entry_num              = ATIM_ENTRIES,
1925         .data_size              = DATA_FRAME_SIZE,
1926         .desc_size              = TXD_DESC_SIZE,
1927         .priv_size              = sizeof(struct queue_entry_priv_pci),
1928 };
1929
1930 static const struct rt2x00_ops rt2500pci_ops = {
1931         .name           = KBUILD_MODNAME,
1932         .max_sta_intf   = 1,
1933         .max_ap_intf    = 1,
1934         .eeprom_size    = EEPROM_SIZE,
1935         .rf_size        = RF_SIZE,
1936         .tx_queues      = NUM_TX_QUEUES,
1937         .rx             = &rt2500pci_queue_rx,
1938         .tx             = &rt2500pci_queue_tx,
1939         .bcn            = &rt2500pci_queue_bcn,
1940         .atim           = &rt2500pci_queue_atim,
1941         .lib            = &rt2500pci_rt2x00_ops,
1942         .hw             = &rt2500pci_mac80211_ops,
1943 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1944         .debugfs        = &rt2500pci_rt2x00debug,
1945 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1946 };
1947
1948 /*
1949  * RT2500pci module information.
1950  */
1951 static struct pci_device_id rt2500pci_device_table[] = {
1952         { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1953         { 0, }
1954 };
1955
1956 MODULE_AUTHOR(DRV_PROJECT);
1957 MODULE_VERSION(DRV_VERSION);
1958 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1959 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1960 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1961 MODULE_LICENSE("GPL");
1962
1963 static struct pci_driver rt2500pci_driver = {
1964         .name           = KBUILD_MODNAME,
1965         .id_table       = rt2500pci_device_table,
1966         .probe          = rt2x00pci_probe,
1967         .remove         = __devexit_p(rt2x00pci_remove),
1968         .suspend        = rt2x00pci_suspend,
1969         .resume         = rt2x00pci_resume,
1970 };
1971
1972 static int __init rt2500pci_init(void)
1973 {
1974         return pci_register_driver(&rt2500pci_driver);
1975 }
1976
1977 static void __exit rt2500pci_exit(void)
1978 {
1979         pci_unregister_driver(&rt2500pci_driver);
1980 }
1981
1982 module_init(rt2500pci_init);
1983 module_exit(rt2500pci_exit);