Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland...
[linux-2.6] / drivers / media / video / cx18 / cx18-firmware.c
1 /*
2  *  cx18 firmware functions
3  *
4  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
5  *  Copyright (C) 2008  Andy Walls <awalls@radix.net>
6  *
7  *  This program is free software; you can redistribute it and/or modify
8  *  it under the terms of the GNU General Public License as published by
9  *  the Free Software Foundation; either version 2 of the License, or
10  *  (at your option) any later version.
11  *
12  *  This program is distributed in the hope that it will be useful,
13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  *  GNU General Public License for more details.
16  *
17  *  You should have received a copy of the GNU General Public License
18  *  along with this program; if not, write to the Free Software
19  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
20  *  02111-1307  USA
21  */
22
23 #include "cx18-driver.h"
24 #include "cx18-io.h"
25 #include "cx18-scb.h"
26 #include "cx18-irq.h"
27 #include "cx18-firmware.h"
28 #include "cx18-cards.h"
29 #include "cx18-av-core.h"
30 #include <linux/firmware.h>
31
32 #define CX18_PROC_SOFT_RESET            0xc70010
33 #define CX18_DDR_SOFT_RESET             0xc70014
34 #define CX18_CLOCK_SELECT1              0xc71000
35 #define CX18_CLOCK_SELECT2              0xc71004
36 #define CX18_HALF_CLOCK_SELECT1         0xc71008
37 #define CX18_HALF_CLOCK_SELECT2         0xc7100C
38 #define CX18_CLOCK_POLARITY1            0xc71010
39 #define CX18_CLOCK_POLARITY2            0xc71014
40 #define CX18_ADD_DELAY_ENABLE1          0xc71018
41 #define CX18_ADD_DELAY_ENABLE2          0xc7101C
42 #define CX18_CLOCK_ENABLE1              0xc71020
43 #define CX18_CLOCK_ENABLE2              0xc71024
44
45 #define CX18_REG_BUS_TIMEOUT_EN         0xc72024
46
47 #define CX18_FAST_CLOCK_PLL_INT         0xc78000
48 #define CX18_FAST_CLOCK_PLL_FRAC        0xc78004
49 #define CX18_FAST_CLOCK_PLL_POST        0xc78008
50 #define CX18_FAST_CLOCK_PLL_PRESCALE    0xc7800C
51 #define CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH 0xc78010
52
53 #define CX18_SLOW_CLOCK_PLL_INT         0xc78014
54 #define CX18_SLOW_CLOCK_PLL_FRAC        0xc78018
55 #define CX18_SLOW_CLOCK_PLL_POST        0xc7801C
56 #define CX18_MPEG_CLOCK_PLL_INT         0xc78040
57 #define CX18_MPEG_CLOCK_PLL_FRAC        0xc78044
58 #define CX18_MPEG_CLOCK_PLL_POST        0xc78048
59 #define CX18_PLL_POWER_DOWN             0xc78088
60 #define CX18_SW1_INT_STATUS             0xc73104
61 #define CX18_SW1_INT_ENABLE_PCI         0xc7311C
62 #define CX18_SW2_INT_SET                0xc73140
63 #define CX18_SW2_INT_STATUS             0xc73144
64 #define CX18_ADEC_CONTROL               0xc78120
65
66 #define CX18_DDR_REQUEST_ENABLE         0xc80000
67 #define CX18_DDR_CHIP_CONFIG            0xc80004
68 #define CX18_DDR_REFRESH                0xc80008
69 #define CX18_DDR_TIMING1                0xc8000C
70 #define CX18_DDR_TIMING2                0xc80010
71 #define CX18_DDR_POWER_REG              0xc8001C
72
73 #define CX18_DDR_TUNE_LANE              0xc80048
74 #define CX18_DDR_INITIAL_EMRS           0xc80054
75 #define CX18_DDR_MB_PER_ROW_7           0xc8009C
76 #define CX18_DDR_BASE_63_ADDR           0xc804FC
77
78 #define CX18_WMB_CLIENT02               0xc90108
79 #define CX18_WMB_CLIENT05               0xc90114
80 #define CX18_WMB_CLIENT06               0xc90118
81 #define CX18_WMB_CLIENT07               0xc9011C
82 #define CX18_WMB_CLIENT08               0xc90120
83 #define CX18_WMB_CLIENT09               0xc90124
84 #define CX18_WMB_CLIENT10               0xc90128
85 #define CX18_WMB_CLIENT11               0xc9012C
86 #define CX18_WMB_CLIENT12               0xc90130
87 #define CX18_WMB_CLIENT13               0xc90134
88 #define CX18_WMB_CLIENT14               0xc90138
89
90 #define CX18_DSP0_INTERRUPT_MASK        0xd0004C
91
92 #define APU_ROM_SYNC1 0x6D676553 /* "mgeS" */
93 #define APU_ROM_SYNC2 0x72646548 /* "rdeH" */
94
95 struct cx18_apu_rom_seghdr {
96         u32 sync1;
97         u32 sync2;
98         u32 addr;
99         u32 size;
100 };
101
102 static int load_cpu_fw_direct(const char *fn, u8 __iomem *mem, struct cx18 *cx)
103 {
104         const struct firmware *fw = NULL;
105         int i, j;
106         unsigned size;
107         u32 __iomem *dst = (u32 __iomem *)mem;
108         const u32 *src;
109
110         if (request_firmware(&fw, fn, &cx->dev->dev)) {
111                 CX18_ERR("Unable to open firmware %s\n", fn);
112                 CX18_ERR("Did you put the firmware in the hotplug firmware directory?\n");
113                 return -ENOMEM;
114         }
115
116         src = (const u32 *)fw->data;
117
118         for (i = 0; i < fw->size; i += 4096) {
119                 cx18_setup_page(cx, i);
120                 for (j = i; j < fw->size && j < i + 4096; j += 4) {
121                         /* no need for endianness conversion on the ppc */
122                         cx18_raw_writel(cx, *src, dst);
123                         if (cx18_raw_readl(cx, dst) != *src) {
124                                 CX18_ERR("Mismatch at offset %x\n", i);
125                                 release_firmware(fw);
126                                 cx18_setup_page(cx, 0);
127                                 return -EIO;
128                         }
129                         dst++;
130                         src++;
131                 }
132         }
133         if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
134                 CX18_INFO("loaded %s firmware (%zd bytes)\n", fn, fw->size);
135         size = fw->size;
136         release_firmware(fw);
137         cx18_setup_page(cx, SCB_OFFSET);
138         return size;
139 }
140
141 static int load_apu_fw_direct(const char *fn, u8 __iomem *dst, struct cx18 *cx,
142                                 u32 *entry_addr)
143 {
144         const struct firmware *fw = NULL;
145         int i, j;
146         unsigned size;
147         const u32 *src;
148         struct cx18_apu_rom_seghdr seghdr;
149         const u8 *vers;
150         u32 offset = 0;
151         u32 apu_version = 0;
152         int sz;
153
154         if (request_firmware(&fw, fn, &cx->dev->dev)) {
155                 CX18_ERR("unable to open firmware %s\n", fn);
156                 CX18_ERR("did you put the firmware in the hotplug firmware directory?\n");
157                 cx18_setup_page(cx, 0);
158                 return -ENOMEM;
159         }
160
161         *entry_addr = 0;
162         src = (const u32 *)fw->data;
163         vers = fw->data + sizeof(seghdr);
164         sz = fw->size;
165
166         apu_version = (vers[0] << 24) | (vers[4] << 16) | vers[32];
167         while (offset + sizeof(seghdr) < fw->size) {
168                 /* TODO: byteswapping */
169                 memcpy(&seghdr, src + offset / 4, sizeof(seghdr));
170                 offset += sizeof(seghdr);
171                 if (seghdr.sync1 != APU_ROM_SYNC1 ||
172                     seghdr.sync2 != APU_ROM_SYNC2) {
173                         offset += seghdr.size;
174                         continue;
175                 }
176                 CX18_DEBUG_INFO("load segment %x-%x\n", seghdr.addr,
177                                 seghdr.addr + seghdr.size - 1);
178                 if (*entry_addr == 0)
179                         *entry_addr = seghdr.addr;
180                 if (offset + seghdr.size > sz)
181                         break;
182                 for (i = 0; i < seghdr.size; i += 4096) {
183                         cx18_setup_page(cx, seghdr.addr + i);
184                         for (j = i; j < seghdr.size && j < i + 4096; j += 4) {
185                                 /* no need for endianness conversion on the ppc */
186                                 cx18_raw_writel(cx, src[(offset + j) / 4],
187                                                 dst + seghdr.addr + j);
188                                 if (cx18_raw_readl(cx, dst + seghdr.addr + j)
189                                     != src[(offset + j) / 4]) {
190                                         CX18_ERR("Mismatch at offset %x\n",
191                                                  offset + j);
192                                         release_firmware(fw);
193                                         cx18_setup_page(cx, 0);
194                                         return -EIO;
195                                 }
196                         }
197                 }
198                 offset += seghdr.size;
199         }
200         if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
201                 CX18_INFO("loaded %s firmware V%08x (%zd bytes)\n",
202                                 fn, apu_version, fw->size);
203         size = fw->size;
204         release_firmware(fw);
205         cx18_setup_page(cx, 0);
206         return size;
207 }
208
209 void cx18_halt_firmware(struct cx18 *cx)
210 {
211         CX18_DEBUG_INFO("Preparing for firmware halt.\n");
212         cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET,
213                                   0x0000000F, 0x000F000F);
214         cx18_write_reg_expect(cx, 0x00020002, CX18_ADEC_CONTROL,
215                                   0x00000002, 0x00020002);
216 }
217
218 void cx18_init_power(struct cx18 *cx, int lowpwr)
219 {
220         /* power-down Spare and AOM PLLs */
221         /* power-up fast, slow and mpeg PLLs */
222         cx18_write_reg(cx, 0x00000008, CX18_PLL_POWER_DOWN);
223
224         /* ADEC out of sleep */
225         cx18_write_reg_expect(cx, 0x00020000, CX18_ADEC_CONTROL,
226                                   0x00000000, 0x00020002);
227
228         /*
229          * The PLL parameters are based on the external crystal frequency that
230          * would ideally be:
231          *
232          * NTSC Color subcarrier freq * 8 =
233          *      4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
234          *
235          * The accidents of history and rationale that explain from where this
236          * combination of magic numbers originate can be found in:
237          *
238          * [1] Abrahams, I. C., "Choice of Chrominance Subcarrier Frequency in
239          * the NTSC Standards", Proceedings of the I-R-E, January 1954, pp 79-80
240          *
241          * [2] Abrahams, I. C., "The 'Frequency Interleaving' Principle in the
242          * NTSC Standards", Proceedings of the I-R-E, January 1954, pp 81-83
243          *
244          * As Mike Bradley has rightly pointed out, it's not the exact crystal
245          * frequency that matters, only that all parts of the driver and
246          * firmware are using the same value (close to the ideal value).
247          *
248          * Since I have a strong suspicion that, if the firmware ever assumes a
249          * crystal value at all, it will assume 28.636360 MHz, the crystal
250          * freq used in calculations in this driver will be:
251          *
252          *      xtal_freq = 28.636360 MHz
253          *
254          * an error of less than 0.13 ppm which is way, way better than any off
255          * the shelf crystal will have for accuracy anyway.
256          *
257          * Below I aim to run the PLLs' VCOs near 400 MHz to minimze errors.
258          *
259          * Many thanks to Jeff Campbell and Mike Bradley for their extensive
260          * investigation, experimentation, testing, and suggested solutions of
261          * of audio/video sync problems with SVideo and CVBS captures.
262          */
263
264         /* the fast clock is at 200/245 MHz */
265         /* 1 * xtal_freq * 0x0d.f7df9b8 / 2 = 200 MHz: 400 MHz pre post-divide*/
266         /* 1 * xtal_freq * 0x11.1c71eb8 / 2 = 245 MHz: 490 MHz pre post-divide*/
267         cx18_write_reg(cx, lowpwr ? 0xD : 0x11, CX18_FAST_CLOCK_PLL_INT);
268         cx18_write_reg(cx, lowpwr ? 0x1EFBF37 : 0x038E3D7,
269                                                 CX18_FAST_CLOCK_PLL_FRAC);
270
271         cx18_write_reg(cx, 2, CX18_FAST_CLOCK_PLL_POST);
272         cx18_write_reg(cx, 1, CX18_FAST_CLOCK_PLL_PRESCALE);
273         cx18_write_reg(cx, 4, CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH);
274
275         /* set slow clock to 125/120 MHz */
276         /* xtal_freq * 0x0d.1861a20 / 3 = 125 MHz: 375 MHz before post-divide */
277         /* xtal_freq * 0x0c.92493f8 / 3 = 120 MHz: 360 MHz before post-divide */
278         cx18_write_reg(cx, lowpwr ? 0xD : 0xC, CX18_SLOW_CLOCK_PLL_INT);
279         cx18_write_reg(cx, lowpwr ? 0x30C344 : 0x124927F,
280                                                 CX18_SLOW_CLOCK_PLL_FRAC);
281         cx18_write_reg(cx, 3, CX18_SLOW_CLOCK_PLL_POST);
282
283         /* mpeg clock pll 54MHz */
284         /* xtal_freq * 0xf.15f17f0 / 8 = 54 MHz: 432 MHz before post-divide */
285         cx18_write_reg(cx, 0xF, CX18_MPEG_CLOCK_PLL_INT);
286         cx18_write_reg(cx, 0x2BE2FE, CX18_MPEG_CLOCK_PLL_FRAC);
287         cx18_write_reg(cx, 8, CX18_MPEG_CLOCK_PLL_POST);
288
289         /*
290          * VDCLK  Integer = 0x0f, Post Divider = 0x04
291          * AIMCLK Integer = 0x0e, Post Divider = 0x16
292          */
293         cx18_av_write4(cx, CXADEC_PLL_CTRL1, 0x160e040f);
294
295         /* VDCLK Fraction = 0x2be2fe */
296         /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz before post divide */
297         cx18_av_write4(cx, CXADEC_VID_PLL_FRAC, 0x002be2fe);
298
299         /* AIMCLK Fraction = 0x05227ad */
300         /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz before post-divide */
301         cx18_av_write4(cx, CXADEC_AUX_PLL_FRAC, 0x005227ad);
302
303         /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */
304         cx18_av_write(cx, CXADEC_I2S_MCLK, 0x56);
305
306         /* Defaults */
307         /* APU = SC or SC/2 = 125/62.5 */
308         /* EPU = SC = 125 */
309         /* DDR = FC = 180 */
310         /* ENC = SC = 125 */
311         /* AI1 = SC = 125 */
312         /* VIM2 = disabled */
313         /* PCI = FC/2 = 90 */
314         /* AI2 = disabled */
315         /* DEMUX = disabled */
316         /* AO = SC/2 = 62.5 */
317         /* SER = 54MHz */
318         /* VFC = disabled */
319         /* USB = disabled */
320
321         if (lowpwr) {
322                 cx18_write_reg_expect(cx, 0xFFFF0020, CX18_CLOCK_SELECT1,
323                                           0x00000020, 0xFFFFFFFF);
324                 cx18_write_reg_expect(cx, 0xFFFF0004, CX18_CLOCK_SELECT2,
325                                           0x00000004, 0xFFFFFFFF);
326         } else {
327                 /* This doesn't explicitly set every clock select */
328                 cx18_write_reg_expect(cx, 0x00060004, CX18_CLOCK_SELECT1,
329                                           0x00000004, 0x00060006);
330                 cx18_write_reg_expect(cx, 0x00060006, CX18_CLOCK_SELECT2,
331                                           0x00000006, 0x00060006);
332         }
333
334         cx18_write_reg_expect(cx, 0xFFFF0002, CX18_HALF_CLOCK_SELECT1,
335                                   0x00000002, 0xFFFFFFFF);
336         cx18_write_reg_expect(cx, 0xFFFF0104, CX18_HALF_CLOCK_SELECT2,
337                                   0x00000104, 0xFFFFFFFF);
338         cx18_write_reg_expect(cx, 0xFFFF9026, CX18_CLOCK_ENABLE1,
339                                   0x00009026, 0xFFFFFFFF);
340         cx18_write_reg_expect(cx, 0xFFFF3105, CX18_CLOCK_ENABLE2,
341                                   0x00003105, 0xFFFFFFFF);
342 }
343
344 void cx18_init_memory(struct cx18 *cx)
345 {
346         cx18_msleep_timeout(10, 0);
347         cx18_write_reg_expect(cx, 0x00010000, CX18_DDR_SOFT_RESET,
348                                   0x00000000, 0x00010001);
349         cx18_msleep_timeout(10, 0);
350
351         cx18_write_reg(cx, cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG);
352
353         cx18_msleep_timeout(10, 0);
354
355         cx18_write_reg(cx, cx->card->ddr.refresh, CX18_DDR_REFRESH);
356         cx18_write_reg(cx, cx->card->ddr.timing1, CX18_DDR_TIMING1);
357         cx18_write_reg(cx, cx->card->ddr.timing2, CX18_DDR_TIMING2);
358
359         cx18_msleep_timeout(10, 0);
360
361         /* Initialize DQS pad time */
362         cx18_write_reg(cx, cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE);
363         cx18_write_reg(cx, cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS);
364
365         cx18_msleep_timeout(10, 0);
366
367         cx18_write_reg_expect(cx, 0x00020000, CX18_DDR_SOFT_RESET,
368                                   0x00000000, 0x00020002);
369         cx18_msleep_timeout(10, 0);
370
371         /* use power-down mode when idle */
372         cx18_write_reg(cx, 0x00000010, CX18_DDR_POWER_REG);
373
374         cx18_write_reg_expect(cx, 0x00010001, CX18_REG_BUS_TIMEOUT_EN,
375                                   0x00000001, 0x00010001);
376
377         cx18_write_reg(cx, 0x48, CX18_DDR_MB_PER_ROW_7);
378         cx18_write_reg(cx, 0xE0000, CX18_DDR_BASE_63_ADDR);
379
380         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT02);  /* AO */
381         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT09);  /* AI2 */
382         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT05);  /* VIM1 */
383         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT06);  /* AI1 */
384         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT07);  /* 3D comb */
385         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT10);  /* ME */
386         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT12);  /* ENC */
387         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT13);  /* PK */
388         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT11);  /* RC */
389         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT14);  /* AVO */
390 }
391
392 int cx18_firmware_init(struct cx18 *cx)
393 {
394         u32 fw_entry_addr;
395         int sz, retries;
396         u32 api_args[MAX_MB_ARGUMENTS];
397
398         /* Allow chip to control CLKRUN */
399         cx18_write_reg(cx, 0x5, CX18_DSP0_INTERRUPT_MASK);
400
401         /* Stop the firmware */
402         cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET,
403                                   0x0000000F, 0x000F000F);
404
405         cx18_msleep_timeout(1, 0);
406
407         /* If the CPU is still running */
408         if ((cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 8) == 0) {
409                 CX18_ERR("%s: couldn't stop CPU to load firmware\n", __func__);
410                 return -EIO;
411         }
412
413         cx18_sw1_irq_enable(cx, IRQ_CPU_TO_EPU | IRQ_APU_TO_EPU);
414         cx18_sw2_irq_enable(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
415
416         sz = load_cpu_fw_direct("v4l-cx23418-cpu.fw", cx->enc_mem, cx);
417         if (sz <= 0)
418                 return sz;
419
420         /* The SCB & IPC area *must* be correct before starting the firmwares */
421         cx18_init_scb(cx);
422
423         fw_entry_addr = 0;
424         sz = load_apu_fw_direct("v4l-cx23418-apu.fw", cx->enc_mem, cx,
425                                 &fw_entry_addr);
426         if (sz <= 0)
427                 return sz;
428
429         /* Start the CPU. The CPU will take care of the APU for us. */
430         cx18_write_reg_expect(cx, 0x00080000, CX18_PROC_SOFT_RESET,
431                                   0x00000000, 0x00080008);
432
433         /* Wait up to 500 ms for the APU to come out of reset */
434         for (retries = 0;
435              retries < 50 && (cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 1) == 1;
436              retries++)
437                 cx18_msleep_timeout(10, 0);
438
439         cx18_msleep_timeout(200, 0);
440
441         if (retries == 50 &&
442             (cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 1) == 1) {
443                 CX18_ERR("Could not start the CPU\n");
444                 return -EIO;
445         }
446
447         /*
448          * The CPU had once before set up to receive an interrupt for it's
449          * outgoing IRQ_CPU_TO_EPU_ACK to us.  If it ever does this, we get an
450          * interrupt when it sends us an ack, but by the time we process it,
451          * that flag in the SW2 status register has been cleared by the CPU
452          * firmware.  We'll prevent that not so useful condition from happening
453          * by clearing the CPU's interrupt enables for Ack IRQ's we want to
454          * process.
455          */
456         cx18_sw2_irq_disable_cpu(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
457
458         /* Try a benign command to see if the CPU is alive and well */
459         sz = cx18_vapi_result(cx, api_args, CX18_CPU_DEBUG_PEEK32, 1, 0);
460         if (sz < 0)
461                 return sz;
462
463         /* initialize GPIO */
464         cx18_write_reg_expect(cx, 0x14001400, 0xc78110, 0x00001400, 0x14001400);
465         return 0;
466 }