Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/shaggy...
[linux-2.6] / drivers / ide / pci / slc90e66.c
1 /*
2  *  linux/drivers/ide/pci/slc90e66.c    Version 0.13    December 30, 2006
3  *
4  *  Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
5  *  Copyright (C) 2006 MontaVista Software, Inc. <source@mvista.com>
6  *
7  * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
8  * but this keeps the ISA-Bridge and slots alive.
9  *
10  */
11
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/hdreg.h>
18 #include <linux/ide.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
21
22 #include <asm/io.h>
23
24 static u8 slc90e66_ratemask (ide_drive_t *drive)
25 {
26         u8 mode = 2;
27
28         if (!eighty_ninty_three(drive))
29                 mode = min_t(u8, mode, 1);
30         return mode;
31 }
32
33 static u8 slc90e66_dma_2_pio (u8 xfer_rate) {
34         switch(xfer_rate) {
35                 case XFER_UDMA_4:
36                 case XFER_UDMA_3:
37                 case XFER_UDMA_2:
38                 case XFER_UDMA_1:
39                 case XFER_UDMA_0:
40                 case XFER_MW_DMA_2:
41                 case XFER_PIO_4:
42                         return 4;
43                 case XFER_MW_DMA_1:
44                 case XFER_PIO_3:
45                         return 3;
46                 case XFER_SW_DMA_2:
47                 case XFER_PIO_2:
48                         return 2;
49                 case XFER_MW_DMA_0:
50                 case XFER_SW_DMA_1:
51                 case XFER_SW_DMA_0:
52                 case XFER_PIO_1:
53                 case XFER_PIO_0:
54                 case XFER_PIO_SLOW:
55                 default:
56                         return 0;
57         }
58 }
59
60 /*
61  *  Based on settings done by AMI BIOS
62  *  (might be useful if drive is not registered in CMOS for any reason).
63  */
64 static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio)
65 {
66         ide_hwif_t *hwif        = HWIF(drive);
67         struct pci_dev *dev     = hwif->pci_dev;
68         int is_slave            = drive->dn & 1;
69         int master_port         = hwif->channel ? 0x42 : 0x40;
70         int slave_port          = 0x44;
71         unsigned long flags;
72         u16 master_data;
73         u8 slave_data;
74         int control = 0;
75                                      /* ISP  RTC */
76         static const u8 timings[][2]= {
77                                         { 0, 0 },
78                                         { 0, 0 },
79                                         { 1, 0 },
80                                         { 2, 1 },
81                                         { 2, 3 }, };
82
83         pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
84         spin_lock_irqsave(&ide_lock, flags);
85         pci_read_config_word(dev, master_port, &master_data);
86
87         if (pio > 1)
88                 control |= 1;   /* Programmable timing on */
89         if (drive->media == ide_disk)
90                 control |= 4;   /* Prefetch, post write */
91         if (pio > 2)
92                 control |= 2;   /* IORDY */
93         if (is_slave) {
94                 master_data |=  0x4000;
95                 master_data &= ~0x0070;
96                 if (pio > 1) {
97                         /* enable PPE, IE and TIME */
98                         master_data = master_data | (control << 4);
99                 }
100                 pci_read_config_byte(dev, slave_port, &slave_data);
101                 slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
102                 slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
103         } else {
104                 master_data &= ~0x3307;
105                 if (pio > 1) {
106                         /* enable PPE, IE and TIME */
107                         master_data = master_data | control;
108                 }
109                 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
110         }
111         pci_write_config_word(dev, master_port, master_data);
112         if (is_slave)
113                 pci_write_config_byte(dev, slave_port, slave_data);
114         spin_unlock_irqrestore(&ide_lock, flags);
115 }
116
117 static int slc90e66_tune_chipset (ide_drive_t *drive, u8 xferspeed)
118 {
119         ide_hwif_t *hwif        = HWIF(drive);
120         struct pci_dev *dev     = hwif->pci_dev;
121         u8 maslave              = hwif->channel ? 0x42 : 0x40;
122         u8 speed        = ide_rate_filter(slc90e66_ratemask(drive), xferspeed);
123         int sitre = 0, a_speed  = 7 << (drive->dn * 4);
124         int u_speed = 0, u_flag = 1 << drive->dn;
125         u16                     reg4042, reg44, reg48, reg4a;
126
127         pci_read_config_word(dev, maslave, &reg4042);
128         sitre = (reg4042 & 0x4000) ? 1 : 0;
129         pci_read_config_word(dev, 0x44, &reg44);
130         pci_read_config_word(dev, 0x48, &reg48);
131         pci_read_config_word(dev, 0x4a, &reg4a);
132
133         switch(speed) {
134                 case XFER_UDMA_4:       u_speed = 4 << (drive->dn * 4); break;
135                 case XFER_UDMA_3:       u_speed = 3 << (drive->dn * 4); break;
136                 case XFER_UDMA_2:       u_speed = 2 << (drive->dn * 4); break;
137                 case XFER_UDMA_1:       u_speed = 1 << (drive->dn * 4); break;
138                 case XFER_UDMA_0:       u_speed = 0 << (drive->dn * 4); break;
139                 case XFER_MW_DMA_2:
140                 case XFER_MW_DMA_1:
141                 case XFER_SW_DMA_2:     break;
142                 case XFER_PIO_4:
143                 case XFER_PIO_3:
144                 case XFER_PIO_2:
145                 case XFER_PIO_0:        break;
146                 default:                return -1;
147         }
148
149         if (speed >= XFER_UDMA_0) {
150                 if (!(reg48 & u_flag))
151                         pci_write_config_word(dev, 0x48, reg48|u_flag);
152                 /* FIXME: (reg4a & a_speed) ? */
153                 if ((reg4a & u_speed) != u_speed) {
154                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
155                         pci_read_config_word(dev, 0x4a, &reg4a);
156                         pci_write_config_word(dev, 0x4a, reg4a|u_speed);
157                 }
158         } else {
159                 if (reg48 & u_flag)
160                         pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
161                 if (reg4a & a_speed)
162                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
163         }
164
165         slc90e66_tune_drive(drive, slc90e66_dma_2_pio(speed));
166         return (ide_config_drive_speed(drive, speed));
167 }
168
169 static int slc90e66_config_drive_for_dma (ide_drive_t *drive)
170 {
171         u8 speed = ide_dma_speed(drive, slc90e66_ratemask(drive));
172
173         if (!speed)
174                 return 0;
175
176         (void) slc90e66_tune_chipset(drive, speed);
177         return ide_dma_enable(drive);
178 }
179
180 static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive)
181 {
182         drive->init_speed = 0;
183
184         if (ide_use_dma(drive) && slc90e66_config_drive_for_dma(drive))
185                 return 0;
186
187         if (ide_use_fast_pio(drive))
188                 (void)slc90e66_tune_chipset(drive, XFER_PIO_0 +
189                                 ide_get_best_pio_mode(drive, 255, 4, NULL));
190
191         return -1;
192 }
193
194 static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
195 {
196         u8 reg47 = 0;
197         u8 mask = hwif->channel ? 0x01 : 0x02;  /* bit0:Primary */
198
199         hwif->autodma = 0;
200
201         if (!hwif->irq)
202                 hwif->irq = hwif->channel ? 15 : 14;
203
204         hwif->speedproc = &slc90e66_tune_chipset;
205         hwif->tuneproc  = &slc90e66_tune_drive;
206
207         pci_read_config_byte(hwif->pci_dev, 0x47, &reg47);
208
209         if (!hwif->dma_base) {
210                 hwif->drives[0].autotune = 1;
211                 hwif->drives[1].autotune = 1;
212                 return;
213         }
214
215         hwif->atapi_dma = 1;
216         hwif->ultra_mask = 0x1f;
217         hwif->mwdma_mask = 0x06;
218         hwif->swdma_mask = 0x04;
219
220         if (!hwif->udma_four) {
221                 /* bit[0(1)]: 0:80, 1:40 */
222                 hwif->udma_four = (reg47 & mask) ? 0 : 1;
223         }
224
225         hwif->ide_dma_check = &slc90e66_config_drive_xfer_rate;
226
227         if (!noautodma)
228                 hwif->autodma = 1;
229         hwif->drives[0].autodma = hwif->autodma;
230         hwif->drives[1].autodma = hwif->autodma;
231 }
232
233 static ide_pci_device_t slc90e66_chipset __devinitdata = {
234         .name           = "SLC90E66",
235         .init_hwif      = init_hwif_slc90e66,
236         .channels       = 2,
237         .autodma        = AUTODMA,
238         .enablebits     = {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
239         .bootable       = ON_BOARD,
240 };
241
242 static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
243 {
244         return ide_setup_pci_device(dev, &slc90e66_chipset);
245 }
246
247 static struct pci_device_id slc90e66_pci_tbl[] = {
248         { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0},
249         { 0, },
250 };
251 MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
252
253 static struct pci_driver driver = {
254         .name           = "SLC90e66_IDE",
255         .id_table       = slc90e66_pci_tbl,
256         .probe          = slc90e66_init_one,
257 };
258
259 static int __init slc90e66_ide_init(void)
260 {
261         return ide_pci_register_driver(&driver);
262 }
263
264 module_init(slc90e66_ide_init);
265
266 MODULE_AUTHOR("Andre Hedrick");
267 MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
268 MODULE_LICENSE("GPL");