git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/rt2x00/rt2500pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500pci
  23         Abstract: rt2500pci device specific routines.
  24         Supported chipsets: RT2560.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2500pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00pci_register_read and rt2x00pci_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  53 {
  54         u32 reg;
  55         unsigned int i;
  56
  57         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  58                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  59                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  60                         break;
  61                 udelay(REGISTER_BUSY_DELAY);
  62         }
  63
  64         return reg;
  65 }
  66
  67 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  68                                 const unsigned int word, const u8 value)
  69 {
  70         u32 reg;
  71
  72         /*
  73          * Wait until the BBP becomes ready.
  74          */
  75         reg = rt2500pci_bbp_check(rt2x00dev);
  76         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  77                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  78                 return;
  79         }
  80
  81         /*
  82          * Write the data into the BBP.
  83          */
  84         reg = 0;
  85         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  86         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  87         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  88         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  89
  90         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  91 }
  92
  93 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  94                                const unsigned int word, u8 *value)
  95 {
  96         u32 reg;
  97
  98         /*
  99          * Wait until the BBP becomes ready.
 100          */
 101         reg = rt2500pci_bbp_check(rt2x00dev);
 102         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 103                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 104                 return;
 105         }
 106
 107         /*
 108          * Write the request into the BBP.
 109          */
 110         reg = 0;
 111         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 112         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 113         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 114
 115         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 116
 117         /*
 118          * Wait until the BBP becomes ready.
 119          */
 120         reg = rt2500pci_bbp_check(rt2x00dev);
 121         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 122                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 123                 *value = 0xff;
 124                 return;
 125         }
 126
 127         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 128 }
 129
 130 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
 131                                const unsigned int word, const u32 value)
 132 {
 133         u32 reg;
 134         unsigned int i;
 135
 136         if (!word)
 137                 return;
 138
 139         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 140                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 141                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 142                         goto rf_write;
 143                 udelay(REGISTER_BUSY_DELAY);
 144         }
 145
 146         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 147         return;
 148
 149 rf_write:
 150         reg = 0;
 151         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 152         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 153         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 154         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 155
 156         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 157         rt2x00_rf_write(rt2x00dev, word, value);
 158 }
 159
 160 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 161 {
 162         struct rt2x00_dev *rt2x00dev = eeprom->data;
 163         u32 reg;
 164
 165         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 166
 167         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 168         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 169         eeprom->reg_data_clock =
 170             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 171         eeprom->reg_chip_select =
 172             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 173 }
 174
 175 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 176 {
 177         struct rt2x00_dev *rt2x00dev = eeprom->data;
 178         u32 reg = 0;
 179
 180         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 181         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 182         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 183                            !!eeprom->reg_data_clock);
 184         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 185                            !!eeprom->reg_chip_select);
 186
 187         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 188 }
 189
 190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 191 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 192
 193 static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
 194                                const unsigned int word, u32 *data)
 195 {
 196         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 197 }
 198
 199 static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
 200                                 const unsigned int word, u32 data)
 201 {
 202         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 203 }
 204
 205 static const struct rt2x00debug rt2500pci_rt2x00debug = {
 206         .owner  = THIS_MODULE,
 207         .csr    = {
 208                 .read           = rt2500pci_read_csr,
 209                 .write          = rt2500pci_write_csr,
 210                 .word_size      = sizeof(u32),
 211                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 212         },
 213         .eeprom = {
 214                 .read           = rt2x00_eeprom_read,
 215                 .write          = rt2x00_eeprom_write,
 216                 .word_size      = sizeof(u16),
 217                 .word_count     = EEPROM_SIZE / sizeof(u16),
 218         },
 219         .bbp    = {
 220                 .read           = rt2500pci_bbp_read,
 221                 .write          = rt2500pci_bbp_write,
 222                 .word_size      = sizeof(u8),
 223                 .word_count     = BBP_SIZE / sizeof(u8),
 224         },
 225         .rf     = {
 226                 .read           = rt2x00_rf_read,
 227                 .write          = rt2500pci_rf_write,
 228                 .word_size      = sizeof(u32),
 229                 .word_count     = RF_SIZE / sizeof(u32),
 230         },
 231 };
 232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 233
 234 #ifdef CONFIG_RT2500PCI_RFKILL
 235 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 236 {
 237         u32 reg;
 238
 239         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 240         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 241 }
 242 #else
 243 #define rt2500pci_rfkill_poll   NULL
 244 #endif /* CONFIG_RT2500PCI_RFKILL */
 245
 246 #ifdef CONFIG_RT2500PCI_LEDS
 247 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
 248                                      enum led_brightness brightness)
 249 {
 250         struct rt2x00_led *led =
 251             container_of(led_cdev, struct rt2x00_led, led_dev);
 252         unsigned int enabled = brightness != LED_OFF;
 253         u32 reg;
 254
 255         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 256
 257         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 258                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 259         else if (led->type == LED_TYPE_ACTIVITY)
 260                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 261
 262         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 263 }
 264
 265 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
 266                                unsigned long *delay_on,
 267                                unsigned long *delay_off)
 268 {
 269         struct rt2x00_led *led =
 270             container_of(led_cdev, struct rt2x00_led, led_dev);
 271         u32 reg;
 272
 273         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 274         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 275         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 276         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 277
 278         return 0;
 279 }
 280 #endif /* CONFIG_RT2500PCI_LEDS */
 281
 282 /*
 283  * Configuration handlers.
 284  */
 285 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
 286                                     const unsigned int filter_flags)
 287 {
 288         u32 reg;
 289
 290         /*
 291          * Start configuration steps.
 292          * Note that the version error will always be dropped
 293          * and broadcast frames will always be accepted since
 294          * there is no filter for it at this time.
 295          */
 296         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 297         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 298                            !(filter_flags & FIF_FCSFAIL));
 299         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 300                            !(filter_flags & FIF_PLCPFAIL));
 301         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 302                            !(filter_flags & FIF_CONTROL));
 303         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 304                            !(filter_flags & FIF_PROMISC_IN_BSS));
 305         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 306                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 307                            !rt2x00dev->intf_ap_count);
 308         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 309         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
 310                            !(filter_flags & FIF_ALLMULTI));
 311         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
 312         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 313 }
 314
 315 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
 316                                   struct rt2x00_intf *intf,
 317                                   struct rt2x00intf_conf *conf,
 318                                   const unsigned int flags)
 319 {
 320         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
 321         unsigned int bcn_preload;
 322         u32 reg;
 323
 324         if (flags & CONFIG_UPDATE_TYPE) {
 325                 /*
 326                  * Enable beacon config
 327                  */
 328                 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
 329                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 330                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 331                 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
 332                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 333
 334                 /*
 335                  * Enable synchronisation.
 336                  */
 337                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 338                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 339                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 340                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 341                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 342         }
 343
 344         if (flags & CONFIG_UPDATE_MAC)
 345                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 346                                               conf->mac, sizeof(conf->mac));
 347
 348         if (flags & CONFIG_UPDATE_BSSID)
 349                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 350                                               conf->bssid, sizeof(conf->bssid));
 351 }
 352
 353 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
 354                                  struct rt2x00lib_erp *erp)
 355 {
 356         int preamble_mask;
 357         u32 reg;
 358
 359         /*
 360          * When short preamble is enabled, we should set bit 0x08
 361          */
 362         preamble_mask = erp->short_preamble << 3;
 363
 364         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 365         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
 366                            erp->ack_timeout);
 367         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
 368                            erp->ack_consume_time);
 369         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 370
 371         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 372         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 373         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 374         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 375         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 376
 377         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 378         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 379         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 380         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 381         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 382
 383         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 384         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 385         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 386         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 387         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 388
 389         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 390         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 391         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 392         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 393         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 394 }
 395
 396 static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 397                                      const int basic_rate_mask)
 398 {
 399         rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
 400 }
 401
 402 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
 403                                      struct rf_channel *rf, const int txpower)
 404 {
 405         u8 r70;
 406
 407         /*
 408          * Set TXpower.
 409          */
 410         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 411
 412         /*
 413          * Switch on tuning bits.
 414          * For RT2523 devices we do not need to update the R1 register.
 415          */
 416         if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
 417                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 418         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 419
 420         /*
 421          * For RT2525 we should first set the channel to half band higher.
 422          */
 423         if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
 424                 static const u32 vals[] = {
 425                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
 426                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
 427                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
 428                         0x00080d2e, 0x00080d3a
 429                 };
 430
 431                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 432                 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
 433                 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 434                 if (rf->rf4)
 435                         rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 436         }
 437
 438         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 439         rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
 440         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 441         if (rf->rf4)
 442                 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 443
 444         /*
 445          * Channel 14 requires the Japan filter bit to be set.
 446          */
 447         r70 = 0x46;
 448         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
 449         rt2500pci_bbp_write(rt2x00dev, 70, r70);
 450
 451         msleep(1);
 452
 453         /*
 454          * Switch off tuning bits.
 455          * For RT2523 devices we do not need to update the R1 register.
 456          */
 457         if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
 458                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 459                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 460         }
 461
 462         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 463         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 464
 465         /*
 466          * Clear false CRC during channel switch.
 467          */
 468         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 469 }
 470
 471 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 472                                      const int txpower)
 473 {
 474         u32 rf3;
 475
 476         rt2x00_rf_read(rt2x00dev, 3, &rf3);
 477         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 478         rt2500pci_rf_write(rt2x00dev, 3, rf3);
 479 }
 480
 481 static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 482                                      struct antenna_setup *ant)
 483 {
 484         u32 reg;
 485         u8 r14;
 486         u8 r2;
 487
 488         /*
 489          * We should never come here because rt2x00lib is supposed
 490          * to catch this and send us the correct antenna explicitely.
 491          */
 492         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 493                ant->tx == ANTENNA_SW_DIVERSITY);
 494
 495         rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
 496         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
 497         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
 498
 499         /*
 500          * Configure the TX antenna.
 501          */
 502         switch (ant->tx) {
 503         case ANTENNA_A:
 504                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
 505                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
 506                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
 507                 break;
 508         case ANTENNA_B:
 509         default:
 510                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 511                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 512                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 513                 break;
 514         }
 515
 516         /*
 517          * Configure the RX antenna.
 518          */
 519         switch (ant->rx) {
 520         case ANTENNA_A:
 521                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
 522                 break;
 523         case ANTENNA_B:
 524         default:
 525                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 526                 break;
 527         }
 528
 529         /*
 530          * RT2525E and RT5222 need to flip TX I/Q
 531          */
 532         if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
 533             rt2x00_rf(&rt2x00dev->chip, RF5222)) {
 534                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
 535                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
 536                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
 537
 538                 /*
 539                  * RT2525E does not need RX I/Q Flip.
 540                  */
 541                 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
 542                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
 543         } else {
 544                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
 545                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
 546         }
 547
 548         rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
 549         rt2500pci_bbp_write(rt2x00dev, 14, r14);
 550         rt2500pci_bbp_write(rt2x00dev, 2, r2);
 551 }
 552
 553 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
 554                                       struct rt2x00lib_conf *libconf)
 555 {
 556         u32 reg;
 557
 558         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 559         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
 560         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 561
 562         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 563         rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
 564         rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
 565         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 566
 567         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 568         rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
 569         rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
 570         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 571
 572         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 573         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 574         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 575         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 576
 577         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 578         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 579                            libconf->conf->beacon_int * 16);
 580         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 581                            libconf->conf->beacon_int * 16);
 582         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 583 }
 584
 585 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
 586                              struct rt2x00lib_conf *libconf,
 587                              const unsigned int flags)
 588 {
 589         if (flags & CONFIG_UPDATE_PHYMODE)
 590                 rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
 591         if (flags & CONFIG_UPDATE_CHANNEL)
 592                 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
 593                                          libconf->conf->power_level);
 594         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
 595                 rt2500pci_config_txpower(rt2x00dev,
 596                                          libconf->conf->power_level);
 597         if (flags & CONFIG_UPDATE_ANTENNA)
 598                 rt2500pci_config_antenna(rt2x00dev, &libconf->ant);
 599         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 600                 rt2500pci_config_duration(rt2x00dev, libconf);
 601 }
 602
 603 /*
 604  * Link tuning
 605  */
 606 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
 607                                  struct link_qual *qual)
 608 {
 609         u32 reg;
 610
 611         /*
 612          * Update FCS error count from register.
 613          */
 614         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 615         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 616
 617         /*
 618          * Update False CCA count from register.
 619          */
 620         rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
 621         qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
 622 }
 623
 624 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 625 {
 626         rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
 627         rt2x00dev->link.vgc_level = 0x48;
 628 }
 629
 630 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 631 {
 632         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
 633         u8 r17;
 634
 635         /*
 636          * To prevent collisions with MAC ASIC on chipsets
 637          * up to version C the link tuning should halt after 20
 638          * seconds while being associated.
 639          */
 640         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
 641             rt2x00dev->intf_associated &&
 642             rt2x00dev->link.count > 20)
 643                 return;
 644
 645         rt2500pci_bbp_read(rt2x00dev, 17, &r17);
 646
 647         /*
 648          * Chipset versions C and lower should directly continue
 649          * to the dynamic CCA tuning. Chipset version D and higher
 650          * should go straight to dynamic CCA tuning when they
 651          * are not associated.
 652          */
 653         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
 654             !rt2x00dev->intf_associated)
 655                 goto dynamic_cca_tune;
 656
 657         /*
 658          * A too low RSSI will cause too much false CCA which will
 659          * then corrupt the R17 tuning. To remidy this the tuning should
 660          * be stopped (While making sure the R17 value will not exceed limits)
 661          */
 662         if (rssi < -80 && rt2x00dev->link.count > 20) {
 663                 if (r17 >= 0x41) {
 664                         r17 = rt2x00dev->link.vgc_level;
 665                         rt2500pci_bbp_write(rt2x00dev, 17, r17);
 666                 }
 667                 return;
 668         }
 669
 670         /*
 671          * Special big-R17 for short distance
 672          */
 673         if (rssi >= -58) {
 674                 if (r17 != 0x50)
 675                         rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
 676                 return;
 677         }
 678
 679         /*
 680          * Special mid-R17 for middle distance
 681          */
 682         if (rssi >= -74) {
 683                 if (r17 != 0x41)
 684                         rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
 685                 return;
 686         }
 687
 688         /*
 689          * Leave short or middle distance condition, restore r17
 690          * to the dynamic tuning range.
 691          */
 692         if (r17 >= 0x41) {
 693                 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
 694                 return;
 695         }
 696
 697 dynamic_cca_tune:
 698
 699         /*
 700          * R17 is inside the dynamic tuning range,
 701          * start tuning the link based on the false cca counter.
 702          */
 703         if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
 704                 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
 705                 rt2x00dev->link.vgc_level = r17;
 706         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
 707                 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
 708                 rt2x00dev->link.vgc_level = r17;
 709         }
 710 }
 711
 712 /*
 713  * Initialization functions.
 714  */
 715 static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
 716                                    struct queue_entry *entry)
 717 {
 718         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
 719         u32 word;
 720
 721         rt2x00_desc_read(priv_rx->desc, 1, &word);
 722         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
 723         rt2x00_desc_write(priv_rx->desc, 1, word);
 724
 725         rt2x00_desc_read(priv_rx->desc, 0, &word);
 726         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 727         rt2x00_desc_write(priv_rx->desc, 0, word);
 728 }
 729
 730 static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
 731                                    struct queue_entry *entry)
 732 {
 733         struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
 734         u32 word;
 735
 736         rt2x00_desc_read(priv_tx->desc, 1, &word);
 737         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
 738         rt2x00_desc_write(priv_tx->desc, 1, word);
 739
 740         rt2x00_desc_read(priv_tx->desc, 0, &word);
 741         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 742         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 743         rt2x00_desc_write(priv_tx->desc, 0, word);
 744 }
 745
 746 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
 747 {
 748         struct queue_entry_priv_pci_rx *priv_rx;
 749         struct queue_entry_priv_pci_tx *priv_tx;
 750         u32 reg;
 751
 752         /*
 753          * Initialize registers.
 754          */
 755         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 756         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 757         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 758         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 759         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 760         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 761
 762         priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
 763         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 764         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 765                            priv_tx->desc_dma);
 766         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 767
 768         priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
 769         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 770         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 771                            priv_tx->desc_dma);
 772         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 773
 774         priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
 775         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 776         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 777                            priv_tx->desc_dma);
 778         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 779
 780         priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
 781         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 782         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 783                            priv_tx->desc_dma);
 784         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 785
 786         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 787         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 788         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 789         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 790
 791         priv_rx = rt2x00dev->rx->entries[0].priv_data;
 792         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 793         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma);
 794         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 795
 796         return 0;
 797 }
 798
 799 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
 800 {
 801         u32 reg;
 802
 803         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 804         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 805         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
 806         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 807
 808         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 809         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 810         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 811         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 812         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 813
 814         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 815         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 816                            rt2x00dev->rx->data_size / 128);
 817         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 818
 819         /*
 820          * Always use CWmin and CWmax set in descriptor.
 821          */
 822         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 823         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
 824         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 825
 826         rt2x00pci_register_write(rt2x00dev, CNT3, 0);
 827
 828         rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
 829         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
 830         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
 831         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
 832         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
 833         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
 834         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
 835         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
 836         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
 837         rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
 838
 839         rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
 840         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
 841         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
 842         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
 843         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
 844         rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
 845
 846         rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
 847         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
 848         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
 849         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
 850         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
 851         rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
 852
 853         rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
 854         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
 855         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
 856         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
 857         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
 858         rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
 859
 860         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 861         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
 862         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 863         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
 864         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 865         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
 866         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 867         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
 868         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
 869         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 870
 871         rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
 872         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
 873         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
 874         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
 875         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
 876         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
 877         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
 878         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
 879         rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
 880
 881         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 882
 883         rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
 884         rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
 885
 886         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 887                 return -EBUSY;
 888
 889         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
 890         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 891
 892         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 893         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 894         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 895
 896         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 897         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 898         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
 899         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
 900         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 901         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
 902         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
 903         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 904
 905         rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
 906
 907         rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
 908
 909         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 910         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 911         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 912         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 913         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 914
 915         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 916         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 917         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 918         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 919
 920         /*
 921          * We must clear the FCS and FIFO error count.
 922          * These registers are cleared on read,
 923          * so we may pass a useless variable to store the value.
 924          */
 925         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 926         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 927
 928         return 0;
 929 }
 930
 931 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 932 {
 933         unsigned int i;
 934         u16 eeprom;
 935         u8 reg_id;
 936         u8 value;
 937
 938         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 939                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
 940                 if ((value != 0xff) && (value != 0x00))
 941                         goto continue_csr_init;
 942                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
 943                 udelay(REGISTER_BUSY_DELAY);
 944         }
 945
 946         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 947         return -EACCES;
 948
 949 continue_csr_init:
 950         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
 951         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
 952         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
 953         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
 954         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
 955         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
 956         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
 957         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
 958         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
 959         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
 960         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
 961         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
 962         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
 963         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
 964         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
 965         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
 966         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
 967         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
 968         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
 969         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
 970         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
 971         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
 972         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
 973         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
 974         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
 975         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
 976         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
 977         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
 978         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
 979         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
 980
 981         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 982                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 983
 984                 if (eeprom != 0xffff && eeprom != 0x0000) {
 985                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 986                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 987                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
 988                 }
 989         }
 990
 991         return 0;
 992 }
 993
 994 /*
 995  * Device state switch handlers.
 996  */
 997 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 998                                 enum dev_state state)
 999 {
1000         u32 reg;
1001
1002         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1003         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1004                            state == STATE_RADIO_RX_OFF);
1005         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1006 }
1007
1008 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1009                                  enum dev_state state)
1010 {
1011         int mask = (state == STATE_RADIO_IRQ_OFF);
1012         u32 reg;
1013
1014         /*
1015          * When interrupts are being enabled, the interrupt registers
1016          * should clear the register to assure a clean state.
1017          */
1018         if (state == STATE_RADIO_IRQ_ON) {
1019                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1020                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1021         }
1022
1023         /*
1024          * Only toggle the interrupts bits we are going to use.
1025          * Non-checked interrupt bits are disabled by default.
1026          */
1027         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1028         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1029         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1030         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1031         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1032         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1033         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1034 }
1035
1036 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1037 {
1038         /*
1039          * Initialize all registers.
1040          */
1041         if (rt2500pci_init_queues(rt2x00dev) ||
1042             rt2500pci_init_registers(rt2x00dev) ||
1043             rt2500pci_init_bbp(rt2x00dev)) {
1044                 ERROR(rt2x00dev, "Register initialization failed.\n");
1045                 return -EIO;
1046         }
1047
1048         /*
1049          * Enable interrupts.
1050          */
1051         rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1052
1053         return 0;
1054 }
1055
1056 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1057 {
1058         u32 reg;
1059
1060         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1061
1062         /*
1063          * Disable synchronisation.
1064          */
1065         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1066
1067         /*
1068          * Cancel RX and TX.
1069          */
1070         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1071         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1072         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1073
1074         /*
1075          * Disable interrupts.
1076          */
1077         rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1078 }
1079
1080 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1081                                enum dev_state state)
1082 {
1083         u32 reg;
1084         unsigned int i;
1085         char put_to_sleep;
1086         char bbp_state;
1087         char rf_state;
1088
1089         put_to_sleep = (state != STATE_AWAKE);
1090
1091         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1092         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1093         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1094         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1095         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1096         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1097
1098         /*
1099          * Device is not guaranteed to be in the requested state yet.
1100          * We must wait until the register indicates that the
1101          * device has entered the correct state.
1102          */
1103         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1104                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1105                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1106                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1107                 if (bbp_state == state && rf_state == state)
1108                         return 0;
1109                 msleep(10);
1110         }
1111
1112         NOTICE(rt2x00dev, "Device failed to enter state %d, "
1113                "current device state: bbp %d and rf %d.\n",
1114                state, bbp_state, rf_state);
1115
1116         return -EBUSY;
1117 }
1118
1119 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1120                                       enum dev_state state)
1121 {
1122         int retval = 0;
1123
1124         switch (state) {
1125         case STATE_RADIO_ON:
1126                 retval = rt2500pci_enable_radio(rt2x00dev);
1127                 break;
1128         case STATE_RADIO_OFF:
1129                 rt2500pci_disable_radio(rt2x00dev);
1130                 break;
1131         case STATE_RADIO_RX_ON:
1132         case STATE_RADIO_RX_ON_LINK:
1133                 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1134                 break;
1135         case STATE_RADIO_RX_OFF:
1136         case STATE_RADIO_RX_OFF_LINK:
1137                 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1138                 break;
1139         case STATE_DEEP_SLEEP:
1140         case STATE_SLEEP:
1141         case STATE_STANDBY:
1142         case STATE_AWAKE:
1143                 retval = rt2500pci_set_state(rt2x00dev, state);
1144                 break;
1145         default:
1146                 retval = -ENOTSUPP;
1147                 break;
1148         }
1149
1150         return retval;
1151 }
1152
1153 /*
1154  * TX descriptor initialization
1155  */
1156 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1157                                     struct sk_buff *skb,
1158                                     struct txentry_desc *txdesc)
1159 {
1160         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1161         __le32 *txd = skbdesc->desc;
1162         u32 word;
1163
1164         /*
1165          * Start writing the descriptor words.
1166          */
1167         rt2x00_desc_read(txd, 2, &word);
1168         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1169         rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1170         rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1171         rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1172         rt2x00_desc_write(txd, 2, word);
1173
1174         rt2x00_desc_read(txd, 3, &word);
1175         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1176         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1177         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1178         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1179         rt2x00_desc_write(txd, 3, word);
1180
1181         rt2x00_desc_read(txd, 10, &word);
1182         rt2x00_set_field32(&word, TXD_W10_RTS,
1183                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1184         rt2x00_desc_write(txd, 10, word);
1185
1186         rt2x00_desc_read(txd, 0, &word);
1187         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1188         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1189         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1190                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1191         rt2x00_set_field32(&word, TXD_W0_ACK,
1192                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1193         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1194                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1195         rt2x00_set_field32(&word, TXD_W0_OFDM,
1196                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1197         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1198         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1199         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1200                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1201         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1202         rt2x00_desc_write(txd, 0, word);
1203 }
1204
1205 /*
1206  * TX data initialization
1207  */
1208 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1209                                     const enum data_queue_qid queue)
1210 {
1211         u32 reg;
1212
1213         if (queue == QID_BEACON) {
1214                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1215                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1216                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1217                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1218                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1219                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1220                 }
1221                 return;
1222         }
1223
1224         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1225         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1226         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1227         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1228         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1229 }
1230
1231 /*
1232  * RX control handlers
1233  */
1234 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1235                                   struct rxdone_entry_desc *rxdesc)
1236 {
1237         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1238         u32 word0;
1239         u32 word2;
1240
1241         rt2x00_desc_read(priv_rx->desc, 0, &word0);
1242         rt2x00_desc_read(priv_rx->desc, 2, &word2);
1243
1244         rxdesc->flags = 0;
1245         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1246                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1247         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1248                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1249
1250         /*
1251          * Obtain the status about this packet.
1252          * When frame was received with an OFDM bitrate,
1253          * the signal is the PLCP value. If it was received with
1254          * a CCK bitrate the signal is the rate in 100kbit/s.
1255          */
1256         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1257         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1258             entry->queue->rt2x00dev->rssi_offset;
1259         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1260
1261         rxdesc->dev_flags = 0;
1262         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1263                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1264         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1265                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1266 }
1267
1268 /*
1269  * Interrupt functions.
1270  */
1271 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1272                              const enum data_queue_qid queue_idx)
1273 {
1274         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1275         struct queue_entry_priv_pci_tx *priv_tx;
1276         struct queue_entry *entry;
1277         struct txdone_entry_desc txdesc;
1278         u32 word;
1279
1280         while (!rt2x00queue_empty(queue)) {
1281                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1282                 priv_tx = entry->priv_data;
1283                 rt2x00_desc_read(priv_tx->desc, 0, &word);
1284
1285                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1286                     !rt2x00_get_field32(word, TXD_W0_VALID))
1287                         break;
1288
1289                 /*
1290                  * Obtain the status about this packet.
1291                  */
1292                 txdesc.flags = 0;
1293                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1294                 case 0: /* Success */
1295                 case 1: /* Success with retry */
1296                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1297                         break;
1298                 case 2: /* Failure, excessive retries */
1299                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1300                         /* Don't break, this is a failed frame! */
1301                 default: /* Failure */
1302                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1303                 }
1304                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1305
1306                 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1307         }
1308 }
1309
1310 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1311 {
1312         struct rt2x00_dev *rt2x00dev = dev_instance;
1313         u32 reg;
1314
1315         /*
1316          * Get the interrupt sources & saved to local variable.
1317          * Write register value back to clear pending interrupts.
1318          */
1319         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1320         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1321
1322         if (!reg)
1323                 return IRQ_NONE;
1324
1325         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1326                 return IRQ_HANDLED;
1327
1328         /*
1329          * Handle interrupts, walk through all bits
1330          * and run the tasks, the bits are checked in order of
1331          * priority.
1332          */
1333
1334         /*
1335          * 1 - Beacon timer expired interrupt.
1336          */
1337         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1338                 rt2x00lib_beacondone(rt2x00dev);
1339
1340         /*
1341          * 2 - Rx ring done interrupt.
1342          */
1343         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1344                 rt2x00pci_rxdone(rt2x00dev);
1345
1346         /*
1347          * 3 - Atim ring transmit done interrupt.
1348          */
1349         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1350                 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1351
1352         /*
1353          * 4 - Priority ring transmit done interrupt.
1354          */
1355         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1356                 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
1357
1358         /*
1359          * 5 - Tx ring transmit done interrupt.
1360          */
1361         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1362                 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1363
1364         return IRQ_HANDLED;
1365 }
1366
1367 /*
1368  * Device probe functions.
1369  */
1370 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1371 {
1372         struct eeprom_93cx6 eeprom;
1373         u32 reg;
1374         u16 word;
1375         u8 *mac;
1376
1377         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1378
1379         eeprom.data = rt2x00dev;
1380         eeprom.register_read = rt2500pci_eepromregister_read;
1381         eeprom.register_write = rt2500pci_eepromregister_write;
1382         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1383             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1384         eeprom.reg_data_in = 0;
1385         eeprom.reg_data_out = 0;
1386         eeprom.reg_data_clock = 0;
1387         eeprom.reg_chip_select = 0;
1388
1389         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1390                                EEPROM_SIZE / sizeof(u16));
1391
1392         /*
1393          * Start validation of the data that has been read.
1394          */
1395         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1396         if (!is_valid_ether_addr(mac)) {
1397                 DECLARE_MAC_BUF(macbuf);
1398
1399                 random_ether_addr(mac);
1400                 EEPROM(rt2x00dev, "MAC: %s\n",
1401                        print_mac(macbuf, mac));
1402         }
1403
1404         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1405         if (word == 0xffff) {
1406                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1407                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1408                                    ANTENNA_SW_DIVERSITY);
1409                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1410                                    ANTENNA_SW_DIVERSITY);
1411                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1412                                    LED_MODE_DEFAULT);
1413                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1414                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1415                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1416                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1417                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1418         }
1419
1420         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1421         if (word == 0xffff) {
1422                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1423                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1424                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1425                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1426                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1427         }
1428
1429         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1430         if (word == 0xffff) {
1431                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1432                                    DEFAULT_RSSI_OFFSET);
1433                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1434                 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1435         }
1436
1437         return 0;
1438 }
1439
1440 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1441 {
1442         u32 reg;
1443         u16 value;
1444         u16 eeprom;
1445
1446         /*
1447          * Read EEPROM word for configuration.
1448          */
1449         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1450
1451         /*
1452          * Identify RF chipset.
1453          */
1454         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1455         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1456         rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1457
1458         if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1459             !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1460             !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1461             !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1462             !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1463             !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1464                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1465                 return -ENODEV;
1466         }
1467
1468         /*
1469          * Identify default antenna configuration.
1470          */
1471         rt2x00dev->default_ant.tx =
1472             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1473         rt2x00dev->default_ant.rx =
1474             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1475
1476         /*
1477          * Store led mode, for correct led behaviour.
1478          */
1479 #ifdef CONFIG_RT2500PCI_LEDS
1480         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1481
1482         rt2x00dev->led_radio.rt2x00dev = rt2x00dev;
1483         rt2x00dev->led_radio.type = LED_TYPE_RADIO;
1484         rt2x00dev->led_radio.led_dev.brightness_set =
1485             rt2500pci_brightness_set;
1486         rt2x00dev->led_radio.led_dev.blink_set =
1487             rt2500pci_blink_set;
1488         rt2x00dev->led_radio.flags = LED_INITIALIZED;
1489
1490         if (value == LED_MODE_TXRX_ACTIVITY) {
1491                 rt2x00dev->led_qual.rt2x00dev = rt2x00dev;
1492                 rt2x00dev->led_qual.type = LED_TYPE_ACTIVITY;
1493                 rt2x00dev->led_qual.led_dev.brightness_set =
1494                     rt2500pci_brightness_set;
1495                 rt2x00dev->led_qual.led_dev.blink_set =
1496                     rt2500pci_blink_set;
1497                 rt2x00dev->led_qual.flags = LED_INITIALIZED;
1498         }
1499 #endif /* CONFIG_RT2500PCI_LEDS */
1500
1501         /*
1502          * Detect if this device has an hardware controlled radio.
1503          */
1504 #ifdef CONFIG_RT2500PCI_RFKILL
1505         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1506                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1507 #endif /* CONFIG_RT2500PCI_RFKILL */
1508
1509         /*
1510          * Check if the BBP tuning should be enabled.
1511          */
1512         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1513
1514         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1515                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1516
1517         /*
1518          * Read the RSSI <-> dBm offset information.
1519          */
1520         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1521         rt2x00dev->rssi_offset =
1522             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1523
1524         return 0;
1525 }
1526
1527 /*
1528  * RF value list for RF2522
1529  * Supports: 2.4 GHz
1530  */
1531 static const struct rf_channel rf_vals_bg_2522[] = {
1532         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1533         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1534         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1535         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1536         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1537         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1538         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1539         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1540         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1541         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1542         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1543         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1544         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1545         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1546 };
1547
1548 /*
1549  * RF value list for RF2523
1550  * Supports: 2.4 GHz
1551  */
1552 static const struct rf_channel rf_vals_bg_2523[] = {
1553         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1554         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1555         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1556         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1557         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1558         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1559         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1560         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1561         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1562         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1563         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1564         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1565         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1566         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1567 };
1568
1569 /*
1570  * RF value list for RF2524
1571  * Supports: 2.4 GHz
1572  */
1573 static const struct rf_channel rf_vals_bg_2524[] = {
1574         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1575         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1576         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1577         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1578         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1579         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1580         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1581         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1582         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1583         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1584         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1585         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1586         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1587         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1588 };
1589
1590 /*
1591  * RF value list for RF2525
1592  * Supports: 2.4 GHz
1593  */
1594 static const struct rf_channel rf_vals_bg_2525[] = {
1595         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1596         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1597         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1598         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1599         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1600         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1601         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1602         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1603         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1604         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1605         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1606         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1607         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1608         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1609 };
1610
1611 /*
1612  * RF value list for RF2525e
1613  * Supports: 2.4 GHz
1614  */
1615 static const struct rf_channel rf_vals_bg_2525e[] = {
1616         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1617         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1618         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1619         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1620         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1621         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1622         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1623         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1624         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1625         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1626         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1627         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1628         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1629         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1630 };
1631
1632 /*
1633  * RF value list for RF5222
1634  * Supports: 2.4 GHz & 5.2 GHz
1635  */
1636 static const struct rf_channel rf_vals_5222[] = {
1637         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1638         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1639         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1640         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1641         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1642         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1643         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1644         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1645         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1646         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1647         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1648         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1649         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1650         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1651
1652         /* 802.11 UNI / HyperLan 2 */
1653         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1654         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1655         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1656         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1657         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1658         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1659         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1660         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1661
1662         /* 802.11 HyperLan 2 */
1663         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1664         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1665         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1666         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1667         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1668         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1669         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1670         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1671         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1672         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1673
1674         /* 802.11 UNII */
1675         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1676         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1677         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1678         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1679         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1680 };
1681
1682 static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1683 {
1684         struct hw_mode_spec *spec = &rt2x00dev->spec;
1685         u8 *txpower;
1686         unsigned int i;
1687
1688         /*
1689          * Initialize all hw fields.
1690          */
1691         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1692                                IEEE80211_HW_SIGNAL_DBM;
1693
1694         rt2x00dev->hw->extra_tx_headroom = 0;
1695
1696         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1697         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1698                                 rt2x00_eeprom_addr(rt2x00dev,
1699                                                    EEPROM_MAC_ADDR_0));
1700
1701         /*
1702          * Convert tx_power array in eeprom.
1703          */
1704         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1705         for (i = 0; i < 14; i++)
1706                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1707
1708         /*
1709          * Initialize hw_mode information.
1710          */
1711         spec->supported_bands = SUPPORT_BAND_2GHZ;
1712         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1713         spec->tx_power_a = NULL;
1714         spec->tx_power_bg = txpower;
1715         spec->tx_power_default = DEFAULT_TXPOWER;
1716
1717         if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1718                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1719                 spec->channels = rf_vals_bg_2522;
1720         } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1721                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1722                 spec->channels = rf_vals_bg_2523;
1723         } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1724                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1725                 spec->channels = rf_vals_bg_2524;
1726         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1727                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1728                 spec->channels = rf_vals_bg_2525;
1729         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1730                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1731                 spec->channels = rf_vals_bg_2525e;
1732         } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1733                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1734                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1735                 spec->channels = rf_vals_5222;
1736         }
1737 }
1738
1739 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1740 {
1741         int retval;
1742
1743         /*
1744          * Allocate eeprom data.
1745          */
1746         retval = rt2500pci_validate_eeprom(rt2x00dev);
1747         if (retval)
1748                 return retval;
1749
1750         retval = rt2500pci_init_eeprom(rt2x00dev);
1751         if (retval)
1752                 return retval;
1753
1754         /*
1755          * Initialize hw specifications.
1756          */
1757         rt2500pci_probe_hw_mode(rt2x00dev);
1758
1759         /*
1760          * This device requires the atim queue
1761          */
1762         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1763
1764         /*
1765          * Set the rssi offset.
1766          */
1767         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1768
1769         return 0;
1770 }
1771
1772 /*
1773  * IEEE80211 stack callback functions.
1774  */
1775 static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1776                                      u32 short_retry, u32 long_retry)
1777 {
1778         struct rt2x00_dev *rt2x00dev = hw->priv;
1779         u32 reg;
1780
1781         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1782         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1783         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1784         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1785
1786         return 0;
1787 }
1788
1789 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1790 {
1791         struct rt2x00_dev *rt2x00dev = hw->priv;
1792         u64 tsf;
1793         u32 reg;
1794
1795         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1796         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1797         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1798         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1799
1800         return tsf;
1801 }
1802
1803 static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1804                                    struct ieee80211_tx_control *control)
1805 {
1806         struct rt2x00_dev *rt2x00dev = hw->priv;
1807         struct rt2x00_intf *intf = vif_to_intf(control->vif);
1808         struct queue_entry_priv_pci_tx *priv_tx;
1809         struct skb_frame_desc *skbdesc;
1810         u32 reg;
1811
1812         if (unlikely(!intf->beacon))
1813                 return -ENOBUFS;
1814
1815         priv_tx = intf->beacon->priv_data;
1816
1817         /*
1818          * Fill in skb descriptor
1819          */
1820         skbdesc = get_skb_frame_desc(skb);
1821         memset(skbdesc, 0, sizeof(*skbdesc));
1822         skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1823         skbdesc->data = skb->data;
1824         skbdesc->data_len = skb->len;
1825         skbdesc->desc = priv_tx->desc;
1826         skbdesc->desc_len = intf->beacon->queue->desc_size;
1827         skbdesc->entry = intf->beacon;
1828
1829         /*
1830          * Disable beaconing while we are reloading the beacon data,
1831          * otherwise we might be sending out invalid data.
1832          */
1833         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1834         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1835         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1836         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1837         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1838
1839         /*
1840          * Enable beacon generation.
1841          * Write entire beacon with descriptor to register,
1842          * and kick the beacon generator.
1843          */
1844         rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1845         memcpy(priv_tx->data, skb->data, skb->len);
1846         rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
1847
1848         return 0;
1849 }
1850
1851 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1852 {
1853         struct rt2x00_dev *rt2x00dev = hw->priv;
1854         u32 reg;
1855
1856         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1857         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1858 }
1859
1860 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1861         .tx                     = rt2x00mac_tx,
1862         .start                  = rt2x00mac_start,
1863         .stop                   = rt2x00mac_stop,
1864         .add_interface          = rt2x00mac_add_interface,
1865         .remove_interface       = rt2x00mac_remove_interface,
1866         .config                 = rt2x00mac_config,
1867         .config_interface       = rt2x00mac_config_interface,
1868         .configure_filter       = rt2x00mac_configure_filter,
1869         .get_stats              = rt2x00mac_get_stats,
1870         .set_retry_limit        = rt2500pci_set_retry_limit,
1871         .bss_info_changed       = rt2x00mac_bss_info_changed,
1872         .conf_tx                = rt2x00mac_conf_tx,
1873         .get_tx_stats           = rt2x00mac_get_tx_stats,
1874         .get_tsf                = rt2500pci_get_tsf,
1875         .beacon_update          = rt2500pci_beacon_update,
1876         .tx_last_beacon         = rt2500pci_tx_last_beacon,
1877 };
1878
1879 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1880         .irq_handler            = rt2500pci_interrupt,
1881         .probe_hw               = rt2500pci_probe_hw,
1882         .initialize             = rt2x00pci_initialize,
1883         .uninitialize           = rt2x00pci_uninitialize,
1884         .init_rxentry           = rt2500pci_init_rxentry,
1885         .init_txentry           = rt2500pci_init_txentry,
1886         .set_device_state       = rt2500pci_set_device_state,
1887         .rfkill_poll            = rt2500pci_rfkill_poll,
1888         .link_stats             = rt2500pci_link_stats,
1889         .reset_tuner            = rt2500pci_reset_tuner,
1890         .link_tuner             = rt2500pci_link_tuner,
1891         .write_tx_desc          = rt2500pci_write_tx_desc,
1892         .write_tx_data          = rt2x00pci_write_tx_data,
1893         .kick_tx_queue          = rt2500pci_kick_tx_queue,
1894         .fill_rxdone            = rt2500pci_fill_rxdone,
1895         .config_filter          = rt2500pci_config_filter,
1896         .config_intf            = rt2500pci_config_intf,
1897         .config_erp             = rt2500pci_config_erp,
1898         .config                 = rt2500pci_config,
1899 };
1900
1901 static const struct data_queue_desc rt2500pci_queue_rx = {
1902         .entry_num              = RX_ENTRIES,
1903         .data_size              = DATA_FRAME_SIZE,
1904         .desc_size              = RXD_DESC_SIZE,
1905         .priv_size              = sizeof(struct queue_entry_priv_pci_rx),
1906 };
1907
1908 static const struct data_queue_desc rt2500pci_queue_tx = {
1909         .entry_num              = TX_ENTRIES,
1910         .data_size              = DATA_FRAME_SIZE,
1911         .desc_size              = TXD_DESC_SIZE,
1912         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1913 };
1914
1915 static const struct data_queue_desc rt2500pci_queue_bcn = {
1916         .entry_num              = BEACON_ENTRIES,
1917         .data_size              = MGMT_FRAME_SIZE,
1918         .desc_size              = TXD_DESC_SIZE,
1919         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1920 };
1921
1922 static const struct data_queue_desc rt2500pci_queue_atim = {
1923         .entry_num              = ATIM_ENTRIES,
1924         .data_size              = DATA_FRAME_SIZE,
1925         .desc_size              = TXD_DESC_SIZE,
1926         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1927 };
1928
1929 static const struct rt2x00_ops rt2500pci_ops = {
1930         .name           = KBUILD_MODNAME,
1931         .max_sta_intf   = 1,
1932         .max_ap_intf    = 1,
1933         .eeprom_size    = EEPROM_SIZE,
1934         .rf_size        = RF_SIZE,
1935         .tx_queues      = NUM_TX_QUEUES,
1936         .rx             = &rt2500pci_queue_rx,
1937         .tx             = &rt2500pci_queue_tx,
1938         .bcn            = &rt2500pci_queue_bcn,
1939         .atim           = &rt2500pci_queue_atim,
1940         .lib            = &rt2500pci_rt2x00_ops,
1941         .hw             = &rt2500pci_mac80211_ops,
1942 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1943         .debugfs        = &rt2500pci_rt2x00debug,
1944 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1945 };
1946
1947 /*
1948  * RT2500pci module information.
1949  */
1950 static struct pci_device_id rt2500pci_device_table[] = {
1951         { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1952         { 0, }
1953 };
1954
1955 MODULE_AUTHOR(DRV_PROJECT);
1956 MODULE_VERSION(DRV_VERSION);
1957 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1958 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1959 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1960 MODULE_LICENSE("GPL");
1961
1962 static struct pci_driver rt2500pci_driver = {
1963         .name           = KBUILD_MODNAME,
1964         .id_table       = rt2500pci_device_table,
1965         .probe          = rt2x00pci_probe,
1966         .remove         = __devexit_p(rt2x00pci_remove),
1967         .suspend        = rt2x00pci_suspend,
1968         .resume         = rt2x00pci_resume,
1969 };
1970
1971 static int __init rt2500pci_init(void)
1972 {
1973         return pci_register_driver(&rt2500pci_driver);
1974 }
1975
1976 static void __exit rt2500pci_exit(void)
1977 {
1978         pci_unregister_driver(&rt2500pci_driver);
1979 }
1980
1981 module_init(rt2500pci_init);
1982 module_exit(rt2500pci_exit);