2 * PCI / PCI-X / PCI-Express support for 4xx parts
4 * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
6 * Most PCI Express code is coming from Stefan Roese implementation for
7 * arch/ppc in the Denx tree, slightly reworked by me.
9 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 * Some of that comes itself from a previous implementation for 440SPE only
14 * Copyright (c) 2005 Cisco Systems. All rights reserved.
15 * Roland Dreier <rolandd@cisco.com>
21 #include <linux/kernel.h>
22 #include <linux/pci.h>
23 #include <linux/init.h>
25 #include <linux/bootmem.h>
26 #include <linux/delay.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/machdep.h>
32 #include <asm/dcr-regs.h>
34 #include "ppc4xx_pci.h"
36 static int dma_offset_set;
38 /* Move that to a useable header */
39 extern unsigned long total_memory;
41 #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
42 #define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
44 #ifdef CONFIG_RESOURCES_64BIT
45 #define RES_TO_U32_LOW(val) U64_TO_U32_LOW(val)
46 #define RES_TO_U32_HIGH(val) U64_TO_U32_HIGH(val)
48 #define RES_TO_U32_LOW(val) (val)
49 #define RES_TO_U32_HIGH(val) (0)
52 static inline int ppc440spe_revA(void)
54 /* Catch both 440SPe variants, with and without RAID6 support */
55 if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890)
61 static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev)
63 struct pci_controller *hose;
66 if (dev->devfn != 0 || dev->bus->self != NULL)
69 hose = pci_bus_to_host(dev->bus);
73 if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") &&
74 !of_device_is_compatible(hose->dn, "ibm,plb-pcix") &&
75 !of_device_is_compatible(hose->dn, "ibm,plb-pci"))
78 if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") ||
79 of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) {
80 hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM;
83 /* Hide the PCI host BARs from the kernel as their content doesn't
84 * fit well in the resource management
86 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
87 dev->resource[i].start = dev->resource[i].end = 0;
88 dev->resource[i].flags = 0;
91 printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n",
94 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge);
96 static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
103 int pna = of_n_addr_cells(hose->dn);
108 res->end = size = 0x80000000;
109 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
111 /* Get dma-ranges property */
112 ranges = of_get_property(hose->dn, "dma-ranges", &rlen);
117 while ((rlen -= np * 4) >= 0) {
118 u32 pci_space = ranges[0];
119 u64 pci_addr = of_read_number(ranges + 1, 2);
120 u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3);
121 size = of_read_number(ranges + pna + 3, 2);
123 if (cpu_addr == OF_BAD_ADDR || size == 0)
126 /* We only care about memory */
127 if ((pci_space & 0x03000000) != 0x02000000)
130 /* We currently only support memory at 0, and pci_addr
131 * within 32 bits space
133 if (cpu_addr != 0 || pci_addr > 0xffffffff) {
134 printk(KERN_WARNING "%s: Ignored unsupported dma range"
135 " 0x%016llx...0x%016llx -> 0x%016llx\n",
137 pci_addr, pci_addr + size - 1, cpu_addr);
141 /* Check if not prefetchable */
142 if (!(pci_space & 0x40000000))
143 res->flags &= ~IORESOURCE_PREFETCH;
147 res->start = pci_addr;
148 #ifndef CONFIG_RESOURCES_64BIT
149 /* Beware of 32 bits resources */
150 if ((pci_addr + size) > 0x100000000ull)
151 res->end = 0xffffffff;
154 res->end = res->start + size - 1;
158 /* We only support one global DMA offset */
159 if (dma_offset_set && pci_dram_offset != res->start) {
160 printk(KERN_ERR "%s: dma-ranges(s) mismatch\n",
161 hose->dn->full_name);
165 /* Check that we can fit all of memory as we don't support
168 if (size < total_memory) {
169 printk(KERN_ERR "%s: dma-ranges too small "
170 "(size=%llx total_memory=%lx)\n",
171 hose->dn->full_name, size, total_memory);
175 /* Check we are a power of 2 size and that base is a multiple of size*/
176 if (!is_power_of_2(size) ||
177 (res->start & (size - 1)) != 0) {
178 printk(KERN_ERR "%s: dma-ranges unaligned\n",
179 hose->dn->full_name);
183 /* Check that we are fully contained within 32 bits space */
184 if (res->end > 0xffffffff) {
185 printk(KERN_ERR "%s: dma-ranges outside of 32 bits space\n",
186 hose->dn->full_name);
191 pci_dram_offset = res->start;
193 printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n",
202 static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
205 u32 la, ma, pcila, pciha;
208 /* Setup outbound memory windows */
209 for (i = j = 0; i < 3; i++) {
210 struct resource *res = &hose->mem_resources[i];
212 /* we only care about memory windows */
213 if (!(res->flags & IORESOURCE_MEM))
216 printk(KERN_WARNING "%s: Too many ranges\n",
217 hose->dn->full_name);
221 /* Calculate register values */
223 pciha = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
224 pcila = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
226 ma = res->end + 1 - res->start;
227 if (!is_power_of_2(ma) || ma < 0x1000 || ma > 0xffffffffu) {
228 printk(KERN_WARNING "%s: Resource out of range\n",
229 hose->dn->full_name);
232 ma = (0xffffffffu << ilog2(ma)) | 0x1;
233 if (res->flags & IORESOURCE_PREFETCH)
236 /* Program register values */
237 writel(la, reg + PCIL0_PMM0LA + (0x10 * j));
238 writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * j));
239 writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * j));
240 writel(ma, reg + PCIL0_PMM0MA + (0x10 * j));
245 static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose,
247 const struct resource *res)
249 resource_size_t size = res->end - res->start + 1;
252 /* Calculate window size */
253 sa = (0xffffffffu << ilog2(size)) | 1;
256 /* RAM is always at 0 local for now */
257 writel(0, reg + PCIL0_PTM1LA);
258 writel(sa, reg + PCIL0_PTM1MS);
260 /* Map on PCI side */
261 early_write_config_dword(hose, hose->first_busno, 0,
262 PCI_BASE_ADDRESS_1, res->start);
263 early_write_config_dword(hose, hose->first_busno, 0,
264 PCI_BASE_ADDRESS_2, 0x00000000);
265 early_write_config_word(hose, hose->first_busno, 0,
266 PCI_COMMAND, 0x0006);
269 static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
272 struct resource rsrc_cfg;
273 struct resource rsrc_reg;
274 struct resource dma_window;
275 struct pci_controller *hose = NULL;
276 void __iomem *reg = NULL;
277 const int *bus_range;
280 /* Fetch config space registers address */
281 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
282 printk(KERN_ERR "%s:Can't get PCI config register base !",
286 /* Fetch host bridge internal registers address */
287 if (of_address_to_resource(np, 3, &rsrc_reg)) {
288 printk(KERN_ERR "%s: Can't get PCI internal register base !",
293 /* Check if primary bridge */
294 if (of_get_property(np, "primary", NULL))
297 /* Get bus range if any */
298 bus_range = of_get_property(np, "bus-range", NULL);
301 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
303 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
307 /* Allocate the host controller data structure */
308 hose = pcibios_alloc_controller(np);
312 hose->first_busno = bus_range ? bus_range[0] : 0x0;
313 hose->last_busno = bus_range ? bus_range[1] : 0xff;
315 /* Setup config space */
316 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
318 /* Disable all windows */
319 writel(0, reg + PCIL0_PMM0MA);
320 writel(0, reg + PCIL0_PMM1MA);
321 writel(0, reg + PCIL0_PMM2MA);
322 writel(0, reg + PCIL0_PTM1MS);
323 writel(0, reg + PCIL0_PTM2MS);
325 /* Parse outbound mapping resources */
326 pci_process_bridge_OF_ranges(hose, np, primary);
328 /* Parse inbound mapping resources */
329 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
332 /* Configure outbound ranges POMs */
333 ppc4xx_configure_pci_PMMs(hose, reg);
335 /* Configure inbound ranges PIMs */
336 ppc4xx_configure_pci_PTMs(hose, reg, &dma_window);
338 /* We don't need the registers anymore */
344 pcibios_free_controller(hose);
353 static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
356 u32 lah, lal, pciah, pcial, sa;
359 /* Setup outbound memory windows */
360 for (i = j = 0; i < 3; i++) {
361 struct resource *res = &hose->mem_resources[i];
363 /* we only care about memory windows */
364 if (!(res->flags & IORESOURCE_MEM))
367 printk(KERN_WARNING "%s: Too many ranges\n",
368 hose->dn->full_name);
372 /* Calculate register values */
373 lah = RES_TO_U32_HIGH(res->start);
374 lal = RES_TO_U32_LOW(res->start);
375 pciah = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
376 pcial = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
377 sa = res->end + 1 - res->start;
378 if (!is_power_of_2(sa) || sa < 0x100000 ||
380 printk(KERN_WARNING "%s: Resource out of range\n",
381 hose->dn->full_name);
384 sa = (0xffffffffu << ilog2(sa)) | 0x1;
386 /* Program register values */
388 writel(lah, reg + PCIX0_POM0LAH);
389 writel(lal, reg + PCIX0_POM0LAL);
390 writel(pciah, reg + PCIX0_POM0PCIAH);
391 writel(pcial, reg + PCIX0_POM0PCIAL);
392 writel(sa, reg + PCIX0_POM0SA);
394 writel(lah, reg + PCIX0_POM1LAH);
395 writel(lal, reg + PCIX0_POM1LAL);
396 writel(pciah, reg + PCIX0_POM1PCIAH);
397 writel(pcial, reg + PCIX0_POM1PCIAL);
398 writel(sa, reg + PCIX0_POM1SA);
404 static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose,
406 const struct resource *res,
410 resource_size_t size = res->end - res->start + 1;
413 /* RAM is always at 0 */
414 writel(0x00000000, reg + PCIX0_PIM0LAH);
415 writel(0x00000000, reg + PCIX0_PIM0LAL);
417 /* Calculate window size */
418 sa = (0xffffffffu << ilog2(size)) | 1;
420 if (res->flags & IORESOURCE_PREFETCH)
424 writel(sa, reg + PCIX0_PIM0SA);
426 writel(0xffffffff, reg + PCIX0_PIM0SAH);
428 /* Map on PCI side */
429 writel(0x00000000, reg + PCIX0_BAR0H);
430 writel(res->start, reg + PCIX0_BAR0L);
431 writew(0x0006, reg + PCIX0_COMMAND);
434 static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
436 struct resource rsrc_cfg;
437 struct resource rsrc_reg;
438 struct resource dma_window;
439 struct pci_controller *hose = NULL;
440 void __iomem *reg = NULL;
441 const int *bus_range;
442 int big_pim = 0, msi = 0, primary = 0;
444 /* Fetch config space registers address */
445 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
446 printk(KERN_ERR "%s:Can't get PCI-X config register base !",
450 /* Fetch host bridge internal registers address */
451 if (of_address_to_resource(np, 3, &rsrc_reg)) {
452 printk(KERN_ERR "%s: Can't get PCI-X internal register base !",
457 /* Check if it supports large PIMs (440GX) */
458 if (of_get_property(np, "large-inbound-windows", NULL))
461 /* Check if we should enable MSIs inbound hole */
462 if (of_get_property(np, "enable-msi-hole", NULL))
465 /* Check if primary bridge */
466 if (of_get_property(np, "primary", NULL))
469 /* Get bus range if any */
470 bus_range = of_get_property(np, "bus-range", NULL);
473 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
475 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
479 /* Allocate the host controller data structure */
480 hose = pcibios_alloc_controller(np);
484 hose->first_busno = bus_range ? bus_range[0] : 0x0;
485 hose->last_busno = bus_range ? bus_range[1] : 0xff;
487 /* Setup config space */
488 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
490 /* Disable all windows */
491 writel(0, reg + PCIX0_POM0SA);
492 writel(0, reg + PCIX0_POM1SA);
493 writel(0, reg + PCIX0_POM2SA);
494 writel(0, reg + PCIX0_PIM0SA);
495 writel(0, reg + PCIX0_PIM1SA);
496 writel(0, reg + PCIX0_PIM2SA);
498 writel(0, reg + PCIX0_PIM0SAH);
499 writel(0, reg + PCIX0_PIM2SAH);
502 /* Parse outbound mapping resources */
503 pci_process_bridge_OF_ranges(hose, np, primary);
505 /* Parse inbound mapping resources */
506 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
509 /* Configure outbound ranges POMs */
510 ppc4xx_configure_pcix_POMs(hose, reg);
512 /* Configure inbound ranges PIMs */
513 ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi);
515 /* We don't need the registers anymore */
521 pcibios_free_controller(hose);
526 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
529 * 4xx PCI-Express part
531 * We support 3 parts currently based on the compatible property:
533 * ibm,plb-pciex-440spe
534 * ibm,plb-pciex-405ex
535 * ibm,plb-pciex-460ex
537 * Anything else will be rejected for now as they are all subtly
538 * different unfortunately.
542 #define MAX_PCIE_BUS_MAPPED 0x40
544 struct ppc4xx_pciex_port
546 struct pci_controller *hose;
547 struct device_node *node;
552 unsigned int sdr_base;
554 struct resource cfg_space;
555 struct resource utl_regs;
556 void __iomem *utl_base;
559 static struct ppc4xx_pciex_port *ppc4xx_pciex_ports;
560 static unsigned int ppc4xx_pciex_port_count;
562 struct ppc4xx_pciex_hwops
564 int (*core_init)(struct device_node *np);
565 int (*port_init_hw)(struct ppc4xx_pciex_port *port);
566 int (*setup_utl)(struct ppc4xx_pciex_port *port);
569 static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops;
573 /* Check various reset bits of the 440SPe PCIe core */
574 static int __init ppc440spe_pciex_check_reset(struct device_node *np)
576 u32 valPE0, valPE1, valPE2;
579 /* SDR0_PEGPLLLCT1 reset */
580 if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) {
582 * the PCIe core was probably already initialised
583 * by firmware - let's re-reset RCSSET regs
585 * -- Shouldn't we also re-reset the whole thing ? -- BenH
587 pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n");
588 mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000);
589 mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000);
590 mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000);
593 valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET);
594 valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET);
595 valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET);
597 /* SDR0_PExRCSSET rstgu */
598 if (!(valPE0 & 0x01000000) ||
599 !(valPE1 & 0x01000000) ||
600 !(valPE2 & 0x01000000)) {
601 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
605 /* SDR0_PExRCSSET rstdl */
606 if (!(valPE0 & 0x00010000) ||
607 !(valPE1 & 0x00010000) ||
608 !(valPE2 & 0x00010000)) {
609 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
613 /* SDR0_PExRCSSET rstpyn */
614 if ((valPE0 & 0x00001000) ||
615 (valPE1 & 0x00001000) ||
616 (valPE2 & 0x00001000)) {
617 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
621 /* SDR0_PExRCSSET hldplb */
622 if ((valPE0 & 0x10000000) ||
623 (valPE1 & 0x10000000) ||
624 (valPE2 & 0x10000000)) {
625 printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
629 /* SDR0_PExRCSSET rdy */
630 if ((valPE0 & 0x00100000) ||
631 (valPE1 & 0x00100000) ||
632 (valPE2 & 0x00100000)) {
633 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
637 /* SDR0_PExRCSSET shutdown */
638 if ((valPE0 & 0x00000100) ||
639 (valPE1 & 0x00000100) ||
640 (valPE2 & 0x00000100)) {
641 printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
648 /* Global PCIe core initializations for 440SPe core */
649 static int __init ppc440spe_pciex_core_init(struct device_node *np)
653 /* Set PLL clock receiver to LVPECL */
654 dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
656 /* Shouldn't we do all the calibration stuff etc... here ? */
657 if (ppc440spe_pciex_check_reset(np))
660 if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) {
661 printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration "
663 mfdcri(SDR0, PESDR0_PLLLCT2));
667 /* De-assert reset of PCIe PLL, wait for lock */
668 dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
672 if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) {
679 printk(KERN_INFO "PCIE: VCO output not locked\n");
683 pr_debug("PCIE initialization OK\n");
688 static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
693 val = PTYPE_LEGACY_ENDPOINT << 20;
695 val = PTYPE_ROOT_PORT << 20;
697 if (port->index == 0)
698 val |= LNKW_X8 << 12;
700 val |= LNKW_X4 << 12;
702 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
703 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);
704 if (ppc440spe_revA())
705 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);
706 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);
707 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);
708 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);
709 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);
710 if (port->index == 0) {
711 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,
713 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,
715 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,
717 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
720 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
721 (1 << 24) | (1 << 16), 1 << 12);
726 static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
728 return ppc440spe_pciex_init_port_hw(port);
731 static int ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
733 int rc = ppc440spe_pciex_init_port_hw(port);
740 static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port)
742 /* XXX Check what that value means... I hate magic */
743 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800);
746 * Set buffer allocations and then assert VRB and TXE.
748 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
749 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
750 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000);
751 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000);
752 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000);
753 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000);
754 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
755 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
760 static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port)
762 /* Report CRS to the operating system */
763 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
768 static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
770 .core_init = ppc440spe_pciex_core_init,
771 .port_init_hw = ppc440speA_pciex_init_port_hw,
772 .setup_utl = ppc440speA_pciex_init_utl,
775 static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
777 .core_init = ppc440spe_pciex_core_init,
778 .port_init_hw = ppc440speB_pciex_init_port_hw,
779 .setup_utl = ppc440speB_pciex_init_utl,
782 static int __init ppc460ex_pciex_core_init(struct device_node *np)
784 /* Nothing to do, return 2 ports */
788 static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
794 val = PTYPE_LEGACY_ENDPOINT << 20;
796 val = PTYPE_ROOT_PORT << 20;
798 if (port->index == 0) {
799 val |= LNKW_X1 << 12;
800 utlset1 = 0x20000000;
802 val |= LNKW_X4 << 12;
803 utlset1 = 0x20101101;
806 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
807 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
808 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
810 switch (port->index) {
812 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
813 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000136);
814 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
816 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);
820 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);
821 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
822 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
823 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
824 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000136);
825 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000136);
826 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000136);
827 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000136);
828 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
829 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
830 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);
831 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);
833 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000);
837 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
838 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
839 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
841 /* Poll for PHY reset */
842 /* XXX FIXME add timeout */
843 switch (port->index) {
845 while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1))
849 while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1))
854 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
855 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
856 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
857 PESDRx_RCSSET_RSTPYN);
864 static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
866 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
869 * Set buffer allocations and then assert VRB and TXE.
871 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c);
872 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
873 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
874 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
875 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000);
876 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
877 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
878 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000);
879 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
884 static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
886 .core_init = ppc460ex_pciex_core_init,
887 .port_init_hw = ppc460ex_pciex_init_port_hw,
888 .setup_utl = ppc460ex_pciex_init_utl,
891 #endif /* CONFIG_44x */
895 static int __init ppc405ex_pciex_core_init(struct device_node *np)
897 /* Nothing to do, return 2 ports */
901 static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port)
903 /* Assert the PE0_PHY reset */
904 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);
907 /* deassert the PE0_hotreset */
909 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);
911 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);
913 /* poll for phy !reset */
914 /* XXX FIXME add timeout */
915 while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000))
918 /* deassert the PE0_gpl_utl_reset */
919 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);
922 static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
927 val = PTYPE_LEGACY_ENDPOINT;
929 val = PTYPE_ROOT_PORT;
931 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,
932 1 << 24 | val << 20 | LNKW_X1 << 12);
934 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
935 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
936 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);
937 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);
940 * Only reset the PHY when no link is currently established.
941 * This is for the Atheros PCIe board which has problems to establish
942 * the link (again) after this PHY reset. All other currently tested
943 * PCIe boards don't show this problem.
944 * This has to be re-tested and fixed in a later release!
946 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
947 if (!(val & 0x00001000))
948 ppc405ex_pcie_phy_reset(port);
950 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */
957 static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
959 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
962 * Set buffer allocations and then assert VRB and TXE.
964 out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000);
965 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
966 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
967 out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000);
968 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
969 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
970 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
971 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
973 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
978 static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
980 .core_init = ppc405ex_pciex_core_init,
981 .port_init_hw = ppc405ex_pciex_init_port_hw,
982 .setup_utl = ppc405ex_pciex_init_utl,
985 #endif /* CONFIG_40x */
988 /* Check that the core has been initied and if not, do it */
989 static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
991 static int core_init;
998 if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) {
999 if (ppc440spe_revA())
1000 ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops;
1002 ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
1004 if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
1005 ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
1006 #endif /* CONFIG_44x */
1008 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
1009 ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops;
1011 if (ppc4xx_pciex_hwops == NULL) {
1012 printk(KERN_WARNING "PCIE: unknown host type %s\n",
1017 count = ppc4xx_pciex_hwops->core_init(np);
1019 ppc4xx_pciex_ports =
1020 kzalloc(count * sizeof(struct ppc4xx_pciex_port),
1022 if (ppc4xx_pciex_ports) {
1023 ppc4xx_pciex_port_count = count;
1026 printk(KERN_WARNING "PCIE: failed to allocate ports array\n");
1032 static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port)
1034 /* We map PCI Express configuration based on the reg property */
1035 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH,
1036 RES_TO_U32_HIGH(port->cfg_space.start));
1037 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL,
1038 RES_TO_U32_LOW(port->cfg_space.start));
1040 /* XXX FIXME: Use size from reg property. For now, map 512M */
1041 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001);
1043 /* We map UTL registers based on the reg property */
1044 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH,
1045 RES_TO_U32_HIGH(port->utl_regs.start));
1046 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL,
1047 RES_TO_U32_LOW(port->utl_regs.start));
1049 /* XXX FIXME: Use size from reg property */
1050 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001);
1052 /* Disable all other outbound windows */
1053 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0);
1054 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0);
1055 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0);
1056 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
1059 static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
1060 unsigned int sdr_offset,
1067 while(timeout_ms--) {
1068 val = mfdcri(SDR0, port->sdr_base + sdr_offset);
1069 if ((val & mask) == value) {
1070 pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
1071 port->index, sdr_offset, timeout_ms, val);
1079 static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1084 if (ppc4xx_pciex_hwops->port_init_hw)
1085 rc = ppc4xx_pciex_hwops->port_init_hw(port);
1089 printk(KERN_INFO "PCIE%d: Checking link...\n",
1092 /* Wait for reset to complete */
1093 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
1094 printk(KERN_WARNING "PCIE%d: PGRST failed\n",
1099 /* Check for card presence detect if supported, if not, just wait for
1100 * link unconditionally.
1102 * note that we don't fail if there is no link, we just filter out
1103 * config space accesses. That way, it will be easier to implement
1106 if (!port->has_ibpre ||
1107 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1108 1 << 28, 1 << 28, 100)) {
1110 "PCIE%d: Device detected, waiting for link...\n",
1112 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1113 0x1000, 0x1000, 2000))
1115 "PCIE%d: Link up failed\n", port->index);
1118 "PCIE%d: link is up !\n", port->index);
1122 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
1125 * Initialize mapping: disable all regions and configure
1126 * CFG and REG regions based on resources in the device tree
1128 ppc4xx_pciex_port_init_mapping(port);
1133 port->utl_base = ioremap(port->utl_regs.start, 0x100);
1134 BUG_ON(port->utl_base == NULL);
1137 * Setup UTL registers --BenH.
1139 if (ppc4xx_pciex_hwops->setup_utl)
1140 ppc4xx_pciex_hwops->setup_utl(port);
1143 * Check for VC0 active and assert RDY.
1146 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
1147 1 << 16, 1 << 16, 5000)) {
1148 printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index);
1152 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
1158 static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port,
1159 struct pci_bus *bus,
1164 /* Endpoint can not generate upstream(remote) config cycles */
1165 if (port->endpoint && bus->number != port->hose->first_busno)
1166 return PCIBIOS_DEVICE_NOT_FOUND;
1168 /* Check we are within the mapped range */
1169 if (bus->number > port->hose->last_busno) {
1171 printk(KERN_WARNING "Warning! Probing bus %u"
1172 " out of range !\n", bus->number);
1175 return PCIBIOS_DEVICE_NOT_FOUND;
1178 /* The root complex has only one device / function */
1179 if (bus->number == port->hose->first_busno && devfn != 0)
1180 return PCIBIOS_DEVICE_NOT_FOUND;
1182 /* The other side of the RC has only one device as well */
1183 if (bus->number == (port->hose->first_busno + 1) &&
1184 PCI_SLOT(devfn) != 0)
1185 return PCIBIOS_DEVICE_NOT_FOUND;
1187 /* Check if we have a link */
1188 if ((bus->number != port->hose->first_busno) && !port->link)
1189 return PCIBIOS_DEVICE_NOT_FOUND;
1194 static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port,
1195 struct pci_bus *bus,
1200 /* Remove the casts when we finally remove the stupid volatile
1201 * in struct pci_controller
1203 if (bus->number == port->hose->first_busno)
1204 return (void __iomem *)port->hose->cfg_addr;
1206 relbus = bus->number - (port->hose->first_busno + 1);
1207 return (void __iomem *)port->hose->cfg_data +
1208 ((relbus << 20) | (devfn << 12));
1211 static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
1212 int offset, int len, u32 *val)
1214 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1215 struct ppc4xx_pciex_port *port =
1216 &ppc4xx_pciex_ports[hose->indirect_type];
1220 BUG_ON(hose != port->hose);
1222 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1223 return PCIBIOS_DEVICE_NOT_FOUND;
1225 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1228 * Reading from configuration space of non-existing device can
1229 * generate transaction errors. For the read duration we suppress
1230 * assertion of machine check exceptions to avoid those.
1232 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1233 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1235 /* Make sure no CRS is recorded */
1236 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000);
1240 *val = in_8((u8 *)(addr + offset));
1243 *val = in_le16((u16 *)(addr + offset));
1246 *val = in_le32((u32 *)(addr + offset));
1250 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x"
1251 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1252 bus->number, hose->first_busno, hose->last_busno,
1253 devfn, offset, len, addr + offset, *val);
1255 /* Check for CRS (440SPe rev B does that for us but heh ..) */
1256 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) {
1257 pr_debug("Got CRS !\n");
1258 if (len != 4 || offset != 0)
1259 return PCIBIOS_DEVICE_NOT_FOUND;
1263 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1265 return PCIBIOS_SUCCESSFUL;
1268 static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
1269 int offset, int len, u32 val)
1271 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1272 struct ppc4xx_pciex_port *port =
1273 &ppc4xx_pciex_ports[hose->indirect_type];
1277 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1278 return PCIBIOS_DEVICE_NOT_FOUND;
1280 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1283 * Reading from configuration space of non-existing device can
1284 * generate transaction errors. For the read duration we suppress
1285 * assertion of machine check exceptions to avoid those.
1287 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1288 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1290 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x"
1291 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1292 bus->number, hose->first_busno, hose->last_busno,
1293 devfn, offset, len, addr + offset, val);
1297 out_8((u8 *)(addr + offset), val);
1300 out_le16((u16 *)(addr + offset), val);
1303 out_le32((u32 *)(addr + offset), val);
1307 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1309 return PCIBIOS_SUCCESSFUL;
1312 static struct pci_ops ppc4xx_pciex_pci_ops =
1314 .read = ppc4xx_pciex_read_config,
1315 .write = ppc4xx_pciex_write_config,
1318 static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
1319 struct pci_controller *hose,
1320 void __iomem *mbase)
1322 u32 lah, lal, pciah, pcial, sa;
1325 /* Setup outbound memory windows */
1326 for (i = j = 0; i < 3; i++) {
1327 struct resource *res = &hose->mem_resources[i];
1329 /* we only care about memory windows */
1330 if (!(res->flags & IORESOURCE_MEM))
1333 printk(KERN_WARNING "%s: Too many ranges\n",
1334 port->node->full_name);
1338 /* Calculate register values */
1339 lah = RES_TO_U32_HIGH(res->start);
1340 lal = RES_TO_U32_LOW(res->start);
1341 pciah = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
1342 pcial = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
1343 sa = res->end + 1 - res->start;
1344 if (!is_power_of_2(sa) || sa < 0x100000 ||
1346 printk(KERN_WARNING "%s: Resource out of range\n",
1347 port->node->full_name);
1350 sa = (0xffffffffu << ilog2(sa)) | 0x1;
1352 /* Program register values */
1355 out_le32(mbase + PECFG_POM0LAH, pciah);
1356 out_le32(mbase + PECFG_POM0LAL, pcial);
1357 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);
1358 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);
1359 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);
1360 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, sa | 3);
1363 out_le32(mbase + PECFG_POM1LAH, pciah);
1364 out_le32(mbase + PECFG_POM1LAL, pcial);
1365 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);
1366 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);
1367 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);
1368 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, sa | 3);
1374 /* Configure IO, always 64K starting at 0 */
1375 if (hose->io_resource.flags & IORESOURCE_IO) {
1376 lah = RES_TO_U32_HIGH(hose->io_base_phys);
1377 lal = RES_TO_U32_LOW(hose->io_base_phys);
1378 out_le32(mbase + PECFG_POM2LAH, 0);
1379 out_le32(mbase + PECFG_POM2LAL, 0);
1380 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah);
1381 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);
1382 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);
1383 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0xffff0000 | 3);
1387 static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
1388 struct pci_controller *hose,
1389 void __iomem *mbase,
1390 struct resource *res)
1392 resource_size_t size = res->end - res->start + 1;
1395 if (port->endpoint) {
1396 resource_size_t ep_addr = 0;
1397 resource_size_t ep_size = 32 << 20;
1399 /* Currently we map a fixed 64MByte window to PLB address
1400 * 0 (SDRAM). This should probably be configurable via a dts
1404 /* Calculate window size */
1405 sa = (0xffffffffffffffffull << ilog2(ep_size));;
1408 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1409 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) |
1410 PCI_BASE_ADDRESS_MEM_TYPE_64);
1412 /* Disable BAR1 & BAR2 */
1413 out_le32(mbase + PECFG_BAR1MPA, 0);
1414 out_le32(mbase + PECFG_BAR2HMPA, 0);
1415 out_le32(mbase + PECFG_BAR2LMPA, 0);
1417 out_le32(mbase + PECFG_PIM01SAH, RES_TO_U32_HIGH(sa));
1418 out_le32(mbase + PECFG_PIM01SAL, RES_TO_U32_LOW(sa));
1420 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr));
1421 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(ep_addr));
1423 /* Calculate window size */
1424 sa = (0xffffffffffffffffull << ilog2(size));;
1425 if (res->flags & IORESOURCE_PREFETCH)
1428 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1429 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa));
1431 /* The setup of the split looks weird to me ... let's see
1434 out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
1435 out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
1436 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
1437 out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
1438 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
1439 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
1441 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start));
1442 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start));
1445 /* Enable inbound mapping */
1446 out_le32(mbase + PECFG_PIMEN, 0x1);
1448 /* Enable I/O, Mem, and Busmaster cycles */
1449 out_le16(mbase + PCI_COMMAND,
1450 in_le16(mbase + PCI_COMMAND) |
1451 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1454 static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port)
1456 struct resource dma_window;
1457 struct pci_controller *hose = NULL;
1458 const int *bus_range;
1459 int primary = 0, busses;
1460 void __iomem *mbase = NULL, *cfg_data = NULL;
1464 /* Check if primary bridge */
1465 if (of_get_property(port->node, "primary", NULL))
1468 /* Get bus range if any */
1469 bus_range = of_get_property(port->node, "bus-range", NULL);
1471 /* Allocate the host controller data structure */
1472 hose = pcibios_alloc_controller(port->node);
1476 /* We stick the port number in "indirect_type" so the config space
1477 * ops can retrieve the port data structure easily
1479 hose->indirect_type = port->index;
1482 hose->first_busno = bus_range ? bus_range[0] : 0x0;
1483 hose->last_busno = bus_range ? bus_range[1] : 0xff;
1485 /* Because of how big mapping the config space is (1M per bus), we
1486 * limit how many busses we support. In the long run, we could replace
1487 * that with something akin to kmap_atomic instead. We set aside 1 bus
1488 * for the host itself too.
1490 busses = hose->last_busno - hose->first_busno; /* This is off by 1 */
1491 if (busses > MAX_PCIE_BUS_MAPPED) {
1492 busses = MAX_PCIE_BUS_MAPPED;
1493 hose->last_busno = hose->first_busno + busses;
1496 if (!port->endpoint) {
1497 /* Only map the external config space in cfg_data for
1498 * PCIe root-complexes. External space is 1M per bus
1500 cfg_data = ioremap(port->cfg_space.start +
1501 (hose->first_busno + 1) * 0x100000,
1503 if (cfg_data == NULL) {
1504 printk(KERN_ERR "%s: Can't map external config space !",
1505 port->node->full_name);
1508 hose->cfg_data = cfg_data;
1511 /* Always map the host config space in cfg_addr.
1512 * Internal space is 4K
1514 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
1515 if (mbase == NULL) {
1516 printk(KERN_ERR "%s: Can't map internal config space !",
1517 port->node->full_name);
1520 hose->cfg_addr = mbase;
1522 pr_debug("PCIE %s, bus %d..%d\n", port->node->full_name,
1523 hose->first_busno, hose->last_busno);
1524 pr_debug(" config space mapped at: root @0x%p, other @0x%p\n",
1525 hose->cfg_addr, hose->cfg_data);
1527 /* Setup config space */
1528 hose->ops = &ppc4xx_pciex_pci_ops;
1530 mbase = (void __iomem *)hose->cfg_addr;
1532 if (!port->endpoint) {
1534 * Set bus numbers on our root port
1536 out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno);
1537 out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1);
1538 out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno);
1542 * OMRs are already reset, also disable PIMs
1544 out_le32(mbase + PECFG_PIMEN, 0);
1546 /* Parse outbound mapping resources */
1547 pci_process_bridge_OF_ranges(hose, port->node, primary);
1549 /* Parse inbound mapping resources */
1550 if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0)
1553 /* Configure outbound ranges POMs */
1554 ppc4xx_configure_pciex_POMs(port, hose, mbase);
1556 /* Configure inbound ranges PIMs */
1557 ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window);
1559 /* The root complex doesn't show up if we don't set some vendor
1560 * and device IDs into it. The defaults below are the same bogus
1561 * one that the initial code in arch/ppc had. This can be
1562 * overwritten by setting the "vendor-id/device-id" properties
1563 * in the pciex node.
1566 /* Get the (optional) vendor-/device-id from the device-tree */
1567 pval = of_get_property(port->node, "vendor-id", NULL);
1571 if (!port->endpoint)
1572 val = 0xaaa0 + port->index;
1574 val = 0xeee0 + port->index;
1576 out_le16(mbase + 0x200, val);
1578 pval = of_get_property(port->node, "device-id", NULL);
1582 if (!port->endpoint)
1583 val = 0xbed0 + port->index;
1585 val = 0xfed0 + port->index;
1587 out_le16(mbase + 0x202, val);
1589 if (!port->endpoint) {
1590 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
1591 out_le32(mbase + 0x208, 0x06040001);
1593 printk(KERN_INFO "PCIE%d: successfully set as root-complex\n",
1596 /* Set Class Code to Processor/PPC */
1597 out_le32(mbase + 0x208, 0x0b200001);
1599 printk(KERN_INFO "PCIE%d: successfully set as endpoint\n",
1606 pcibios_free_controller(hose);
1613 static void __init ppc4xx_probe_pciex_bridge(struct device_node *np)
1615 struct ppc4xx_pciex_port *port;
1621 /* First, proceed to core initialization as we assume there's
1622 * only one PCIe core in the system
1624 if (ppc4xx_pciex_check_core_init(np))
1627 /* Get the port number from the device-tree */
1628 pval = of_get_property(np, "port", NULL);
1630 printk(KERN_ERR "PCIE: Can't find port number for %s\n",
1635 if (portno >= ppc4xx_pciex_port_count) {
1636 printk(KERN_ERR "PCIE: port number out of range for %s\n",
1640 port = &ppc4xx_pciex_ports[portno];
1641 port->index = portno;
1644 * Check if device is enabled
1646 if (!of_device_is_available(np)) {
1647 printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index);
1651 port->node = of_node_get(np);
1652 pval = of_get_property(np, "sdr-base", NULL);
1654 printk(KERN_ERR "PCIE: missing sdr-base for %s\n",
1658 port->sdr_base = *pval;
1660 /* Check if device_type property is set to "pci" or "pci-endpoint".
1661 * Resulting from this setup this PCIe port will be configured
1662 * as root-complex or as endpoint.
1664 val = of_get_property(port->node, "device_type", NULL);
1665 if (!strcmp(val, "pci-endpoint")) {
1667 } else if (!strcmp(val, "pci")) {
1670 printk(KERN_ERR "PCIE: missing or incorrect device_type for %s\n",
1675 /* Fetch config space registers address */
1676 if (of_address_to_resource(np, 0, &port->cfg_space)) {
1677 printk(KERN_ERR "%s: Can't get PCI-E config space !",
1681 /* Fetch host bridge internal registers address */
1682 if (of_address_to_resource(np, 1, &port->utl_regs)) {
1683 printk(KERN_ERR "%s: Can't get UTL register base !",
1689 dcrs = dcr_resource_start(np, 0);
1691 printk(KERN_ERR "%s: Can't get DCR register base !",
1695 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
1697 /* Initialize the port specific registers */
1698 if (ppc4xx_pciex_port_init(port)) {
1699 printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index);
1703 /* Setup the linux hose data structure */
1704 ppc4xx_pciex_port_setup_hose(port);
1707 #endif /* CONFIG_PPC4xx_PCI_EXPRESS */
1709 static int __init ppc4xx_pci_find_bridges(void)
1711 struct device_node *np;
1713 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
1714 for_each_compatible_node(np, NULL, "ibm,plb-pciex")
1715 ppc4xx_probe_pciex_bridge(np);
1717 for_each_compatible_node(np, NULL, "ibm,plb-pcix")
1718 ppc4xx_probe_pcix_bridge(np);
1719 for_each_compatible_node(np, NULL, "ibm,plb-pci")
1720 ppc4xx_probe_pci_bridge(np);
1724 arch_initcall(ppc4xx_pci_find_bridges);