git.oblomov.eu Git - linux-2.6/blob - drivers/infiniband/hw/ipath/ipath_ht400.c

   1 /*
   2  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 /*
  34  * This file contains all of the code that is specific to the InfiniPath
  35  * HT-400 chip.
  36  */
  37
  38 #include <linux/pci.h>
  39 #include <linux/delay.h>
  40
  41 #include "ipath_kernel.h"
  42 #include "ipath_registers.h"
  43
  44 /*
  45  * This lists the InfiniPath HT400 registers, in the actual chip layout.
  46  * This structure should never be directly accessed.
  47  *
  48  * The names are in InterCap form because they're taken straight from
  49  * the chip specification.  Since they're only used in this file, they
  50  * don't pollute the rest of the source.
  51 */
  52
  53 struct _infinipath_do_not_use_kernel_regs {
  54         unsigned long long Revision;
  55         unsigned long long Control;
  56         unsigned long long PageAlign;
  57         unsigned long long PortCnt;
  58         unsigned long long DebugPortSelect;
  59         unsigned long long DebugPort;
  60         unsigned long long SendRegBase;
  61         unsigned long long UserRegBase;
  62         unsigned long long CounterRegBase;
  63         unsigned long long Scratch;
  64         unsigned long long ReservedMisc1;
  65         unsigned long long InterruptConfig;
  66         unsigned long long IntBlocked;
  67         unsigned long long IntMask;
  68         unsigned long long IntStatus;
  69         unsigned long long IntClear;
  70         unsigned long long ErrorMask;
  71         unsigned long long ErrorStatus;
  72         unsigned long long ErrorClear;
  73         unsigned long long HwErrMask;
  74         unsigned long long HwErrStatus;
  75         unsigned long long HwErrClear;
  76         unsigned long long HwDiagCtrl;
  77         unsigned long long MDIO;
  78         unsigned long long IBCStatus;
  79         unsigned long long IBCCtrl;
  80         unsigned long long ExtStatus;
  81         unsigned long long ExtCtrl;
  82         unsigned long long GPIOOut;
  83         unsigned long long GPIOMask;
  84         unsigned long long GPIOStatus;
  85         unsigned long long GPIOClear;
  86         unsigned long long RcvCtrl;
  87         unsigned long long RcvBTHQP;
  88         unsigned long long RcvHdrSize;
  89         unsigned long long RcvHdrCnt;
  90         unsigned long long RcvHdrEntSize;
  91         unsigned long long RcvTIDBase;
  92         unsigned long long RcvTIDCnt;
  93         unsigned long long RcvEgrBase;
  94         unsigned long long RcvEgrCnt;
  95         unsigned long long RcvBufBase;
  96         unsigned long long RcvBufSize;
  97         unsigned long long RxIntMemBase;
  98         unsigned long long RxIntMemSize;
  99         unsigned long long RcvPartitionKey;
 100         unsigned long long ReservedRcv[10];
 101         unsigned long long SendCtrl;
 102         unsigned long long SendPIOBufBase;
 103         unsigned long long SendPIOSize;
 104         unsigned long long SendPIOBufCnt;
 105         unsigned long long SendPIOAvailAddr;
 106         unsigned long long TxIntMemBase;
 107         unsigned long long TxIntMemSize;
 108         unsigned long long ReservedSend[9];
 109         unsigned long long SendBufferError;
 110         unsigned long long SendBufferErrorCONT1;
 111         unsigned long long SendBufferErrorCONT2;
 112         unsigned long long SendBufferErrorCONT3;
 113         unsigned long long ReservedSBE[4];
 114         unsigned long long RcvHdrAddr0;
 115         unsigned long long RcvHdrAddr1;
 116         unsigned long long RcvHdrAddr2;
 117         unsigned long long RcvHdrAddr3;
 118         unsigned long long RcvHdrAddr4;
 119         unsigned long long RcvHdrAddr5;
 120         unsigned long long RcvHdrAddr6;
 121         unsigned long long RcvHdrAddr7;
 122         unsigned long long RcvHdrAddr8;
 123         unsigned long long ReservedRHA[7];
 124         unsigned long long RcvHdrTailAddr0;
 125         unsigned long long RcvHdrTailAddr1;
 126         unsigned long long RcvHdrTailAddr2;
 127         unsigned long long RcvHdrTailAddr3;
 128         unsigned long long RcvHdrTailAddr4;
 129         unsigned long long RcvHdrTailAddr5;
 130         unsigned long long RcvHdrTailAddr6;
 131         unsigned long long RcvHdrTailAddr7;
 132         unsigned long long RcvHdrTailAddr8;
 133         unsigned long long ReservedRHTA[7];
 134         unsigned long long Sync;        /* Software only */
 135         unsigned long long Dump;        /* Software only */
 136         unsigned long long SimVer;      /* Software only */
 137         unsigned long long ReservedSW[5];
 138         unsigned long long SerdesConfig0;
 139         unsigned long long SerdesConfig1;
 140         unsigned long long SerdesStatus;
 141         unsigned long long XGXSConfig;
 142         unsigned long long ReservedSW2[4];
 143 };
 144
 145 #define IPATH_KREG_OFFSET(field) (offsetof(struct \
 146     _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
 147 #define IPATH_CREG_OFFSET(field) (offsetof( \
 148     struct infinipath_counters, field) / sizeof(u64))
 149
 150 static const struct ipath_kregs ipath_ht_kregs = {
 151         .kr_control = IPATH_KREG_OFFSET(Control),
 152         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
 153         .kr_debugport = IPATH_KREG_OFFSET(DebugPort),
 154         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
 155         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
 156         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
 157         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
 158         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
 159         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
 160         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
 161         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
 162         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
 163         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
 164         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
 165         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
 166         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
 167         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
 168         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
 169         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
 170         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
 171         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
 172         .kr_interruptconfig = IPATH_KREG_OFFSET(InterruptConfig),
 173         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
 174         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
 175         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
 176         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
 177         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
 178         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
 179         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
 180         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
 181         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
 182         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
 183         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
 184         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
 185         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
 186         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
 187         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
 188         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
 189         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
 190         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
 191         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
 192         .kr_revision = IPATH_KREG_OFFSET(Revision),
 193         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
 194         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
 195         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
 196         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
 197         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
 198         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
 199         .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
 200         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
 201         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
 202         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
 203         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
 204         .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
 205         .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
 206         .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
 207         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
 208         /*
 209          * These should not be used directly via ipath_read_kreg64(),
 210          * use them with ipath_read_kreg64_port(),
 211          */
 212         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
 213         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0)
 214 };
 215
 216 static const struct ipath_cregs ipath_ht_cregs = {
 217         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
 218         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
 219         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
 220         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
 221         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
 222         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
 223         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
 224         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
 225         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
 226         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
 227         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
 228         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
 229         /* calc from Reg_CounterRegBase + offset */
 230         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
 231         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
 232         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
 233         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
 234         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
 235         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
 236         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
 237         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
 238         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
 239         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
 240         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
 241         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
 242         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
 243         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
 244         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
 245         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
 246         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
 247         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
 248         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
 249         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
 250         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
 251 };
 252
 253 /* kr_intstatus, kr_intclear, kr_intmask bits */
 254 #define INFINIPATH_I_RCVURG_MASK 0x1FF
 255 #define INFINIPATH_I_RCVAVAIL_MASK 0x1FF
 256
 257 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
 258 #define INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT 0
 259 #define INFINIPATH_HWE_HTCMEMPARITYERR_MASK 0x3FFFFFULL
 260 #define INFINIPATH_HWE_HTCLNKABYTE0CRCERR   0x0000000000800000ULL
 261 #define INFINIPATH_HWE_HTCLNKABYTE1CRCERR   0x0000000001000000ULL
 262 #define INFINIPATH_HWE_HTCLNKBBYTE0CRCERR   0x0000000002000000ULL
 263 #define INFINIPATH_HWE_HTCLNKBBYTE1CRCERR   0x0000000004000000ULL
 264 #define INFINIPATH_HWE_HTCMISCERR4          0x0000000008000000ULL
 265 #define INFINIPATH_HWE_HTCMISCERR5          0x0000000010000000ULL
 266 #define INFINIPATH_HWE_HTCMISCERR6          0x0000000020000000ULL
 267 #define INFINIPATH_HWE_HTCMISCERR7          0x0000000040000000ULL
 268 #define INFINIPATH_HWE_HTCBUSTREQPARITYERR  0x0000000080000000ULL
 269 #define INFINIPATH_HWE_HTCBUSTRESPPARITYERR 0x0000000100000000ULL
 270 #define INFINIPATH_HWE_HTCBUSIREQPARITYERR  0x0000000200000000ULL
 271 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
 272 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
 273 #define INFINIPATH_HWE_HTBPLL_FBSLIP        0x0200000000000000ULL
 274 #define INFINIPATH_HWE_HTBPLL_RFSLIP        0x0400000000000000ULL
 275 #define INFINIPATH_HWE_HTAPLL_FBSLIP        0x0800000000000000ULL
 276 #define INFINIPATH_HWE_HTAPLL_RFSLIP        0x1000000000000000ULL
 277 #define INFINIPATH_HWE_SERDESPLLFAILED      0x2000000000000000ULL
 278
 279 /* kr_extstatus bits */
 280 #define INFINIPATH_EXTS_FREQSEL 0x2
 281 #define INFINIPATH_EXTS_SERDESSEL 0x4
 282 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
 283 #define INFINIPATH_EXTS_MEMBIST_CORRECT     0x0000000000008000
 284
 285 /*
 286  * masks and bits that are different in different chips, or present only
 287  * in one
 288  */
 289 static const ipath_err_t infinipath_hwe_htcmemparityerr_mask =
 290     INFINIPATH_HWE_HTCMEMPARITYERR_MASK;
 291 static const ipath_err_t infinipath_hwe_htcmemparityerr_shift =
 292     INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT;
 293
 294 static const ipath_err_t infinipath_hwe_htclnkabyte0crcerr =
 295     INFINIPATH_HWE_HTCLNKABYTE0CRCERR;
 296 static const ipath_err_t infinipath_hwe_htclnkabyte1crcerr =
 297     INFINIPATH_HWE_HTCLNKABYTE1CRCERR;
 298 static const ipath_err_t infinipath_hwe_htclnkbbyte0crcerr =
 299     INFINIPATH_HWE_HTCLNKBBYTE0CRCERR;
 300 static const ipath_err_t infinipath_hwe_htclnkbbyte1crcerr =
 301     INFINIPATH_HWE_HTCLNKBBYTE1CRCERR;
 302
 303 #define _IPATH_GPIO_SDA_NUM 1
 304 #define _IPATH_GPIO_SCL_NUM 0
 305
 306 #define IPATH_GPIO_SDA \
 307         (1ULL << (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 308 #define IPATH_GPIO_SCL \
 309         (1ULL << (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 310
 311 /* keep the code below somewhat more readonable; not used elsewhere */
 312 #define _IPATH_HTLINK0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
 313                                 infinipath_hwe_htclnkabyte1crcerr)
 314 #define _IPATH_HTLINK1_CRCBITS (infinipath_hwe_htclnkbbyte0crcerr |     \
 315                                 infinipath_hwe_htclnkbbyte1crcerr)
 316 #define _IPATH_HTLANE0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
 317                                 infinipath_hwe_htclnkbbyte0crcerr)
 318 #define _IPATH_HTLANE1_CRCBITS (infinipath_hwe_htclnkabyte1crcerr |     \
 319                                 infinipath_hwe_htclnkbbyte1crcerr)
 320
 321 static void hwerr_crcbits(struct ipath_devdata *dd, ipath_err_t hwerrs,
 322                           char *msg, size_t msgl)
 323 {
 324         char bitsmsg[64];
 325         ipath_err_t crcbits = hwerrs &
 326                 (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS);
 327         /* don't check if 8bit HT */
 328         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
 329                 crcbits &= ~infinipath_hwe_htclnkabyte1crcerr;
 330         /* don't check if 8bit HT */
 331         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
 332                 crcbits &= ~infinipath_hwe_htclnkbbyte1crcerr;
 333         /*
 334          * we'll want to ignore link errors on link that is
 335          * not in use, if any.  For now, complain about both
 336          */
 337         if (crcbits) {
 338                 u16 ctrl0, ctrl1;
 339                 snprintf(bitsmsg, sizeof bitsmsg,
 340                          "[HT%s lane %s CRC (%llx); ignore till reload]",
 341                          !(crcbits & _IPATH_HTLINK1_CRCBITS) ?
 342                          "0 (A)" : (!(crcbits & _IPATH_HTLINK0_CRCBITS)
 343                                     ? "1 (B)" : "0+1 (A+B)"),
 344                          !(crcbits & _IPATH_HTLANE1_CRCBITS) ? "0"
 345                          : (!(crcbits & _IPATH_HTLANE0_CRCBITS) ? "1" :
 346                             "0+1"), (unsigned long long) crcbits);
 347                 strlcat(msg, bitsmsg, msgl);
 348
 349                 /*
 350                  * print extra info for debugging.  slave/primary
 351                  * config word 4, 8 (link control 0, 1)
 352                  */
 353
 354                 if (pci_read_config_word(dd->pcidev,
 355                                          dd->ipath_ht_slave_off + 0x4,
 356                                          &ctrl0))
 357                         dev_info(&dd->pcidev->dev, "Couldn't read "
 358                                  "linkctrl0 of slave/primary "
 359                                  "config block\n");
 360                 else if (!(ctrl0 & 1 << 6))
 361                         /* not if EOC bit set */
 362                         ipath_dbg("HT linkctrl0 0x%x%s%s\n", ctrl0,
 363                                   ((ctrl0 >> 8) & 7) ? " CRC" : "",
 364                                   ((ctrl0 >> 4) & 1) ? "linkfail" :
 365                                   "");
 366                 if (pci_read_config_word(dd->pcidev,
 367                                          dd->ipath_ht_slave_off + 0x8,
 368                                          &ctrl1))
 369                         dev_info(&dd->pcidev->dev, "Couldn't read "
 370                                  "linkctrl1 of slave/primary "
 371                                  "config block\n");
 372                 else if (!(ctrl1 & 1 << 6))
 373                         /* not if EOC bit set */
 374                         ipath_dbg("HT linkctrl1 0x%x%s%s\n", ctrl1,
 375                                   ((ctrl1 >> 8) & 7) ? " CRC" : "",
 376                                   ((ctrl1 >> 4) & 1) ? "linkfail" :
 377                                   "");
 378
 379                 /* disable until driver reloaded */
 380                 dd->ipath_hwerrmask &= ~crcbits;
 381                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 382                                  dd->ipath_hwerrmask);
 383                 ipath_dbg("HT crc errs: %s\n", msg);
 384         } else
 385                 ipath_dbg("ignoring HT crc errors 0x%llx, "
 386                           "not in use\n", (unsigned long long)
 387                           (hwerrs & (_IPATH_HTLINK0_CRCBITS |
 388                                      _IPATH_HTLINK1_CRCBITS)));
 389 }
 390
 391 /**
 392  * ipath_ht_handle_hwerrors - display hardware errors
 393  * @dd: the infinipath device
 394  * @msg: the output buffer
 395  * @msgl: the size of the output buffer
 396  *
 397  * Use same msg buffer as regular errors to avoid
 398  * excessive stack use.  Most hardware errors are catastrophic, but for
 399  * right now, we'll print them and continue.
 400  * We reuse the same message buffer as ipath_handle_errors() to avoid
 401  * excessive stack usage.
 402  */
 403 static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg,
 404                                      size_t msgl)
 405 {
 406         ipath_err_t hwerrs;
 407         u32 bits, ctrl;
 408         int isfatal = 0;
 409         char bitsmsg[64];
 410
 411         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
 412
 413         if (!hwerrs) {
 414                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
 415                 /*
 416                  * better than printing cofusing messages
 417                  * This seems to be related to clearing the crc error, or
 418                  * the pll error during init.
 419                  */
 420                 goto bail;
 421         } else if (hwerrs == -1LL) {
 422                 ipath_dev_err(dd, "Read of hardware error status failed "
 423                               "(all bits set); ignoring\n");
 424                 goto bail;
 425         }
 426         ipath_stats.sps_hwerrs++;
 427
 428         /* Always clear the error status register, except MEMBISTFAIL,
 429          * regardless of whether we continue or stop using the chip.
 430          * We want that set so we know it failed, even across driver reload.
 431          * We'll still ignore it in the hwerrmask.  We do this partly for
 432          * diagnostics, but also for support */
 433         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 434                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
 435
 436         hwerrs &= dd->ipath_hwerrmask;
 437
 438         /*
 439          * make sure we get this much out, unless told to be quiet,
 440          * or it's occurred within the last 5 seconds
 441          */
 442         if ((hwerrs & ~dd->ipath_lasthwerror) ||
 443             (ipath_debug & __IPATH_VERBDBG))
 444                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
 445                          "(cleared)\n", (unsigned long long) hwerrs);
 446         dd->ipath_lasthwerror |= hwerrs;
 447
 448         if (hwerrs & ~infinipath_hwe_bitsextant)
 449                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
 450                               "%llx set\n", (unsigned long long)
 451                               (hwerrs & ~infinipath_hwe_bitsextant));
 452
 453         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
 454         if (ctrl & INFINIPATH_C_FREEZEMODE) {
 455                 if (hwerrs) {
 456                         /*
 457                          * if any set that we aren't ignoring; only
 458                          * make the complaint once, in case it's stuck
 459                          * or recurring, and we get here multiple
 460                          * times.
 461                          */
 462                         if (dd->ipath_flags & IPATH_INITTED) {
 463                                 ipath_dev_err(dd, "Fatal Error (freeze "
 464                                               "mode), no longer usable\n");
 465                                 isfatal = 1;
 466                         }
 467                         *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
 468                         /* mark as having had error */
 469                         *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 470                         /*
 471                          * mark as not usable, at a minimum until driver
 472                          * is reloaded, probably until reboot, since no
 473                          * other reset is possible.
 474                          */
 475                         dd->ipath_flags &= ~IPATH_INITTED;
 476                 } else {
 477                         ipath_dbg("Clearing freezemode on ignored hardware "
 478                                   "error\n");
 479                         ctrl &= ~INFINIPATH_C_FREEZEMODE;
 480                         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 481                                          ctrl);
 482                 }
 483         }
 484
 485         *msg = '\0';
 486
 487         /*
 488          * may someday want to decode into which bits are which
 489          * functional area for parity errors, etc.
 490          */
 491         if (hwerrs & (infinipath_hwe_htcmemparityerr_mask
 492                       << INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT)) {
 493                 bits = (u32) ((hwerrs >>
 494                                INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) &
 495                               INFINIPATH_HWE_HTCMEMPARITYERR_MASK);
 496                 snprintf(bitsmsg, sizeof bitsmsg, "[HTC Parity Errs %x] ",
 497                          bits);
 498                 strlcat(msg, bitsmsg, msgl);
 499         }
 500         if (hwerrs & (INFINIPATH_HWE_RXEMEMPARITYERR_MASK
 501                       << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)) {
 502                 bits = (u32) ((hwerrs >>
 503                                INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) &
 504                               INFINIPATH_HWE_RXEMEMPARITYERR_MASK);
 505                 snprintf(bitsmsg, sizeof bitsmsg, "[RXE Parity Errs %x] ",
 506                          bits);
 507                 strlcat(msg, bitsmsg, msgl);
 508         }
 509         if (hwerrs & (INFINIPATH_HWE_TXEMEMPARITYERR_MASK
 510                       << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)) {
 511                 bits = (u32) ((hwerrs >>
 512                                INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) &
 513                               INFINIPATH_HWE_TXEMEMPARITYERR_MASK);
 514                 snprintf(bitsmsg, sizeof bitsmsg, "[TXE Parity Errs %x] ",
 515                          bits);
 516                 strlcat(msg, bitsmsg, msgl);
 517         }
 518         if (hwerrs & INFINIPATH_HWE_IBCBUSTOSPCPARITYERR)
 519                 strlcat(msg, "[IB2IPATH Parity]", msgl);
 520         if (hwerrs & INFINIPATH_HWE_IBCBUSFRSPCPARITYERR)
 521                 strlcat(msg, "[IPATH2IB Parity]", msgl);
 522         if (hwerrs & INFINIPATH_HWE_HTCBUSIREQPARITYERR)
 523                 strlcat(msg, "[HTC Ireq Parity]", msgl);
 524         if (hwerrs & INFINIPATH_HWE_HTCBUSTREQPARITYERR)
 525                 strlcat(msg, "[HTC Treq Parity]", msgl);
 526         if (hwerrs & INFINIPATH_HWE_HTCBUSTRESPPARITYERR)
 527                 strlcat(msg, "[HTC Tresp Parity]", msgl);
 528
 529         if (hwerrs & (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS))
 530                 hwerr_crcbits(dd, hwerrs, msg, msgl);
 531
 532         if (hwerrs & INFINIPATH_HWE_HTCMISCERR5)
 533                 strlcat(msg, "[HT core Misc5]", msgl);
 534         if (hwerrs & INFINIPATH_HWE_HTCMISCERR6)
 535                 strlcat(msg, "[HT core Misc6]", msgl);
 536         if (hwerrs & INFINIPATH_HWE_HTCMISCERR7)
 537                 strlcat(msg, "[HT core Misc7]", msgl);
 538         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
 539                 strlcat(msg, "[Memory BIST test failed, HT-400 unusable]",
 540                         msgl);
 541                 /* ignore from now on, so disable until driver reloaded */
 542                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
 543                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 544                                  dd->ipath_hwerrmask);
 545         }
 546 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
 547                          INFINIPATH_HWE_COREPLL_RFSLIP |        \
 548                          INFINIPATH_HWE_HTBPLL_FBSLIP |         \
 549                          INFINIPATH_HWE_HTBPLL_RFSLIP |         \
 550                          INFINIPATH_HWE_HTAPLL_FBSLIP |         \
 551                          INFINIPATH_HWE_HTAPLL_RFSLIP)
 552
 553         if (hwerrs & _IPATH_PLL_FAIL) {
 554                 snprintf(bitsmsg, sizeof bitsmsg,
 555                          "[PLL failed (%llx), HT-400 unusable]",
 556                          (unsigned long long) (hwerrs & _IPATH_PLL_FAIL));
 557                 strlcat(msg, bitsmsg, msgl);
 558                 /* ignore from now on, so disable until driver reloaded */
 559                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
 560                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 561                                  dd->ipath_hwerrmask);
 562         }
 563
 564         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
 565                 /*
 566                  * If it occurs, it is left masked since the eternal
 567                  * interface is unused
 568                  */
 569                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 570                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 571                                  dd->ipath_hwerrmask);
 572         }
 573
 574         if (hwerrs & INFINIPATH_HWE_RXDSYNCMEMPARITYERR)
 575                 strlcat(msg, "[Rx Dsync]", msgl);
 576         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED)
 577                 strlcat(msg, "[SerDes PLL]", msgl);
 578
 579         ipath_dev_err(dd, "%s hardware error\n", msg);
 580         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
 581                 /*
 582                  * for status file; if no trailing brace is copied,
 583                  * we'll know it was truncated.
 584                  */
 585                 snprintf(dd->ipath_freezemsg,
 586                          dd->ipath_freezelen, "{%s}", msg);
 587
 588 bail:;
 589 }
 590
 591 /**
 592  * ipath_ht_boardname - fill in the board name
 593  * @dd: the infinipath device
 594  * @name: the output buffer
 595  * @namelen: the size of the output buffer
 596  *
 597  * fill in the board name, based on the board revision register
 598  */
 599 static int ipath_ht_boardname(struct ipath_devdata *dd, char *name,
 600                               size_t namelen)
 601 {
 602         char *n = NULL;
 603         u8 boardrev = dd->ipath_boardrev;
 604         int ret;
 605
 606         switch (boardrev) {
 607         case 4:         /* Ponderosa is one of the bringup boards */
 608                 n = "Ponderosa";
 609                 break;
 610         case 5:
 611                 /*
 612                  * HT-460 original production board; two production levels, with
 613                  * different serial number ranges.   See ipath_ht_early_init() for
 614                  * case where we enable IPATH_GPIO_INTR for later serial # range.
 615                  */
 616                 n = "InfiniPath_HT-460";
 617                 break;
 618         case 6:
 619                 n = "OEM_Board_3";
 620                 break;
 621         case 7:
 622                 /* HT-460 small form factor production board */
 623                 n = "InfiniPath_HT-465";
 624                 break;
 625         case 8:
 626                 n = "LS/X-1";
 627                 break;
 628         case 9:         /* Comstock bringup test board */
 629                 n = "Comstock";
 630                 break;
 631         case 10:
 632                 n = "OEM_Board_2";
 633                 break;
 634         case 11:
 635                 n = "InfiniPath_HT-470";
 636                 break;
 637         case 12:
 638                 n = "OEM_Board_4";
 639                 break;
 640         default:                /* don't know, just print the number */
 641                 ipath_dev_err(dd, "Don't yet know about board "
 642                               "with ID %u\n", boardrev);
 643                 snprintf(name, namelen, "Unknown_InfiniPath_HT-4xx_%u",
 644                          boardrev);
 645                 break;
 646         }
 647         if (n)
 648                 snprintf(name, namelen, "%s", n);
 649
 650         if (dd->ipath_majrev != 3 || (dd->ipath_minrev < 2 || dd->ipath_minrev > 3)) {
 651                 /*
 652                  * This version of the driver only supports the HT-400
 653                  * Rev 3.2
 654                  */
 655                 ipath_dev_err(dd,
 656                               "Unsupported HT-400 revision %u.%u!\n",
 657                               dd->ipath_majrev, dd->ipath_minrev);
 658                 ret = 1;
 659                 goto bail;
 660         }
 661         /*
 662          * pkt/word counters are 32 bit, and therefore wrap fast enough
 663          * that we snapshot them from a timer, and maintain 64 bit shadow
 664          * copies
 665          */
 666         dd->ipath_flags |= IPATH_32BITCOUNTERS;
 667         if (dd->ipath_htspeed != 800)
 668                 ipath_dev_err(dd,
 669                               "Incorrectly configured for HT @ %uMHz\n",
 670                               dd->ipath_htspeed);
 671         if (dd->ipath_boardrev == 7 || dd->ipath_boardrev == 11 ||
 672             dd->ipath_boardrev == 6)
 673                 dd->ipath_flags |= IPATH_GPIO_INTR;
 674         else
 675                 dd->ipath_flags |= IPATH_POLL_RX_INTR;
 676         if (dd->ipath_boardrev == 8) {  /* LS/X-1 */
 677                 u64 val;
 678                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
 679                 if (val & INFINIPATH_EXTS_SERDESSEL) {
 680                         /*
 681                          * hardware disabled
 682                          *
 683                          * This means that the chip is hardware disabled,
 684                          * and will not be able to bring up the link,
 685                          * in any case.  We special case this and abort
 686                          * early, to avoid later messages.  We also set
 687                          * the DISABLED status bit
 688                          */
 689                         ipath_dbg("Unit %u is hardware-disabled\n",
 690                                   dd->ipath_unit);
 691                         *dd->ipath_statusp |= IPATH_STATUS_DISABLED;
 692                         /* this value is handled differently */
 693                         ret = 2;
 694                         goto bail;
 695                 }
 696         }
 697         ret = 0;
 698
 699 bail:
 700         return ret;
 701 }
 702
 703 static void ipath_check_htlink(struct ipath_devdata *dd)
 704 {
 705         u8 linkerr, link_off, i;
 706
 707         for (i = 0; i < 2; i++) {
 708                 link_off = dd->ipath_ht_slave_off + i * 4 + 0xd;
 709                 if (pci_read_config_byte(dd->pcidev, link_off, &linkerr))
 710                         dev_info(&dd->pcidev->dev, "Couldn't read "
 711                                  "linkerror%d of HT slave/primary block\n",
 712                                  i);
 713                 else if (linkerr & 0xf0) {
 714                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
 715                                    "clearing\n", linkerr >> 4, i);
 716                         /*
 717                          * writing the linkerr bits that are set should
 718                          * clear them
 719                          */
 720                         if (pci_write_config_byte(dd->pcidev, link_off,
 721                                                   linkerr))
 722                                 ipath_dbg("Failed write to clear HT "
 723                                           "linkerror%d\n", i);
 724                         if (pci_read_config_byte(dd->pcidev, link_off,
 725                                                  &linkerr))
 726                                 dev_info(&dd->pcidev->dev,
 727                                          "Couldn't reread linkerror%d of "
 728                                          "HT slave/primary block\n", i);
 729                         else if (linkerr & 0xf0)
 730                                 dev_info(&dd->pcidev->dev,
 731                                          "HT linkerror%d bits 0x%x "
 732                                          "couldn't be cleared\n",
 733                                          i, linkerr >> 4);
 734                 }
 735         }
 736 }
 737
 738 static int ipath_setup_ht_reset(struct ipath_devdata *dd)
 739 {
 740         ipath_dbg("No reset possible for HT-400\n");
 741         return 0;
 742 }
 743
 744 #define HT_CAPABILITY_ID   0x08 /* HT capabilities not defined in kernel */
 745 #define HT_INTR_DISC_CONFIG  0x80       /* HT interrupt and discovery cap */
 746 #define HT_INTR_REG_INDEX    2  /* intconfig requires indirect accesses */
 747
 748 /*
 749  * Bits 13-15 of command==0 is slave/primary block.  Clear any HT CRC
 750  * errors.  We only bother to do this at load time, because it's OK if
 751  * it happened before we were loaded (first time after boot/reset),
 752  * but any time after that, it's fatal anyway.  Also need to not check
 753  * for for upper byte errors if we are in 8 bit mode, so figure out
 754  * our width.  For now, at least, also complain if it's 8 bit.
 755  */
 756 static void slave_or_pri_blk(struct ipath_devdata *dd, struct pci_dev *pdev,
 757                              int pos, u8 cap_type)
 758 {
 759         u8 linkwidth = 0, linkerr, link_a_b_off, link_off;
 760         u16 linkctrl = 0;
 761         int i;
 762
 763         dd->ipath_ht_slave_off = pos;
 764         /* command word, master_host bit */
 765         /* master host || slave */
 766         if ((cap_type >> 2) & 1)
 767                 link_a_b_off = 4;
 768         else
 769                 link_a_b_off = 0;
 770         ipath_cdbg(VERBOSE, "HT%u (Link %c) connected to processor\n",
 771                    link_a_b_off ? 1 : 0,
 772                    link_a_b_off ? 'B' : 'A');
 773
 774         link_a_b_off += pos;
 775
 776         /*
 777          * check both link control registers; clear both HT CRC sets if
 778          * necessary.
 779          */
 780         for (i = 0; i < 2; i++) {
 781                 link_off = pos + i * 4 + 0x4;
 782                 if (pci_read_config_word(pdev, link_off, &linkctrl))
 783                         ipath_dev_err(dd, "Couldn't read HT link control%d "
 784                                       "register\n", i);
 785                 else if (linkctrl & (0xf << 8)) {
 786                         ipath_cdbg(VERBOSE, "Clear linkctrl%d CRC Error "
 787                                    "bits %x\n", i, linkctrl & (0xf << 8));
 788                         /*
 789                          * now write them back to clear the error.
 790                          */
 791                         pci_write_config_byte(pdev, link_off,
 792                                               linkctrl & (0xf << 8));
 793                 }
 794         }
 795
 796         /*
 797          * As with HT CRC bits, same for protocol errors that might occur
 798          * during boot.
 799          */
 800         for (i = 0; i < 2; i++) {
 801                 link_off = pos + i * 4 + 0xd;
 802                 if (pci_read_config_byte(pdev, link_off, &linkerr))
 803                         dev_info(&pdev->dev, "Couldn't read linkerror%d "
 804                                  "of HT slave/primary block\n", i);
 805                 else if (linkerr & 0xf0) {
 806                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
 807                                    "clearing\n", linkerr >> 4, i);
 808                         /*
 809                          * writing the linkerr bits that are set will clear
 810                          * them
 811                          */
 812                         if (pci_write_config_byte
 813                             (pdev, link_off, linkerr))
 814                                 ipath_dbg("Failed write to clear HT "
 815                                           "linkerror%d\n", i);
 816                         if (pci_read_config_byte(pdev, link_off, &linkerr))
 817                                 dev_info(&pdev->dev, "Couldn't reread "
 818                                          "linkerror%d of HT slave/primary "
 819                                          "block\n", i);
 820                         else if (linkerr & 0xf0)
 821                                 dev_info(&pdev->dev, "HT linkerror%d bits "
 822                                          "0x%x couldn't be cleared\n",
 823                                          i, linkerr >> 4);
 824                 }
 825         }
 826
 827         /*
 828          * this is just for our link to the host, not devices connected
 829          * through tunnel.
 830          */
 831
 832         if (pci_read_config_byte(pdev, link_a_b_off + 7, &linkwidth))
 833                 ipath_dev_err(dd, "Couldn't read HT link width "
 834                               "config register\n");
 835         else {
 836                 u32 width;
 837                 switch (linkwidth & 7) {
 838                 case 5:
 839                         width = 4;
 840                         break;
 841                 case 4:
 842                         width = 2;
 843                         break;
 844                 case 3:
 845                         width = 32;
 846                         break;
 847                 case 1:
 848                         width = 16;
 849                         break;
 850                 case 0:
 851                 default:        /* if wrong, assume 8 bit */
 852                         width = 8;
 853                         break;
 854                 }
 855
 856                 dd->ipath_htwidth = width;
 857
 858                 if (linkwidth != 0x11) {
 859                         ipath_dev_err(dd, "Not configured for 16 bit HT "
 860                                       "(%x)\n", linkwidth);
 861                         if (!(linkwidth & 0xf)) {
 862                                 ipath_dbg("Will ignore HT lane1 errors\n");
 863                                 dd->ipath_flags |= IPATH_8BIT_IN_HT0;
 864                         }
 865                 }
 866         }
 867
 868         /*
 869          * this is just for our link to the host, not devices connected
 870          * through tunnel.
 871          */
 872         if (pci_read_config_byte(pdev, link_a_b_off + 0xd, &linkwidth))
 873                 ipath_dev_err(dd, "Couldn't read HT link frequency "
 874                               "config register\n");
 875         else {
 876                 u32 speed;
 877                 switch (linkwidth & 0xf) {
 878                 case 6:
 879                         speed = 1000;
 880                         break;
 881                 case 5:
 882                         speed = 800;
 883                         break;
 884                 case 4:
 885                         speed = 600;
 886                         break;
 887                 case 3:
 888                         speed = 500;
 889                         break;
 890                 case 2:
 891                         speed = 400;
 892                         break;
 893                 case 1:
 894                         speed = 300;
 895                         break;
 896                 default:
 897                         /*
 898                          * assume reserved and vendor-specific are 200...
 899                          */
 900                 case 0:
 901                         speed = 200;
 902                         break;
 903                 }
 904                 dd->ipath_htspeed = speed;
 905         }
 906 }
 907
 908 static int set_int_handler(struct ipath_devdata *dd, struct pci_dev *pdev,
 909                             int pos)
 910 {
 911         u32 int_handler_addr_lower;
 912         u32 int_handler_addr_upper;
 913         u64 ihandler;
 914         u32 intvec;
 915
 916         /* use indirection register to get the intr handler */
 917         pci_write_config_byte(pdev, pos + HT_INTR_REG_INDEX, 0x10);
 918         pci_read_config_dword(pdev, pos + 4, &int_handler_addr_lower);
 919         pci_write_config_byte(pdev, pos + HT_INTR_REG_INDEX, 0x11);
 920         pci_read_config_dword(pdev, pos + 4, &int_handler_addr_upper);
 921
 922         ihandler = (u64) int_handler_addr_lower |
 923                 ((u64) int_handler_addr_upper << 32);
 924
 925         /*
 926          * kernels with CONFIG_PCI_MSI set the vector in the irq field of
 927          * struct pci_device, so we use that to program the HT-400 internal
 928          * interrupt register (not config space) with that value. The BIOS
 929          * must still have done the basic MSI setup.
 930          */
 931         intvec = pdev->irq;
 932         /*
 933          * clear any vector bits there; normally not set but we'll overload
 934          * this for some debug purposes (setting the HTC debug register
 935          * value from software, rather than GPIOs), so it might be set on a
 936          * driver reload.
 937          */
 938         ihandler &= ~0xff0000;
 939         /* x86 vector goes in intrinfo[23:16] */
 940         ihandler |= intvec << 16;
 941         ipath_cdbg(VERBOSE, "ihandler lower %x, upper %x, intvec %x, "
 942                    "interruptconfig %llx\n", int_handler_addr_lower,
 943                    int_handler_addr_upper, intvec,
 944                    (unsigned long long) ihandler);
 945
 946         /* can't program yet, so save for interrupt setup */
 947         dd->ipath_intconfig = ihandler;
 948         /* keep going, so we find link control stuff also */
 949
 950         return ihandler != 0;
 951 }
 952
 953 /**
 954  * ipath_setup_ht_config - setup the interruptconfig register
 955  * @dd: the infinipath device
 956  * @pdev: the PCI device
 957  *
 958  * setup the interruptconfig register from the HT config info.
 959  * Also clear CRC errors in HT linkcontrol, if necessary.
 960  * This is done only for the real hardware.  It is done before
 961  * chip address space is initted, so can't touch infinipath registers
 962  */
 963 static int ipath_setup_ht_config(struct ipath_devdata *dd,
 964                                  struct pci_dev *pdev)
 965 {
 966         int pos, ret = 0;
 967         int ihandler = 0;
 968
 969         /*
 970          * Read the capability info to find the interrupt info, and also
 971          * handle clearing CRC errors in linkctrl register if necessary.  We
 972          * do this early, before we ever enable errors or hardware errors,
 973          * mostly to avoid causing the chip to enter freeze mode.
 974          */
 975         pos = pci_find_capability(pdev, HT_CAPABILITY_ID);
 976         if (!pos) {
 977                 ipath_dev_err(dd, "Couldn't find HyperTransport "
 978                               "capability; no interrupts\n");
 979                 ret = -ENODEV;
 980                 goto bail;
 981         }
 982         do {
 983                 u8 cap_type;
 984
 985                 /* the HT capability type byte is 3 bytes after the
 986                  * capability byte.
 987                  */
 988                 if (pci_read_config_byte(pdev, pos + 3, &cap_type)) {
 989                         dev_info(&pdev->dev, "Couldn't read config "
 990                                  "command @ %d\n", pos);
 991                         continue;
 992                 }
 993                 if (!(cap_type & 0xE0))
 994                         slave_or_pri_blk(dd, pdev, pos, cap_type);
 995                 else if (cap_type == HT_INTR_DISC_CONFIG)
 996                         ihandler = set_int_handler(dd, pdev, pos);
 997         } while ((pos = pci_find_next_capability(pdev, pos,
 998                                                  HT_CAPABILITY_ID)));
 999
1000         if (!ihandler) {
1001                 ipath_dev_err(dd, "Couldn't find interrupt handler in "
1002                               "config space\n");
1003                 ret = -ENODEV;
1004         }
1005
1006 bail:
1007         return ret;
1008 }
1009
1010 /**
1011  * ipath_setup_ht_cleanup - clean up any per-chip chip-specific stuff
1012  * @dd: the infinipath device
1013  *
1014  * Called during driver unload.
1015  * This is currently a nop for the HT-400, not for all chips
1016  */
1017 static void ipath_setup_ht_cleanup(struct ipath_devdata *dd)
1018 {
1019 }
1020
1021 /**
1022  * ipath_setup_ht_setextled - set the state of the two external LEDs
1023  * @dd: the infinipath device
1024  * @lst: the L state
1025  * @ltst: the LT state
1026  *
1027  * Set the state of the two external LEDs, to indicate physical and
1028  * logical state of IB link.   For this chip (at least with recommended
1029  * board pinouts), LED1 is Green (physical state), and LED2 is Yellow
1030  * (logical state)
1031  *
1032  * Note:  We try to match the Mellanox HCA LED behavior as best
1033  * we can.  Green indicates physical link state is OK (something is
1034  * plugged in, and we can train).
1035  * Amber indicates the link is logically up (ACTIVE).
1036  * Mellanox further blinks the amber LED to indicate data packet
1037  * activity, but we have no hardware support for that, so it would
1038  * require waking up every 10-20 msecs and checking the counters
1039  * on the chip, and then turning the LED off if appropriate.  That's
1040  * visible overhead, so not something we will do.
1041  *
1042  */
1043 static void ipath_setup_ht_setextled(struct ipath_devdata *dd,
1044                                      u64 lst, u64 ltst)
1045 {
1046         u64 extctl;
1047
1048         /* the diags use the LED to indicate diag info, so we leave
1049          * the external LED alone when the diags are running */
1050         if (ipath_diag_inuse)
1051                 return;
1052
1053         /*
1054          * start by setting both LED control bits to off, then turn
1055          * on the appropriate bit(s).
1056          */
1057         if (dd->ipath_boardrev == 8) { /* LS/X-1 uses different pins */
1058                 /*
1059                  * major difference is that INFINIPATH_EXTC_LEDGBLERR_OFF
1060                  * is inverted,  because it is normally used to indicate
1061                  * a hardware fault at reset, if there were errors
1062                  */
1063                 extctl = (dd->ipath_extctrl & ~INFINIPATH_EXTC_LEDGBLOK_ON)
1064                         | INFINIPATH_EXTC_LEDGBLERR_OFF;
1065                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1066                         extctl &= ~INFINIPATH_EXTC_LEDGBLERR_OFF;
1067                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1068                         extctl |= INFINIPATH_EXTC_LEDGBLOK_ON;
1069         }
1070         else {
1071                 extctl = dd->ipath_extctrl &
1072                         ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
1073                           INFINIPATH_EXTC_LED2PRIPORT_ON);
1074                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1075                         extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
1076                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1077                         extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
1078         }
1079         dd->ipath_extctrl = extctl;
1080         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
1081 }
1082
1083 static void ipath_init_ht_variables(void)
1084 {
1085         ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1086         ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1087         ipath_gpio_sda = IPATH_GPIO_SDA;
1088         ipath_gpio_scl = IPATH_GPIO_SCL;
1089
1090         infinipath_i_bitsextant =
1091                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1092                 (INFINIPATH_I_RCVAVAIL_MASK <<
1093                  INFINIPATH_I_RCVAVAIL_SHIFT) |
1094                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1095                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1096
1097         infinipath_e_bitsextant =
1098                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1099                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1100                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1101                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1102                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1103                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1104                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1105                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1106                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1107                 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1108                 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1109                 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1110                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1111                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1112                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1113                 INFINIPATH_E_HARDWARE;
1114
1115         infinipath_hwe_bitsextant =
1116                 (INFINIPATH_HWE_HTCMEMPARITYERR_MASK <<
1117                  INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) |
1118                 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1119                  INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1120                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1121                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1122                 INFINIPATH_HWE_HTCLNKABYTE0CRCERR |
1123                 INFINIPATH_HWE_HTCLNKABYTE1CRCERR |
1124                 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR |
1125                 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR |
1126                 INFINIPATH_HWE_HTCMISCERR4 |
1127                 INFINIPATH_HWE_HTCMISCERR5 | INFINIPATH_HWE_HTCMISCERR6 |
1128                 INFINIPATH_HWE_HTCMISCERR7 |
1129                 INFINIPATH_HWE_HTCBUSTREQPARITYERR |
1130                 INFINIPATH_HWE_HTCBUSTRESPPARITYERR |
1131                 INFINIPATH_HWE_HTCBUSIREQPARITYERR |
1132                 INFINIPATH_HWE_RXDSYNCMEMPARITYERR |
1133                 INFINIPATH_HWE_MEMBISTFAILED |
1134                 INFINIPATH_HWE_COREPLL_FBSLIP |
1135                 INFINIPATH_HWE_COREPLL_RFSLIP |
1136                 INFINIPATH_HWE_HTBPLL_FBSLIP |
1137                 INFINIPATH_HWE_HTBPLL_RFSLIP |
1138                 INFINIPATH_HWE_HTAPLL_FBSLIP |
1139                 INFINIPATH_HWE_HTAPLL_RFSLIP |
1140                 INFINIPATH_HWE_SERDESPLLFAILED |
1141                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1142                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1143
1144         infinipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1145         infinipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1146 }
1147
1148 /**
1149  * ipath_ht_init_hwerrors - enable hardware errors
1150  * @dd: the infinipath device
1151  *
1152  * now that we have finished initializing everything that might reasonably
1153  * cause a hardware error, and cleared those errors bits as they occur,
1154  * we can enable hardware errors in the mask (potentially enabling
1155  * freeze mode), and enable hardware errors as errors (along with
1156  * everything else) in errormask
1157  */
1158 static void ipath_ht_init_hwerrors(struct ipath_devdata *dd)
1159 {
1160         ipath_err_t val;
1161         u64 extsval;
1162
1163         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
1164
1165         if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
1166                 ipath_dev_err(dd, "MemBIST did not complete!\n");
1167
1168         ipath_check_htlink(dd);
1169
1170         /* barring bugs, all hwerrors become interrupts, which can */
1171         val = -1LL;
1172         /* don't look at crc lane1 if 8 bit */
1173         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
1174                 val &= ~infinipath_hwe_htclnkabyte1crcerr;
1175         /* don't look at crc lane1 if 8 bit */
1176         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
1177                 val &= ~infinipath_hwe_htclnkbbyte1crcerr;
1178
1179         /*
1180          * disable RXDSYNCMEMPARITY because external serdes is unused,
1181          * and therefore the logic will never be used or initialized,
1182          * and uninitialized state will normally result in this error
1183          * being asserted.  Similarly for the external serdess pll
1184          * lock signal.
1185          */
1186         val &= ~(INFINIPATH_HWE_SERDESPLLFAILED |
1187                  INFINIPATH_HWE_RXDSYNCMEMPARITYERR);
1188
1189         /*
1190          * Disable MISCERR4 because of an inversion in the HT core
1191          * logic checking for errors that cause this bit to be set.
1192          * The errata can also cause the protocol error bit to be set
1193          * in the HT config space linkerror register(s).
1194          */
1195         val &= ~INFINIPATH_HWE_HTCMISCERR4;
1196
1197         /*
1198          * PLL ignored because MDIO interface has a logic problem
1199          * for reads, on Comstock and Ponderosa.  BRINGUP
1200          */
1201         if (dd->ipath_boardrev == 4 || dd->ipath_boardrev == 9)
1202                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
1203         dd->ipath_hwerrmask = val;
1204 }
1205
1206 /**
1207  * ipath_ht_bringup_serdes - bring up the serdes
1208  * @dd: the infinipath device
1209  */
1210 static int ipath_ht_bringup_serdes(struct ipath_devdata *dd)
1211 {
1212         u64 val, config1;
1213         int ret = 0, change = 0;
1214
1215         ipath_dbg("Trying to bringup serdes\n");
1216
1217         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
1218             INFINIPATH_HWE_SERDESPLLFAILED)
1219         {
1220                 ipath_dbg("At start, serdes PLL failed bit set in "
1221                           "hwerrstatus, clearing and continuing\n");
1222                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
1223                                  INFINIPATH_HWE_SERDESPLLFAILED);
1224         }
1225
1226         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1227         config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
1228
1229         ipath_cdbg(VERBOSE, "Initial serdes status is config0=%llx "
1230                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1231                    (unsigned long long) val, (unsigned long long) config1,
1232                    (unsigned long long)
1233                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1234                    (unsigned long long)
1235                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1236
1237         /* force reset on */
1238         val |= INFINIPATH_SERDC0_RESET_PLL
1239                 /* | INFINIPATH_SERDC0_RESET_MASK */
1240                 ;
1241         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1242         udelay(15);             /* need pll reset set at least for a bit */
1243
1244         if (val & INFINIPATH_SERDC0_RESET_PLL) {
1245                 u64 val2 = val &= ~INFINIPATH_SERDC0_RESET_PLL;
1246                 /* set lane resets, and tx idle, during pll reset */
1247                 val2 |= INFINIPATH_SERDC0_RESET_MASK |
1248                         INFINIPATH_SERDC0_TXIDLE;
1249                 ipath_cdbg(VERBOSE, "Clearing serdes PLL reset (writing "
1250                            "%llx)\n", (unsigned long long) val2);
1251                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1252                                  val2);
1253                 /*
1254                  * be sure chip saw it
1255                  */
1256                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1257                 /*
1258                  * need pll reset clear at least 11 usec before lane
1259                  * resets cleared; give it a few more
1260                  */
1261                 udelay(15);
1262                 val = val2;     /* for check below */
1263         }
1264
1265         if (val & (INFINIPATH_SERDC0_RESET_PLL |
1266                    INFINIPATH_SERDC0_RESET_MASK |
1267                    INFINIPATH_SERDC0_TXIDLE)) {
1268                 val &= ~(INFINIPATH_SERDC0_RESET_PLL |
1269                          INFINIPATH_SERDC0_RESET_MASK |
1270                          INFINIPATH_SERDC0_TXIDLE);
1271                 /* clear them */
1272                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1273                                  val);
1274         }
1275
1276         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1277         if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
1278              INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
1279                 val &= ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
1280                          INFINIPATH_XGXS_MDIOADDR_SHIFT);
1281                 /*
1282                  * we use address 3
1283                  */
1284                 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
1285                 change = 1;
1286         }
1287         if (val & INFINIPATH_XGXS_RESET) {
1288                 /* normally true after boot */
1289                 val &= ~INFINIPATH_XGXS_RESET;
1290                 change = 1;
1291         }
1292         if (change)
1293                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1294
1295         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1296
1297         /* clear current and de-emphasis bits */
1298         config1 &= ~0x0ffffffff00ULL;
1299         /* set current to 20ma */
1300         config1 |= 0x00000000000ULL;
1301         /* set de-emphasis to -5.68dB */
1302         config1 |= 0x0cccc000000ULL;
1303         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
1304
1305         ipath_cdbg(VERBOSE, "After setup: serdes status is config0=%llx "
1306                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1307                    (unsigned long long) val, (unsigned long long) config1,
1308                    (unsigned long long)
1309                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1310                    (unsigned long long)
1311                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1312
1313         if (!ipath_waitfor_mdio_cmdready(dd)) {
1314                 ipath_write_kreg(dd, dd->ipath_kregs->kr_mdio,
1315                                  ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
1316                                                 IPATH_MDIO_CTRL_XGXS_REG_8,
1317                                                 0));
1318                 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
1319                                            IPATH_MDIO_DATAVALID, &val))
1320                         ipath_dbg("Never got MDIO data for XGXS status "
1321                                   "read\n");
1322                 else
1323                         ipath_cdbg(VERBOSE, "MDIO Read reg8, "
1324                                    "'bank' 31 %x\n", (u32) val);
1325         } else
1326                 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
1327
1328         return ret;             /* for now, say we always succeeded */
1329 }
1330
1331 /**
1332  * ipath_ht_quiet_serdes - set serdes to txidle
1333  * @dd: the infinipath device
1334  * driver is being unloaded
1335  */
1336 static void ipath_ht_quiet_serdes(struct ipath_devdata *dd)
1337 {
1338         u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1339
1340         val |= INFINIPATH_SERDC0_TXIDLE;
1341         ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
1342                   (unsigned long long) val);
1343         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1344 }
1345
1346 static int ipath_ht_intconfig(struct ipath_devdata *dd)
1347 {
1348         int ret;
1349
1350         if (!dd->ipath_intconfig) {
1351                 ipath_dev_err(dd, "No interrupts enabled, couldn't setup "
1352                               "interrupt address\n");
1353                 ret = 1;
1354                 goto bail;
1355         }
1356
1357         ipath_write_kreg(dd, dd->ipath_kregs->kr_interruptconfig,
1358                          dd->ipath_intconfig);  /* interrupt address */
1359         ret = 0;
1360
1361 bail:
1362         return ret;
1363 }
1364
1365 /**
1366  * ipath_pe_put_tid - write a TID in chip
1367  * @dd: the infinipath device
1368  * @tidptr: pointer to the expected TID (in chip) to udpate
1369  * @tidtype: 0 for eager, 1 for expected
1370  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1371  *
1372  * This exists as a separate routine to allow for special locking etc.
1373  * It's used for both the full cleanup on exit, as well as the normal
1374  * setup and teardown.
1375  */
1376 static void ipath_ht_put_tid(struct ipath_devdata *dd,
1377                              u64 __iomem *tidptr, u32 type,
1378                              unsigned long pa)
1379 {
1380         if (pa != dd->ipath_tidinvalid) {
1381                 if (unlikely((pa & ~INFINIPATH_RT_ADDR_MASK))) {
1382                         dev_info(&dd->pcidev->dev,
1383                                  "physaddr %lx has more than "
1384                                  "40 bits, using only 40!!!\n", pa);
1385                         pa &= INFINIPATH_RT_ADDR_MASK;
1386                 }
1387                 if (type == 0)
1388                         pa |= dd->ipath_tidtemplate;
1389                 else {
1390                         /* in words (fixed, full page).  */
1391                         u64 lenvalid = PAGE_SIZE >> 2;
1392                         lenvalid <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1393                         pa |= lenvalid | INFINIPATH_RT_VALID;
1394                 }
1395         }
1396         if (dd->ipath_kregbase)
1397                 writeq(pa, tidptr);
1398 }
1399
1400 /**
1401  * ipath_ht_clear_tid - clear all TID entries for a port, expected and eager
1402  * @dd: the infinipath device
1403  * @port: the port
1404  *
1405  * Used from ipath_close(), and at chip initialization.
1406  */
1407 static void ipath_ht_clear_tids(struct ipath_devdata *dd, unsigned port)
1408 {
1409         u64 __iomem *tidbase;
1410         int i;
1411
1412         if (!dd->ipath_kregbase)
1413                 return;
1414
1415         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1416
1417         /*
1418          * need to invalidate all of the expected TID entries for this
1419          * port, so we don't have valid entries that might somehow get
1420          * used (early in next use of this port, or through some bug)
1421          */
1422         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1423                                    dd->ipath_rcvtidbase +
1424                                    port * dd->ipath_rcvtidcnt *
1425                                    sizeof(*tidbase));
1426         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1427                 ipath_ht_put_tid(dd, &tidbase[i], 1, dd->ipath_tidinvalid);
1428
1429         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1430                                    dd->ipath_rcvegrbase +
1431                                    port * dd->ipath_rcvegrcnt *
1432                                    sizeof(*tidbase));
1433
1434         for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1435                 ipath_ht_put_tid(dd, &tidbase[i], 0, dd->ipath_tidinvalid);
1436 }
1437
1438 /**
1439  * ipath_ht_tidtemplate - setup constants for TID updates
1440  * @dd: the infinipath device
1441  *
1442  * We setup stuff that we use a lot, to avoid calculating each time
1443  */
1444 static void ipath_ht_tidtemplate(struct ipath_devdata *dd)
1445 {
1446         dd->ipath_tidtemplate = dd->ipath_ibmaxlen >> 2;
1447         dd->ipath_tidtemplate <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1448         dd->ipath_tidtemplate |= INFINIPATH_RT_VALID;
1449
1450         /*
1451          * work around chip errata bug 7358, by marking invalid tids
1452          * as having max length
1453          */
1454         dd->ipath_tidinvalid = (-1LL & INFINIPATH_RT_BUFSIZE_MASK) <<
1455                 INFINIPATH_RT_BUFSIZE_SHIFT;
1456 }
1457
1458 static int ipath_ht_early_init(struct ipath_devdata *dd)
1459 {
1460         u32 __iomem *piobuf;
1461         u32 pioincr, val32, egrsize;
1462         int i;
1463
1464         /*
1465          * one cache line; long IB headers will spill over into received
1466          * buffer
1467          */
1468         dd->ipath_rcvhdrentsize = 16;
1469         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1470
1471         /*
1472          * For HT-400, we allocate a somewhat overly large eager buffer,
1473          * such that we can guarantee that we can receive the largest
1474          * packet that we can send out.  To truly support a 4KB MTU,
1475          * we need to bump this to a large value.  To date, other than
1476          * testing, we have never encountered an HCA that can really
1477          * send 4KB MTU packets, so we do not handle that (we'll get
1478          * errors interrupts if we ever see one).
1479          */
1480         dd->ipath_rcvegrbufsize = dd->ipath_piosize2k;
1481         egrsize = dd->ipath_rcvegrbufsize;
1482
1483         /*
1484          * the min() check here is currently a nop, but it may not
1485          * always be, depending on just how we do ipath_rcvegrbufsize
1486          */
1487         dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1488                                  dd->ipath_rcvegrbufsize);
1489         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1490         ipath_ht_tidtemplate(dd);
1491
1492         /*
1493          * zero all the TID entries at startup.  We do this for sanity,
1494          * in case of a previous driver crash of some kind, and also
1495          * because the chip powers up with these memories in an unknown
1496          * state.  Use portcnt, not cfgports, since this is for the
1497          * full chip, not for current (possibly different) configuration
1498          * value.
1499          * Chip Errata bug 6447
1500          */
1501         for (val32 = 0; val32 < dd->ipath_portcnt; val32++)
1502                 ipath_ht_clear_tids(dd, val32);
1503
1504         /*
1505          * write the pbc of each buffer, to be sure it's initialized, then
1506          * cancel all the buffers, and also abort any packets that might
1507          * have been in flight for some reason (the latter is for driver
1508          * unload/reload, but isn't a bad idea at first init).  PIO send
1509          * isn't enabled at this point, so there is no danger of sending
1510          * these out on the wire.
1511          * Chip Errata bug 6610
1512          */
1513         piobuf = (u32 __iomem *) (((char __iomem *)(dd->ipath_kregbase)) +
1514                                   dd->ipath_piobufbase);
1515         pioincr = dd->ipath_palign / sizeof(*piobuf);
1516         for (i = 0; i < dd->ipath_piobcnt2k; i++) {
1517                 /*
1518                  * reasonable word count, just to init pbc
1519                  */
1520                 writel(16, piobuf);
1521                 piobuf += pioincr;
1522         }
1523         /*
1524          * self-clearing
1525          */
1526         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1527                          INFINIPATH_S_ABORT);
1528
1529         ipath_get_eeprom_info(dd);
1530         if(dd->ipath_boardrev == 5 && dd->ipath_serial[0] == '1' &&
1531                 dd->ipath_serial[1] == '2' && dd->ipath_serial[2] == '8') {
1532                 /*
1533                  * Later production HT-460 has same changes as HT-465, so
1534                  * can use GPIO interrupts.  They have serial #'s starting
1535                  * with 128, rather than 112.
1536                  */
1537                 dd->ipath_flags |= IPATH_GPIO_INTR;
1538                 dd->ipath_flags &= ~IPATH_POLL_RX_INTR;
1539         }
1540         return 0;
1541 }
1542
1543 /**
1544  * ipath_init_ht_get_base_info - set chip-specific flags for user code
1545  * @dd: the infinipath device
1546  * @kbase: ipath_base_info pointer
1547  *
1548  * We set the PCIE flag because the lower bandwidth on PCIe vs
1549  * HyperTransport can affect some user packet algorithims.
1550  */
1551 static int ipath_ht_get_base_info(struct ipath_portdata *pd, void *kbase)
1552 {
1553         struct ipath_base_info *kinfo = kbase;
1554
1555         kinfo->spi_runtime_flags |= IPATH_RUNTIME_HT |
1556                 IPATH_RUNTIME_RCVHDR_COPY;
1557
1558         return 0;
1559 }
1560
1561 /**
1562  * ipath_init_ht400_funcs - set up the chip-specific function pointers
1563  * @dd: the infinipath device
1564  *
1565  * This is global, and is called directly at init to set up the
1566  * chip-specific function pointers for later use.
1567  */
1568 void ipath_init_ht400_funcs(struct ipath_devdata *dd)
1569 {
1570         dd->ipath_f_intrsetup = ipath_ht_intconfig;
1571         dd->ipath_f_bus = ipath_setup_ht_config;
1572         dd->ipath_f_reset = ipath_setup_ht_reset;
1573         dd->ipath_f_get_boardname = ipath_ht_boardname;
1574         dd->ipath_f_init_hwerrors = ipath_ht_init_hwerrors;
1575         dd->ipath_f_init_hwerrors = ipath_ht_init_hwerrors;
1576         dd->ipath_f_early_init = ipath_ht_early_init;
1577         dd->ipath_f_handle_hwerrors = ipath_ht_handle_hwerrors;
1578         dd->ipath_f_quiet_serdes = ipath_ht_quiet_serdes;
1579         dd->ipath_f_bringup_serdes = ipath_ht_bringup_serdes;
1580         dd->ipath_f_clear_tids = ipath_ht_clear_tids;
1581         dd->ipath_f_put_tid = ipath_ht_put_tid;
1582         dd->ipath_f_cleanup = ipath_setup_ht_cleanup;
1583         dd->ipath_f_setextled = ipath_setup_ht_setextled;
1584         dd->ipath_f_get_base_info = ipath_ht_get_base_info;
1585
1586         /*
1587          * initialize chip-specific variables
1588          */
1589         dd->ipath_f_tidtemplate = ipath_ht_tidtemplate;
1590
1591         /*
1592          * setup the register offsets, since they are different for each
1593          * chip
1594          */
1595         dd->ipath_kregs = &ipath_ht_kregs;
1596         dd->ipath_cregs = &ipath_ht_cregs;
1597
1598         /*
1599          * do very early init that is needed before ipath_f_bus is
1600          * called
1601          */
1602         ipath_init_ht_variables();
1603 }