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   1 /*
   2  * srmmu.c:  SRMMU specific routines for memory management.
   3  *
   4  * Copyright (C) 1995 David S. Miller  (davem@caip.rutgers.edu)
   5  * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
   6  * Copyright (C) 1996 Eddie C. Dost    (ecd@skynet.be)
   7  * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   8  * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/mm.h>
  13 #include <linux/slab.h>
  14 #include <linux/vmalloc.h>
  15 #include <linux/pagemap.h>
  16 #include <linux/init.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/bootmem.h>
  19 #include <linux/fs.h>
  20 #include <linux/seq_file.h>
  21 #include <linux/kdebug.h>
  22
  23 #include <asm/bitext.h>
  24 #include <asm/page.h>
  25 #include <asm/pgalloc.h>
  26 #include <asm/pgtable.h>
  27 #include <asm/io.h>
  28 #include <asm/vaddrs.h>
  29 #include <asm/traps.h>
  30 #include <asm/smp.h>
  31 #include <asm/mbus.h>
  32 #include <asm/cache.h>
  33 #include <asm/oplib.h>
  34 #include <asm/asi.h>
  35 #include <asm/msi.h>
  36 #include <asm/mmu_context.h>
  37 #include <asm/io-unit.h>
  38 #include <asm/cacheflush.h>
  39 #include <asm/tlbflush.h>
  40
  41 /* Now the cpu specific definitions. */
  42 #include <asm/viking.h>
  43 #include <asm/mxcc.h>
  44 #include <asm/ross.h>
  45 #include <asm/tsunami.h>
  46 #include <asm/swift.h>
  47 #include <asm/turbosparc.h>
  48
  49 #include <asm/btfixup.h>
  50
  51 enum mbus_module srmmu_modtype;
  52 static unsigned int hwbug_bitmask;
  53 int vac_cache_size;
  54 int vac_line_size;
  55
  56 extern struct resource sparc_iomap;
  57
  58 extern unsigned long last_valid_pfn;
  59
  60 extern unsigned long page_kernel;
  61
  62 static pgd_t *srmmu_swapper_pg_dir;
  63
  64 #ifdef CONFIG_SMP
  65 #define FLUSH_BEGIN(mm)
  66 #define FLUSH_END
  67 #else
  68 #define FLUSH_BEGIN(mm) if((mm)->context != NO_CONTEXT) {
  69 #define FLUSH_END       }
  70 #endif
  71
  72 BTFIXUPDEF_CALL(void, flush_page_for_dma, unsigned long)
  73 #define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page)
  74
  75 int flush_page_for_dma_global = 1;
  76
  77 #ifdef CONFIG_SMP
  78 BTFIXUPDEF_CALL(void, local_flush_page_for_dma, unsigned long)
  79 #define local_flush_page_for_dma(page) BTFIXUP_CALL(local_flush_page_for_dma)(page)
  80 #endif
  81
  82 char *srmmu_name;
  83
  84 ctxd_t *srmmu_ctx_table_phys;
  85 static ctxd_t *srmmu_context_table;
  86
  87 int viking_mxcc_present;
  88 static DEFINE_SPINLOCK(srmmu_context_spinlock);
  89
  90 static int is_hypersparc;
  91
  92 /*
  93  * In general all page table modifications should use the V8 atomic
  94  * swap instruction.  This insures the mmu and the cpu are in sync
  95  * with respect to ref/mod bits in the page tables.
  96  */
  97 static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value)
  98 {
  99         __asm__ __volatile__("swap [%2], %0" : "=&r" (value) : "0" (value), "r" (addr));
 100         return value;
 101 }
 102
 103 static inline void srmmu_set_pte(pte_t *ptep, pte_t pteval)
 104 {
 105         srmmu_swap((unsigned long *)ptep, pte_val(pteval));
 106 }
 107
 108 /* The very generic SRMMU page table operations. */
 109 static inline int srmmu_device_memory(unsigned long x)
 110 {
 111         return ((x & 0xF0000000) != 0);
 112 }
 113
 114 static int srmmu_cache_pagetables;
 115
 116 /* these will be initialized in srmmu_nocache_calcsize() */
 117 static unsigned long srmmu_nocache_size;
 118 static unsigned long srmmu_nocache_end;
 119
 120 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
 121 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
 122
 123 /* The context table is a nocache user with the biggest alignment needs. */
 124 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
 125
 126 void *srmmu_nocache_pool;
 127 void *srmmu_nocache_bitmap;
 128 static struct bit_map srmmu_nocache_map;
 129
 130 static unsigned long srmmu_pte_pfn(pte_t pte)
 131 {
 132         if (srmmu_device_memory(pte_val(pte))) {
 133                 /* Just return something that will cause
 134                  * pfn_valid() to return false.  This makes
 135                  * copy_one_pte() to just directly copy to
 136                  * PTE over.
 137                  */
 138                 return ~0UL;
 139         }
 140         return (pte_val(pte) & SRMMU_PTE_PMASK) >> (PAGE_SHIFT-4);
 141 }
 142
 143 static struct page *srmmu_pmd_page(pmd_t pmd)
 144 {
 145
 146         if (srmmu_device_memory(pmd_val(pmd)))
 147                 BUG();
 148         return pfn_to_page((pmd_val(pmd) & SRMMU_PTD_PMASK) >> (PAGE_SHIFT-4));
 149 }
 150
 151 static inline unsigned long srmmu_pgd_page(pgd_t pgd)
 152 { return srmmu_device_memory(pgd_val(pgd))?~0:(unsigned long)__nocache_va((pgd_val(pgd) & SRMMU_PTD_PMASK) << 4); }
 153
 154
 155 static inline int srmmu_pte_none(pte_t pte)
 156 { return !(pte_val(pte) & 0xFFFFFFF); }
 157
 158 static inline int srmmu_pte_present(pte_t pte)
 159 { return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE); }
 160
 161 static inline void srmmu_pte_clear(pte_t *ptep)
 162 { srmmu_set_pte(ptep, __pte(0)); }
 163
 164 static inline int srmmu_pmd_none(pmd_t pmd)
 165 { return !(pmd_val(pmd) & 0xFFFFFFF); }
 166
 167 static inline int srmmu_pmd_bad(pmd_t pmd)
 168 { return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
 169
 170 static inline int srmmu_pmd_present(pmd_t pmd)
 171 { return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
 172
 173 static inline void srmmu_pmd_clear(pmd_t *pmdp) {
 174         int i;
 175         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++)
 176                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], __pte(0));
 177 }
 178
 179 static inline int srmmu_pgd_none(pgd_t pgd)
 180 { return !(pgd_val(pgd) & 0xFFFFFFF); }
 181
 182 static inline int srmmu_pgd_bad(pgd_t pgd)
 183 { return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
 184
 185 static inline int srmmu_pgd_present(pgd_t pgd)
 186 { return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
 187
 188 static inline void srmmu_pgd_clear(pgd_t * pgdp)
 189 { srmmu_set_pte((pte_t *)pgdp, __pte(0)); }
 190
 191 static inline pte_t srmmu_pte_wrprotect(pte_t pte)
 192 { return __pte(pte_val(pte) & ~SRMMU_WRITE);}
 193
 194 static inline pte_t srmmu_pte_mkclean(pte_t pte)
 195 { return __pte(pte_val(pte) & ~SRMMU_DIRTY);}
 196
 197 static inline pte_t srmmu_pte_mkold(pte_t pte)
 198 { return __pte(pte_val(pte) & ~SRMMU_REF);}
 199
 200 static inline pte_t srmmu_pte_mkwrite(pte_t pte)
 201 { return __pte(pte_val(pte) | SRMMU_WRITE);}
 202
 203 static inline pte_t srmmu_pte_mkdirty(pte_t pte)
 204 { return __pte(pte_val(pte) | SRMMU_DIRTY);}
 205
 206 static inline pte_t srmmu_pte_mkyoung(pte_t pte)
 207 { return __pte(pte_val(pte) | SRMMU_REF);}
 208
 209 /*
 210  * Conversion functions: convert a page and protection to a page entry,
 211  * and a page entry and page directory to the page they refer to.
 212  */
 213 static pte_t srmmu_mk_pte(struct page *page, pgprot_t pgprot)
 214 { return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) | pgprot_val(pgprot)); }
 215
 216 static pte_t srmmu_mk_pte_phys(unsigned long page, pgprot_t pgprot)
 217 { return __pte(((page) >> 4) | pgprot_val(pgprot)); }
 218
 219 static pte_t srmmu_mk_pte_io(unsigned long page, pgprot_t pgprot, int space)
 220 { return __pte(((page) >> 4) | (space << 28) | pgprot_val(pgprot)); }
 221
 222 /* XXX should we hyper_flush_whole_icache here - Anton */
 223 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
 224 { srmmu_set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); }
 225
 226 static inline void srmmu_pgd_set(pgd_t * pgdp, pmd_t * pmdp)
 227 { srmmu_set_pte((pte_t *)pgdp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pmdp) >> 4))); }
 228
 229 static void srmmu_pmd_set(pmd_t *pmdp, pte_t *ptep)
 230 {
 231         unsigned long ptp;      /* Physical address, shifted right by 4 */
 232         int i;
 233
 234         ptp = __nocache_pa((unsigned long) ptep) >> 4;
 235         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
 236                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
 237                 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
 238         }
 239 }
 240
 241 static void srmmu_pmd_populate(pmd_t *pmdp, struct page *ptep)
 242 {
 243         unsigned long ptp;      /* Physical address, shifted right by 4 */
 244         int i;
 245
 246         ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4);      /* watch for overflow */
 247         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
 248                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
 249                 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
 250         }
 251 }
 252
 253 static inline pte_t srmmu_pte_modify(pte_t pte, pgprot_t newprot)
 254 { return __pte((pte_val(pte) & SRMMU_CHG_MASK) | pgprot_val(newprot)); }
 255
 256 /* to find an entry in a top-level page table... */
 257 static inline pgd_t *srmmu_pgd_offset(struct mm_struct * mm, unsigned long address)
 258 { return mm->pgd + (address >> SRMMU_PGDIR_SHIFT); }
 259
 260 /* Find an entry in the second-level page table.. */
 261 static inline pmd_t *srmmu_pmd_offset(pgd_t * dir, unsigned long address)
 262 {
 263         return (pmd_t *) srmmu_pgd_page(*dir) +
 264             ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
 265 }
 266
 267 /* Find an entry in the third-level page table.. */
 268 static inline pte_t *srmmu_pte_offset(pmd_t * dir, unsigned long address)
 269 {
 270         void *pte;
 271
 272         pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4);
 273         return (pte_t *) pte +
 274             ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
 275 }
 276
 277 static unsigned long srmmu_swp_type(swp_entry_t entry)
 278 {
 279         return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK;
 280 }
 281
 282 static unsigned long srmmu_swp_offset(swp_entry_t entry)
 283 {
 284         return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK;
 285 }
 286
 287 static swp_entry_t srmmu_swp_entry(unsigned long type, unsigned long offset)
 288 {
 289         return (swp_entry_t) {
 290                   (type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT
 291                 | (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT };
 292 }
 293
 294 /*
 295  * size: bytes to allocate in the nocache area.
 296  * align: bytes, number to align at.
 297  * Returns the virtual address of the allocated area.
 298  */
 299 static unsigned long __srmmu_get_nocache(int size, int align)
 300 {
 301         int offset;
 302
 303         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
 304                 printk("Size 0x%x too small for nocache request\n", size);
 305                 size = SRMMU_NOCACHE_BITMAP_SHIFT;
 306         }
 307         if (size & (SRMMU_NOCACHE_BITMAP_SHIFT-1)) {
 308                 printk("Size 0x%x unaligned int nocache request\n", size);
 309                 size += SRMMU_NOCACHE_BITMAP_SHIFT-1;
 310         }
 311         BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
 312
 313         offset = bit_map_string_get(&srmmu_nocache_map,
 314                                         size >> SRMMU_NOCACHE_BITMAP_SHIFT,
 315                                         align >> SRMMU_NOCACHE_BITMAP_SHIFT);
 316         if (offset == -1) {
 317                 printk("srmmu: out of nocache %d: %d/%d\n",
 318                     size, (int) srmmu_nocache_size,
 319                     srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
 320                 return 0;
 321         }
 322
 323         return (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT));
 324 }
 325
 326 static unsigned long srmmu_get_nocache(int size, int align)
 327 {
 328         unsigned long tmp;
 329
 330         tmp = __srmmu_get_nocache(size, align);
 331
 332         if (tmp)
 333                 memset((void *)tmp, 0, size);
 334
 335         return tmp;
 336 }
 337
 338 static void srmmu_free_nocache(unsigned long vaddr, int size)
 339 {
 340         int offset;
 341
 342         if (vaddr < SRMMU_NOCACHE_VADDR) {
 343                 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
 344                     vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
 345                 BUG();
 346         }
 347         if (vaddr+size > srmmu_nocache_end) {
 348                 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
 349                     vaddr, srmmu_nocache_end);
 350                 BUG();
 351         }
 352         if (size & (size-1)) {
 353                 printk("Size 0x%x is not a power of 2\n", size);
 354                 BUG();
 355         }
 356         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
 357                 printk("Size 0x%x is too small\n", size);
 358                 BUG();
 359         }
 360         if (vaddr & (size-1)) {
 361                 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
 362                 BUG();
 363         }
 364
 365         offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
 366         size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 367
 368         bit_map_clear(&srmmu_nocache_map, offset, size);
 369 }
 370
 371 static void srmmu_early_allocate_ptable_skeleton(unsigned long start,
 372                                                  unsigned long end);
 373
 374 extern unsigned long probe_memory(void);        /* in fault.c */
 375
 376 /*
 377  * Reserve nocache dynamically proportionally to the amount of
 378  * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
 379  */
 380 static void srmmu_nocache_calcsize(void)
 381 {
 382         unsigned long sysmemavail = probe_memory() / 1024;
 383         int srmmu_nocache_npages;
 384
 385         srmmu_nocache_npages =
 386                 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
 387
 388  /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
 389         // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
 390         if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
 391                 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
 392
 393         /* anything above 1280 blows up */
 394         if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
 395                 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
 396
 397         srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
 398         srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
 399 }
 400
 401 static void __init srmmu_nocache_init(void)
 402 {
 403         unsigned int bitmap_bits;
 404         pgd_t *pgd;
 405         pmd_t *pmd;
 406         pte_t *pte;
 407         unsigned long paddr, vaddr;
 408         unsigned long pteval;
 409
 410         bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 411
 412         srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size,
 413                 SRMMU_NOCACHE_ALIGN_MAX, 0UL);
 414         memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
 415
 416         srmmu_nocache_bitmap = __alloc_bootmem(bitmap_bits >> 3, SMP_CACHE_BYTES, 0UL);
 417         bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
 418
 419         srmmu_swapper_pg_dir = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 420         memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
 421         init_mm.pgd = srmmu_swapper_pg_dir;
 422
 423         srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
 424
 425         paddr = __pa((unsigned long)srmmu_nocache_pool);
 426         vaddr = SRMMU_NOCACHE_VADDR;
 427
 428         while (vaddr < srmmu_nocache_end) {
 429                 pgd = pgd_offset_k(vaddr);
 430                 pmd = srmmu_pmd_offset(__nocache_fix(pgd), vaddr);
 431                 pte = srmmu_pte_offset(__nocache_fix(pmd), vaddr);
 432
 433                 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
 434
 435                 if (srmmu_cache_pagetables)
 436                         pteval |= SRMMU_CACHE;
 437
 438                 srmmu_set_pte(__nocache_fix(pte), __pte(pteval));
 439
 440                 vaddr += PAGE_SIZE;
 441                 paddr += PAGE_SIZE;
 442         }
 443
 444         flush_cache_all();
 445         flush_tlb_all();
 446 }
 447
 448 static inline pgd_t *srmmu_get_pgd_fast(void)
 449 {
 450         pgd_t *pgd = NULL;
 451
 452         pgd = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 453         if (pgd) {
 454                 pgd_t *init = pgd_offset_k(0);
 455                 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
 456                 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
 457                                                 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
 458         }
 459
 460         return pgd;
 461 }
 462
 463 static void srmmu_free_pgd_fast(pgd_t *pgd)
 464 {
 465         srmmu_free_nocache((unsigned long)pgd, SRMMU_PGD_TABLE_SIZE);
 466 }
 467
 468 static pmd_t *srmmu_pmd_alloc_one(struct mm_struct *mm, unsigned long address)
 469 {
 470         return (pmd_t *)srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
 471 }
 472
 473 static void srmmu_pmd_free(pmd_t * pmd)
 474 {
 475         srmmu_free_nocache((unsigned long)pmd, SRMMU_PMD_TABLE_SIZE);
 476 }
 477
 478 /*
 479  * Hardware needs alignment to 256 only, but we align to whole page size
 480  * to reduce fragmentation problems due to the buddy principle.
 481  * XXX Provide actual fragmentation statistics in /proc.
 482  *
 483  * Alignments up to the page size are the same for physical and virtual
 484  * addresses of the nocache area.
 485  */
 486 static pte_t *
 487 srmmu_pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
 488 {
 489         return (pte_t *)srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
 490 }
 491
 492 static pgtable_t
 493 srmmu_pte_alloc_one(struct mm_struct *mm, unsigned long address)
 494 {
 495         unsigned long pte;
 496         struct page *page;
 497
 498         if ((pte = (unsigned long)srmmu_pte_alloc_one_kernel(mm, address)) == 0)
 499                 return NULL;
 500         page = pfn_to_page( __nocache_pa(pte) >> PAGE_SHIFT );
 501         pgtable_page_ctor(page);
 502         return page;
 503 }
 504
 505 static void srmmu_free_pte_fast(pte_t *pte)
 506 {
 507         srmmu_free_nocache((unsigned long)pte, PTE_SIZE);
 508 }
 509
 510 static void srmmu_pte_free(pgtable_t pte)
 511 {
 512         unsigned long p;
 513
 514         pgtable_page_dtor(pte);
 515         p = (unsigned long)page_address(pte);   /* Cached address (for test) */
 516         if (p == 0)
 517                 BUG();
 518         p = page_to_pfn(pte) << PAGE_SHIFT;     /* Physical address */
 519         p = (unsigned long) __nocache_va(p);    /* Nocached virtual */
 520         srmmu_free_nocache(p, PTE_SIZE);
 521 }
 522
 523 /*
 524  */
 525 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
 526 {
 527         struct ctx_list *ctxp;
 528
 529         ctxp = ctx_free.next;
 530         if(ctxp != &ctx_free) {
 531                 remove_from_ctx_list(ctxp);
 532                 add_to_used_ctxlist(ctxp);
 533                 mm->context = ctxp->ctx_number;
 534                 ctxp->ctx_mm = mm;
 535                 return;
 536         }
 537         ctxp = ctx_used.next;
 538         if(ctxp->ctx_mm == old_mm)
 539                 ctxp = ctxp->next;
 540         if(ctxp == &ctx_used)
 541                 panic("out of mmu contexts");
 542         flush_cache_mm(ctxp->ctx_mm);
 543         flush_tlb_mm(ctxp->ctx_mm);
 544         remove_from_ctx_list(ctxp);
 545         add_to_used_ctxlist(ctxp);
 546         ctxp->ctx_mm->context = NO_CONTEXT;
 547         ctxp->ctx_mm = mm;
 548         mm->context = ctxp->ctx_number;
 549 }
 550
 551 static inline void free_context(int context)
 552 {
 553         struct ctx_list *ctx_old;
 554
 555         ctx_old = ctx_list_pool + context;
 556         remove_from_ctx_list(ctx_old);
 557         add_to_free_ctxlist(ctx_old);
 558 }
 559
 560
 561 static void srmmu_switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
 562     struct task_struct *tsk, int cpu)
 563 {
 564         if(mm->context == NO_CONTEXT) {
 565                 spin_lock(&srmmu_context_spinlock);
 566                 alloc_context(old_mm, mm);
 567                 spin_unlock(&srmmu_context_spinlock);
 568                 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
 569         }
 570
 571         if (is_hypersparc)
 572                 hyper_flush_whole_icache();
 573
 574         srmmu_set_context(mm->context);
 575 }
 576
 577 /* Low level IO area allocation on the SRMMU. */
 578 static inline void srmmu_mapioaddr(unsigned long physaddr,
 579     unsigned long virt_addr, int bus_type)
 580 {
 581         pgd_t *pgdp;
 582         pmd_t *pmdp;
 583         pte_t *ptep;
 584         unsigned long tmp;
 585
 586         physaddr &= PAGE_MASK;
 587         pgdp = pgd_offset_k(virt_addr);
 588         pmdp = srmmu_pmd_offset(pgdp, virt_addr);
 589         ptep = srmmu_pte_offset(pmdp, virt_addr);
 590         tmp = (physaddr >> 4) | SRMMU_ET_PTE;
 591
 592         /*
 593          * I need to test whether this is consistent over all
 594          * sun4m's.  The bus_type represents the upper 4 bits of
 595          * 36-bit physical address on the I/O space lines...
 596          */
 597         tmp |= (bus_type << 28);
 598         tmp |= SRMMU_PRIV;
 599         __flush_page_to_ram(virt_addr);
 600         srmmu_set_pte(ptep, __pte(tmp));
 601 }
 602
 603 static void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
 604     unsigned long xva, unsigned int len)
 605 {
 606         while (len != 0) {
 607                 len -= PAGE_SIZE;
 608                 srmmu_mapioaddr(xpa, xva, bus);
 609                 xva += PAGE_SIZE;
 610                 xpa += PAGE_SIZE;
 611         }
 612         flush_tlb_all();
 613 }
 614
 615 static inline void srmmu_unmapioaddr(unsigned long virt_addr)
 616 {
 617         pgd_t *pgdp;
 618         pmd_t *pmdp;
 619         pte_t *ptep;
 620
 621         pgdp = pgd_offset_k(virt_addr);
 622         pmdp = srmmu_pmd_offset(pgdp, virt_addr);
 623         ptep = srmmu_pte_offset(pmdp, virt_addr);
 624
 625         /* No need to flush uncacheable page. */
 626         srmmu_pte_clear(ptep);
 627 }
 628
 629 static void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
 630 {
 631         while (len != 0) {
 632                 len -= PAGE_SIZE;
 633                 srmmu_unmapioaddr(virt_addr);
 634                 virt_addr += PAGE_SIZE;
 635         }
 636         flush_tlb_all();
 637 }
 638
 639 /*
 640  * On the SRMMU we do not have the problems with limited tlb entries
 641  * for mapping kernel pages, so we just take things from the free page
 642  * pool.  As a side effect we are putting a little too much pressure
 643  * on the gfp() subsystem.  This setup also makes the logic of the
 644  * iommu mapping code a lot easier as we can transparently handle
 645  * mappings on the kernel stack without any special code as we did
 646  * need on the sun4c.
 647  */
 648 static struct thread_info *srmmu_alloc_thread_info(void)
 649 {
 650         struct thread_info *ret;
 651
 652         ret = (struct thread_info *)__get_free_pages(GFP_KERNEL,
 653                                                      THREAD_INFO_ORDER);
 654 #ifdef CONFIG_DEBUG_STACK_USAGE
 655         if (ret)
 656                 memset(ret, 0, PAGE_SIZE << THREAD_INFO_ORDER);
 657 #endif /* DEBUG_STACK_USAGE */
 658
 659         return ret;
 660 }
 661
 662 static void srmmu_free_thread_info(struct thread_info *ti)
 663 {
 664         free_pages((unsigned long)ti, THREAD_INFO_ORDER);
 665 }
 666
 667 /* tsunami.S */
 668 extern void tsunami_flush_cache_all(void);
 669 extern void tsunami_flush_cache_mm(struct mm_struct *mm);
 670 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 671 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 672 extern void tsunami_flush_page_to_ram(unsigned long page);
 673 extern void tsunami_flush_page_for_dma(unsigned long page);
 674 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 675 extern void tsunami_flush_tlb_all(void);
 676 extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
 677 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 678 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 679 extern void tsunami_setup_blockops(void);
 680
 681 /*
 682  * Workaround, until we find what's going on with Swift. When low on memory,
 683  * it sometimes loops in fault/handle_mm_fault incl. flush_tlb_page to find
 684  * out it is already in page tables/ fault again on the same instruction.
 685  * I really don't understand it, have checked it and contexts
 686  * are right, flush_tlb_all is done as well, and it faults again...
 687  * Strange. -jj
 688  *
 689  * The following code is a deadwood that may be necessary when
 690  * we start to make precise page flushes again. --zaitcev
 691  */
 692 static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
 693 {
 694 #if 0
 695         static unsigned long last;
 696         unsigned int val;
 697         /* unsigned int n; */
 698
 699         if (address == last) {
 700                 val = srmmu_hwprobe(address);
 701                 if (val != 0 && pte_val(pte) != val) {
 702                         printk("swift_update_mmu_cache: "
 703                             "addr %lx put %08x probed %08x from %p\n",
 704                             address, pte_val(pte), val,
 705                             __builtin_return_address(0));
 706                         srmmu_flush_whole_tlb();
 707                 }
 708         }
 709         last = address;
 710 #endif
 711 }
 712
 713 /* swift.S */
 714 extern void swift_flush_cache_all(void);
 715 extern void swift_flush_cache_mm(struct mm_struct *mm);
 716 extern void swift_flush_cache_range(struct vm_area_struct *vma,
 717                                     unsigned long start, unsigned long end);
 718 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 719 extern void swift_flush_page_to_ram(unsigned long page);
 720 extern void swift_flush_page_for_dma(unsigned long page);
 721 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 722 extern void swift_flush_tlb_all(void);
 723 extern void swift_flush_tlb_mm(struct mm_struct *mm);
 724 extern void swift_flush_tlb_range(struct vm_area_struct *vma,
 725                                   unsigned long start, unsigned long end);
 726 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 727
 728 #if 0  /* P3: deadwood to debug precise flushes on Swift. */
 729 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 730 {
 731         int cctx, ctx1;
 732
 733         page &= PAGE_MASK;
 734         if ((ctx1 = vma->vm_mm->context) != -1) {
 735                 cctx = srmmu_get_context();
 736 /* Is context # ever different from current context? P3 */
 737                 if (cctx != ctx1) {
 738                         printk("flush ctx %02x curr %02x\n", ctx1, cctx);
 739                         srmmu_set_context(ctx1);
 740                         swift_flush_page(page);
 741                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 742                                         "r" (page), "i" (ASI_M_FLUSH_PROBE));
 743                         srmmu_set_context(cctx);
 744                 } else {
 745                          /* Rm. prot. bits from virt. c. */
 746                         /* swift_flush_cache_all(); */
 747                         /* swift_flush_cache_page(vma, page); */
 748                         swift_flush_page(page);
 749
 750                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 751                                 "r" (page), "i" (ASI_M_FLUSH_PROBE));
 752                         /* same as above: srmmu_flush_tlb_page() */
 753                 }
 754         }
 755 }
 756 #endif
 757
 758 /*
 759  * The following are all MBUS based SRMMU modules, and therefore could
 760  * be found in a multiprocessor configuration.  On the whole, these
 761  * chips seems to be much more touchy about DVMA and page tables
 762  * with respect to cache coherency.
 763  */
 764
 765 /* Cypress flushes. */
 766 static void cypress_flush_cache_all(void)
 767 {
 768         volatile unsigned long cypress_sucks;
 769         unsigned long faddr, tagval;
 770
 771         flush_user_windows();
 772         for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
 773                 __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
 774                                      "=r" (tagval) :
 775                                      "r" (faddr), "r" (0x40000),
 776                                      "i" (ASI_M_DATAC_TAG));
 777
 778                 /* If modified and valid, kick it. */
 779                 if((tagval & 0x60) == 0x60)
 780                         cypress_sucks = *(unsigned long *)(0xf0020000 + faddr);
 781         }
 782 }
 783
 784 static void cypress_flush_cache_mm(struct mm_struct *mm)
 785 {
 786         register unsigned long a, b, c, d, e, f, g;
 787         unsigned long flags, faddr;
 788         int octx;
 789
 790         FLUSH_BEGIN(mm)
 791         flush_user_windows();
 792         local_irq_save(flags);
 793         octx = srmmu_get_context();
 794         srmmu_set_context(mm->context);
 795         a = 0x20; b = 0x40; c = 0x60;
 796         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 797
 798         faddr = (0x10000 - 0x100);
 799         goto inside;
 800         do {
 801                 faddr -= 0x100;
 802         inside:
 803                 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 804                                      "sta %%g0, [%0 + %2] %1\n\t"
 805                                      "sta %%g0, [%0 + %3] %1\n\t"
 806                                      "sta %%g0, [%0 + %4] %1\n\t"
 807                                      "sta %%g0, [%0 + %5] %1\n\t"
 808                                      "sta %%g0, [%0 + %6] %1\n\t"
 809                                      "sta %%g0, [%0 + %7] %1\n\t"
 810                                      "sta %%g0, [%0 + %8] %1\n\t" : :
 811                                      "r" (faddr), "i" (ASI_M_FLUSH_CTX),
 812                                      "r" (a), "r" (b), "r" (c), "r" (d),
 813                                      "r" (e), "r" (f), "r" (g));
 814         } while(faddr);
 815         srmmu_set_context(octx);
 816         local_irq_restore(flags);
 817         FLUSH_END
 818 }
 819
 820 static void cypress_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 821 {
 822         struct mm_struct *mm = vma->vm_mm;
 823         register unsigned long a, b, c, d, e, f, g;
 824         unsigned long flags, faddr;
 825         int octx;
 826
 827         FLUSH_BEGIN(mm)
 828         flush_user_windows();
 829         local_irq_save(flags);
 830         octx = srmmu_get_context();
 831         srmmu_set_context(mm->context);
 832         a = 0x20; b = 0x40; c = 0x60;
 833         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 834
 835         start &= SRMMU_REAL_PMD_MASK;
 836         while(start < end) {
 837                 faddr = (start + (0x10000 - 0x100));
 838                 goto inside;
 839                 do {
 840                         faddr -= 0x100;
 841                 inside:
 842                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 843                                              "sta %%g0, [%0 + %2] %1\n\t"
 844                                              "sta %%g0, [%0 + %3] %1\n\t"
 845                                              "sta %%g0, [%0 + %4] %1\n\t"
 846                                              "sta %%g0, [%0 + %5] %1\n\t"
 847                                              "sta %%g0, [%0 + %6] %1\n\t"
 848                                              "sta %%g0, [%0 + %7] %1\n\t"
 849                                              "sta %%g0, [%0 + %8] %1\n\t" : :
 850                                              "r" (faddr),
 851                                              "i" (ASI_M_FLUSH_SEG),
 852                                              "r" (a), "r" (b), "r" (c), "r" (d),
 853                                              "r" (e), "r" (f), "r" (g));
 854                 } while (faddr != start);
 855                 start += SRMMU_REAL_PMD_SIZE;
 856         }
 857         srmmu_set_context(octx);
 858         local_irq_restore(flags);
 859         FLUSH_END
 860 }
 861
 862 static void cypress_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
 863 {
 864         register unsigned long a, b, c, d, e, f, g;
 865         struct mm_struct *mm = vma->vm_mm;
 866         unsigned long flags, line;
 867         int octx;
 868
 869         FLUSH_BEGIN(mm)
 870         flush_user_windows();
 871         local_irq_save(flags);
 872         octx = srmmu_get_context();
 873         srmmu_set_context(mm->context);
 874         a = 0x20; b = 0x40; c = 0x60;
 875         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 876
 877         page &= PAGE_MASK;
 878         line = (page + PAGE_SIZE) - 0x100;
 879         goto inside;
 880         do {
 881                 line -= 0x100;
 882         inside:
 883                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 884                                              "sta %%g0, [%0 + %2] %1\n\t"
 885                                              "sta %%g0, [%0 + %3] %1\n\t"
 886                                              "sta %%g0, [%0 + %4] %1\n\t"
 887                                              "sta %%g0, [%0 + %5] %1\n\t"
 888                                              "sta %%g0, [%0 + %6] %1\n\t"
 889                                              "sta %%g0, [%0 + %7] %1\n\t"
 890                                              "sta %%g0, [%0 + %8] %1\n\t" : :
 891                                              "r" (line),
 892                                              "i" (ASI_M_FLUSH_PAGE),
 893                                              "r" (a), "r" (b), "r" (c), "r" (d),
 894                                              "r" (e), "r" (f), "r" (g));
 895         } while(line != page);
 896         srmmu_set_context(octx);
 897         local_irq_restore(flags);
 898         FLUSH_END
 899 }
 900
 901 /* Cypress is copy-back, at least that is how we configure it. */
 902 static void cypress_flush_page_to_ram(unsigned long page)
 903 {
 904         register unsigned long a, b, c, d, e, f, g;
 905         unsigned long line;
 906
 907         a = 0x20; b = 0x40; c = 0x60; d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 908         page &= PAGE_MASK;
 909         line = (page + PAGE_SIZE) - 0x100;
 910         goto inside;
 911         do {
 912                 line -= 0x100;
 913         inside:
 914                 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 915                                      "sta %%g0, [%0 + %2] %1\n\t"
 916                                      "sta %%g0, [%0 + %3] %1\n\t"
 917                                      "sta %%g0, [%0 + %4] %1\n\t"
 918                                      "sta %%g0, [%0 + %5] %1\n\t"
 919                                      "sta %%g0, [%0 + %6] %1\n\t"
 920                                      "sta %%g0, [%0 + %7] %1\n\t"
 921                                      "sta %%g0, [%0 + %8] %1\n\t" : :
 922                                      "r" (line),
 923                                      "i" (ASI_M_FLUSH_PAGE),
 924                                      "r" (a), "r" (b), "r" (c), "r" (d),
 925                                      "r" (e), "r" (f), "r" (g));
 926         } while(line != page);
 927 }
 928
 929 /* Cypress is also IO cache coherent. */
 930 static void cypress_flush_page_for_dma(unsigned long page)
 931 {
 932 }
 933
 934 /* Cypress has unified L2 VIPT, from which both instructions and data
 935  * are stored.  It does not have an onboard icache of any sort, therefore
 936  * no flush is necessary.
 937  */
 938 static void cypress_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
 939 {
 940 }
 941
 942 static void cypress_flush_tlb_all(void)
 943 {
 944         srmmu_flush_whole_tlb();
 945 }
 946
 947 static void cypress_flush_tlb_mm(struct mm_struct *mm)
 948 {
 949         FLUSH_BEGIN(mm)
 950         __asm__ __volatile__(
 951         "lda    [%0] %3, %%g5\n\t"
 952         "sta    %2, [%0] %3\n\t"
 953         "sta    %%g0, [%1] %4\n\t"
 954         "sta    %%g5, [%0] %3\n"
 955         : /* no outputs */
 956         : "r" (SRMMU_CTX_REG), "r" (0x300), "r" (mm->context),
 957           "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
 958         : "g5");
 959         FLUSH_END
 960 }
 961
 962 static void cypress_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 963 {
 964         struct mm_struct *mm = vma->vm_mm;
 965         unsigned long size;
 966
 967         FLUSH_BEGIN(mm)
 968         start &= SRMMU_PGDIR_MASK;
 969         size = SRMMU_PGDIR_ALIGN(end) - start;
 970         __asm__ __volatile__(
 971                 "lda    [%0] %5, %%g5\n\t"
 972                 "sta    %1, [%0] %5\n"
 973                 "1:\n\t"
 974                 "subcc  %3, %4, %3\n\t"
 975                 "bne    1b\n\t"
 976                 " sta   %%g0, [%2 + %3] %6\n\t"
 977                 "sta    %%g5, [%0] %5\n"
 978         : /* no outputs */
 979         : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (start | 0x200),
 980           "r" (size), "r" (SRMMU_PGDIR_SIZE), "i" (ASI_M_MMUREGS),
 981           "i" (ASI_M_FLUSH_PROBE)
 982         : "g5", "cc");
 983         FLUSH_END
 984 }
 985
 986 static void cypress_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 987 {
 988         struct mm_struct *mm = vma->vm_mm;
 989
 990         FLUSH_BEGIN(mm)
 991         __asm__ __volatile__(
 992         "lda    [%0] %3, %%g5\n\t"
 993         "sta    %1, [%0] %3\n\t"
 994         "sta    %%g0, [%2] %4\n\t"
 995         "sta    %%g5, [%0] %3\n"
 996         : /* no outputs */
 997         : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (page & PAGE_MASK),
 998           "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
 999         : "g5");
1000         FLUSH_END
1001 }
1002
1003 /* viking.S */
1004 extern void viking_flush_cache_all(void);
1005 extern void viking_flush_cache_mm(struct mm_struct *mm);
1006 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
1007                                      unsigned long end);
1008 extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
1009 extern void viking_flush_page_to_ram(unsigned long page);
1010 extern void viking_flush_page_for_dma(unsigned long page);
1011 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
1012 extern void viking_flush_page(unsigned long page);
1013 extern void viking_mxcc_flush_page(unsigned long page);
1014 extern void viking_flush_tlb_all(void);
1015 extern void viking_flush_tlb_mm(struct mm_struct *mm);
1016 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
1017                                    unsigned long end);
1018 extern void viking_flush_tlb_page(struct vm_area_struct *vma,
1019                                   unsigned long page);
1020 extern void sun4dsmp_flush_tlb_all(void);
1021 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
1022 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
1023                                    unsigned long end);
1024 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
1025                                   unsigned long page);
1026
1027 /* hypersparc.S */
1028 extern void hypersparc_flush_cache_all(void);
1029 extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
1030 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
1031 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
1032 extern void hypersparc_flush_page_to_ram(unsigned long page);
1033 extern void hypersparc_flush_page_for_dma(unsigned long page);
1034 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
1035 extern void hypersparc_flush_tlb_all(void);
1036 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
1037 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
1038 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
1039 extern void hypersparc_setup_blockops(void);
1040
1041 /*
1042  * NOTE: All of this startup code assumes the low 16mb (approx.) of
1043  *       kernel mappings are done with one single contiguous chunk of
1044  *       ram.  On small ram machines (classics mainly) we only get
1045  *       around 8mb mapped for us.
1046  */
1047
1048 static void __init early_pgtable_allocfail(char *type)
1049 {
1050         prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
1051         prom_halt();
1052 }
1053
1054 static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
1055                                                         unsigned long end)
1056 {
1057         pgd_t *pgdp;
1058         pmd_t *pmdp;
1059         pte_t *ptep;
1060
1061         while(start < end) {
1062                 pgdp = pgd_offset_k(start);
1063                 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1064                         pmdp = (pmd_t *) __srmmu_get_nocache(
1065                             SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1066                         if (pmdp == NULL)
1067                                 early_pgtable_allocfail("pmd");
1068                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1069                         srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1070                 }
1071                 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1072                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1073                         ptep = (pte_t *)__srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
1074                         if (ptep == NULL)
1075                                 early_pgtable_allocfail("pte");
1076                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
1077                         srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1078                 }
1079                 if (start > (0xffffffffUL - PMD_SIZE))
1080                         break;
1081                 start = (start + PMD_SIZE) & PMD_MASK;
1082         }
1083 }
1084
1085 static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
1086                                                   unsigned long end)
1087 {
1088         pgd_t *pgdp;
1089         pmd_t *pmdp;
1090         pte_t *ptep;
1091
1092         while(start < end) {
1093                 pgdp = pgd_offset_k(start);
1094                 if(srmmu_pgd_none(*pgdp)) {
1095                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1096                         if (pmdp == NULL)
1097                                 early_pgtable_allocfail("pmd");
1098                         memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
1099                         srmmu_pgd_set(pgdp, pmdp);
1100                 }
1101                 pmdp = srmmu_pmd_offset(pgdp, start);
1102                 if(srmmu_pmd_none(*pmdp)) {
1103                         ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1104                                                              PTE_SIZE);
1105                         if (ptep == NULL)
1106                                 early_pgtable_allocfail("pte");
1107                         memset(ptep, 0, PTE_SIZE);
1108                         srmmu_pmd_set(pmdp, ptep);
1109                 }
1110                 if (start > (0xffffffffUL - PMD_SIZE))
1111                         break;
1112                 start = (start + PMD_SIZE) & PMD_MASK;
1113         }
1114 }
1115
1116 /*
1117  * This is much cleaner than poking around physical address space
1118  * looking at the prom's page table directly which is what most
1119  * other OS's do.  Yuck... this is much better.
1120  */
1121 static void __init srmmu_inherit_prom_mappings(unsigned long start,
1122                                                unsigned long end)
1123 {
1124         pgd_t *pgdp;
1125         pmd_t *pmdp;
1126         pte_t *ptep;
1127         int what = 0; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
1128         unsigned long prompte;
1129
1130         while(start <= end) {
1131                 if (start == 0)
1132                         break; /* probably wrap around */
1133                 if(start == 0xfef00000)
1134                         start = KADB_DEBUGGER_BEGVM;
1135                 if(!(prompte = srmmu_hwprobe(start))) {
1136                         start += PAGE_SIZE;
1137                         continue;
1138                 }
1139
1140                 /* A red snapper, see what it really is. */
1141                 what = 0;
1142
1143                 if(!(start & ~(SRMMU_REAL_PMD_MASK))) {
1144                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_REAL_PMD_SIZE) == prompte)
1145                                 what = 1;
1146                 }
1147
1148                 if(!(start & ~(SRMMU_PGDIR_MASK))) {
1149                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_PGDIR_SIZE) ==
1150                            prompte)
1151                                 what = 2;
1152                 }
1153
1154                 pgdp = pgd_offset_k(start);
1155                 if(what == 2) {
1156                         *(pgd_t *)__nocache_fix(pgdp) = __pgd(prompte);
1157                         start += SRMMU_PGDIR_SIZE;
1158                         continue;
1159                 }
1160                 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1161                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1162                         if (pmdp == NULL)
1163                                 early_pgtable_allocfail("pmd");
1164                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1165                         srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1166                 }
1167                 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1168                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1169                         ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1170                                                              PTE_SIZE);
1171                         if (ptep == NULL)
1172                                 early_pgtable_allocfail("pte");
1173                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
1174                         srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1175                 }
1176                 if(what == 1) {
1177                         /*
1178                          * We bend the rule where all 16 PTPs in a pmd_t point
1179                          * inside the same PTE page, and we leak a perfectly
1180                          * good hardware PTE piece. Alternatives seem worse.
1181                          */
1182                         unsigned int x; /* Index of HW PMD in soft cluster */
1183                         x = (start >> PMD_SHIFT) & 15;
1184                         *(unsigned long *)__nocache_fix(&pmdp->pmdv[x]) = prompte;
1185                         start += SRMMU_REAL_PMD_SIZE;
1186                         continue;
1187                 }
1188                 ptep = srmmu_pte_offset(__nocache_fix(pmdp), start);
1189                 *(pte_t *)__nocache_fix(ptep) = __pte(prompte);
1190                 start += PAGE_SIZE;
1191         }
1192 }
1193
1194 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
1195
1196 /* Create a third-level SRMMU 16MB page mapping. */
1197 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
1198 {
1199         pgd_t *pgdp = pgd_offset_k(vaddr);
1200         unsigned long big_pte;
1201
1202         big_pte = KERNEL_PTE(phys_base >> 4);
1203         *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
1204 }
1205
1206 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
1207 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
1208 {
1209         unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK);
1210         unsigned long vstart = (vbase & SRMMU_PGDIR_MASK);
1211         unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
1212         /* Map "low" memory only */
1213         const unsigned long min_vaddr = PAGE_OFFSET;
1214         const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
1215
1216         if (vstart < min_vaddr || vstart >= max_vaddr)
1217                 return vstart;
1218
1219         if (vend > max_vaddr || vend < min_vaddr)
1220                 vend = max_vaddr;
1221
1222         while(vstart < vend) {
1223                 do_large_mapping(vstart, pstart);
1224                 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE;
1225         }
1226         return vstart;
1227 }
1228
1229 static inline void memprobe_error(char *msg)
1230 {
1231         prom_printf(msg);
1232         prom_printf("Halting now...\n");
1233         prom_halt();
1234 }
1235
1236 static inline void map_kernel(void)
1237 {
1238         int i;
1239
1240         if (phys_base > 0) {
1241                 do_large_mapping(PAGE_OFFSET, phys_base);
1242         }
1243
1244         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1245                 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
1246         }
1247
1248         BTFIXUPSET_SIMM13(user_ptrs_per_pgd, PAGE_OFFSET / SRMMU_PGDIR_SIZE);
1249 }
1250
1251 /* Paging initialization on the Sparc Reference MMU. */
1252 extern void sparc_context_init(int);
1253
1254 void (*poke_srmmu)(void) __cpuinitdata = NULL;
1255
1256 extern unsigned long bootmem_init(unsigned long *pages_avail);
1257
1258 void __init srmmu_paging_init(void)
1259 {
1260         int i, cpunode;
1261         char node_str[128];
1262         pgd_t *pgd;
1263         pmd_t *pmd;
1264         pte_t *pte;
1265         unsigned long pages_avail;
1266
1267         sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
1268
1269         if (sparc_cpu_model == sun4d)
1270                 num_contexts = 65536; /* We know it is Viking */
1271         else {
1272                 /* Find the number of contexts on the srmmu. */
1273                 cpunode = prom_getchild(prom_root_node);
1274                 num_contexts = 0;
1275                 while(cpunode != 0) {
1276                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1277                         if(!strcmp(node_str, "cpu")) {
1278                                 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
1279                                 break;
1280                         }
1281                         cpunode = prom_getsibling(cpunode);
1282                 }
1283         }
1284
1285         if(!num_contexts) {
1286                 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
1287                 prom_halt();
1288         }
1289
1290         pages_avail = 0;
1291         last_valid_pfn = bootmem_init(&pages_avail);
1292
1293         srmmu_nocache_calcsize();
1294         srmmu_nocache_init();
1295         srmmu_inherit_prom_mappings(0xfe400000,(LINUX_OPPROM_ENDVM-PAGE_SIZE));
1296         map_kernel();
1297
1298         /* ctx table has to be physically aligned to its size */
1299         srmmu_context_table = (ctxd_t *)__srmmu_get_nocache(num_contexts*sizeof(ctxd_t), num_contexts*sizeof(ctxd_t));
1300         srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa((unsigned long)srmmu_context_table);
1301
1302         for(i = 0; i < num_contexts; i++)
1303                 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
1304
1305         flush_cache_all();
1306         srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
1307 #ifdef CONFIG_SMP
1308         /* Stop from hanging here... */
1309         local_flush_tlb_all();
1310 #else
1311         flush_tlb_all();
1312 #endif
1313         poke_srmmu();
1314
1315         srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
1316         srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
1317
1318         srmmu_allocate_ptable_skeleton(
1319                 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
1320         srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
1321
1322         pgd = pgd_offset_k(PKMAP_BASE);
1323         pmd = srmmu_pmd_offset(pgd, PKMAP_BASE);
1324         pte = srmmu_pte_offset(pmd, PKMAP_BASE);
1325         pkmap_page_table = pte;
1326
1327         flush_cache_all();
1328         flush_tlb_all();
1329
1330         sparc_context_init(num_contexts);
1331
1332         kmap_init();
1333
1334         {
1335                 unsigned long zones_size[MAX_NR_ZONES];
1336                 unsigned long zholes_size[MAX_NR_ZONES];
1337                 unsigned long npages;
1338                 int znum;
1339
1340                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1341                         zones_size[znum] = zholes_size[znum] = 0;
1342
1343                 npages = max_low_pfn - pfn_base;
1344
1345                 zones_size[ZONE_DMA] = npages;
1346                 zholes_size[ZONE_DMA] = npages - pages_avail;
1347
1348                 npages = highend_pfn - max_low_pfn;
1349                 zones_size[ZONE_HIGHMEM] = npages;
1350                 zholes_size[ZONE_HIGHMEM] = npages - calc_highpages();
1351
1352                 free_area_init_node(0, zones_size, pfn_base, zholes_size);
1353         }
1354 }
1355
1356 static void srmmu_mmu_info(struct seq_file *m)
1357 {
1358         seq_printf(m,
1359                    "MMU type\t: %s\n"
1360                    "contexts\t: %d\n"
1361                    "nocache total\t: %ld\n"
1362                    "nocache used\t: %d\n",
1363                    srmmu_name,
1364                    num_contexts,
1365                    srmmu_nocache_size,
1366                    srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
1367 }
1368
1369 static void srmmu_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
1370 {
1371 }
1372
1373 static void srmmu_destroy_context(struct mm_struct *mm)
1374 {
1375
1376         if(mm->context != NO_CONTEXT) {
1377                 flush_cache_mm(mm);
1378                 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
1379                 flush_tlb_mm(mm);
1380                 spin_lock(&srmmu_context_spinlock);
1381                 free_context(mm->context);
1382                 spin_unlock(&srmmu_context_spinlock);
1383                 mm->context = NO_CONTEXT;
1384         }
1385 }
1386
1387 /* Init various srmmu chip types. */
1388 static void __init srmmu_is_bad(void)
1389 {
1390         prom_printf("Could not determine SRMMU chip type.\n");
1391         prom_halt();
1392 }
1393
1394 static void __init init_vac_layout(void)
1395 {
1396         int nd, cache_lines;
1397         char node_str[128];
1398 #ifdef CONFIG_SMP
1399         int cpu = 0;
1400         unsigned long max_size = 0;
1401         unsigned long min_line_size = 0x10000000;
1402 #endif
1403
1404         nd = prom_getchild(prom_root_node);
1405         while((nd = prom_getsibling(nd)) != 0) {
1406                 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1407                 if(!strcmp(node_str, "cpu")) {
1408                         vac_line_size = prom_getint(nd, "cache-line-size");
1409                         if (vac_line_size == -1) {
1410                                 prom_printf("can't determine cache-line-size, "
1411                                             "halting.\n");
1412                                 prom_halt();
1413                         }
1414                         cache_lines = prom_getint(nd, "cache-nlines");
1415                         if (cache_lines == -1) {
1416                                 prom_printf("can't determine cache-nlines, halting.\n");
1417                                 prom_halt();
1418                         }
1419
1420                         vac_cache_size = cache_lines * vac_line_size;
1421 #ifdef CONFIG_SMP
1422                         if(vac_cache_size > max_size)
1423                                 max_size = vac_cache_size;
1424                         if(vac_line_size < min_line_size)
1425                                 min_line_size = vac_line_size;
1426                         //FIXME: cpus not contiguous!!
1427                         cpu++;
1428                         if (cpu >= NR_CPUS || !cpu_online(cpu))
1429                                 break;
1430 #else
1431                         break;
1432 #endif
1433                 }
1434         }
1435         if(nd == 0) {
1436                 prom_printf("No CPU nodes found, halting.\n");
1437                 prom_halt();
1438         }
1439 #ifdef CONFIG_SMP
1440         vac_cache_size = max_size;
1441         vac_line_size = min_line_size;
1442 #endif
1443         printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1444                (int)vac_cache_size, (int)vac_line_size);
1445 }
1446
1447 static void __cpuinit poke_hypersparc(void)
1448 {
1449         volatile unsigned long clear;
1450         unsigned long mreg = srmmu_get_mmureg();
1451
1452         hyper_flush_unconditional_combined();
1453
1454         mreg &= ~(HYPERSPARC_CWENABLE);
1455         mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1456         mreg |= (HYPERSPARC_CMODE);
1457
1458         srmmu_set_mmureg(mreg);
1459
1460 #if 0 /* XXX I think this is bad news... -DaveM */
1461         hyper_clear_all_tags();
1462 #endif
1463
1464         put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1465         hyper_flush_whole_icache();
1466         clear = srmmu_get_faddr();
1467         clear = srmmu_get_fstatus();
1468 }
1469
1470 static void __init init_hypersparc(void)
1471 {
1472         srmmu_name = "ROSS HyperSparc";
1473         srmmu_modtype = HyperSparc;
1474
1475         init_vac_layout();
1476
1477         is_hypersparc = 1;
1478
1479         BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1480         BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1481         BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1482         BTFIXUPSET_CALL(flush_cache_all, hypersparc_flush_cache_all, BTFIXUPCALL_NORM);
1483         BTFIXUPSET_CALL(flush_cache_mm, hypersparc_flush_cache_mm, BTFIXUPCALL_NORM);
1484         BTFIXUPSET_CALL(flush_cache_range, hypersparc_flush_cache_range, BTFIXUPCALL_NORM);
1485         BTFIXUPSET_CALL(flush_cache_page, hypersparc_flush_cache_page, BTFIXUPCALL_NORM);
1486
1487         BTFIXUPSET_CALL(flush_tlb_all, hypersparc_flush_tlb_all, BTFIXUPCALL_NORM);
1488         BTFIXUPSET_CALL(flush_tlb_mm, hypersparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1489         BTFIXUPSET_CALL(flush_tlb_range, hypersparc_flush_tlb_range, BTFIXUPCALL_NORM);
1490         BTFIXUPSET_CALL(flush_tlb_page, hypersparc_flush_tlb_page, BTFIXUPCALL_NORM);
1491
1492         BTFIXUPSET_CALL(__flush_page_to_ram, hypersparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1493         BTFIXUPSET_CALL(flush_sig_insns, hypersparc_flush_sig_insns, BTFIXUPCALL_NORM);
1494         BTFIXUPSET_CALL(flush_page_for_dma, hypersparc_flush_page_for_dma, BTFIXUPCALL_NOP);
1495
1496
1497         poke_srmmu = poke_hypersparc;
1498
1499         hypersparc_setup_blockops();
1500 }
1501
1502 static void __cpuinit poke_cypress(void)
1503 {
1504         unsigned long mreg = srmmu_get_mmureg();
1505         unsigned long faddr, tagval;
1506         volatile unsigned long cypress_sucks;
1507         volatile unsigned long clear;
1508
1509         clear = srmmu_get_faddr();
1510         clear = srmmu_get_fstatus();
1511
1512         if (!(mreg & CYPRESS_CENABLE)) {
1513                 for(faddr = 0x0; faddr < 0x10000; faddr += 20) {
1514                         __asm__ __volatile__("sta %%g0, [%0 + %1] %2\n\t"
1515                                              "sta %%g0, [%0] %2\n\t" : :
1516                                              "r" (faddr), "r" (0x40000),
1517                                              "i" (ASI_M_DATAC_TAG));
1518                 }
1519         } else {
1520                 for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
1521                         __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
1522                                              "=r" (tagval) :
1523                                              "r" (faddr), "r" (0x40000),
1524                                              "i" (ASI_M_DATAC_TAG));
1525
1526                         /* If modified and valid, kick it. */
1527                         if((tagval & 0x60) == 0x60)
1528                                 cypress_sucks = *(unsigned long *)
1529                                                         (0xf0020000 + faddr);
1530                 }
1531         }
1532
1533         /* And one more, for our good neighbor, Mr. Broken Cypress. */
1534         clear = srmmu_get_faddr();
1535         clear = srmmu_get_fstatus();
1536
1537         mreg |= (CYPRESS_CENABLE | CYPRESS_CMODE);
1538         srmmu_set_mmureg(mreg);
1539 }
1540
1541 static void __init init_cypress_common(void)
1542 {
1543         init_vac_layout();
1544
1545         BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1546         BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1547         BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1548         BTFIXUPSET_CALL(flush_cache_all, cypress_flush_cache_all, BTFIXUPCALL_NORM);
1549         BTFIXUPSET_CALL(flush_cache_mm, cypress_flush_cache_mm, BTFIXUPCALL_NORM);
1550         BTFIXUPSET_CALL(flush_cache_range, cypress_flush_cache_range, BTFIXUPCALL_NORM);
1551         BTFIXUPSET_CALL(flush_cache_page, cypress_flush_cache_page, BTFIXUPCALL_NORM);
1552
1553         BTFIXUPSET_CALL(flush_tlb_all, cypress_flush_tlb_all, BTFIXUPCALL_NORM);
1554         BTFIXUPSET_CALL(flush_tlb_mm, cypress_flush_tlb_mm, BTFIXUPCALL_NORM);
1555         BTFIXUPSET_CALL(flush_tlb_page, cypress_flush_tlb_page, BTFIXUPCALL_NORM);
1556         BTFIXUPSET_CALL(flush_tlb_range, cypress_flush_tlb_range, BTFIXUPCALL_NORM);
1557
1558
1559         BTFIXUPSET_CALL(__flush_page_to_ram, cypress_flush_page_to_ram, BTFIXUPCALL_NORM);
1560         BTFIXUPSET_CALL(flush_sig_insns, cypress_flush_sig_insns, BTFIXUPCALL_NOP);
1561         BTFIXUPSET_CALL(flush_page_for_dma, cypress_flush_page_for_dma, BTFIXUPCALL_NOP);
1562
1563         poke_srmmu = poke_cypress;
1564 }
1565
1566 static void __init init_cypress_604(void)
1567 {
1568         srmmu_name = "ROSS Cypress-604(UP)";
1569         srmmu_modtype = Cypress;
1570         init_cypress_common();
1571 }
1572
1573 static void __init init_cypress_605(unsigned long mrev)
1574 {
1575         srmmu_name = "ROSS Cypress-605(MP)";
1576         if(mrev == 0xe) {
1577                 srmmu_modtype = Cypress_vE;
1578                 hwbug_bitmask |= HWBUG_COPYBACK_BROKEN;
1579         } else {
1580                 if(mrev == 0xd) {
1581                         srmmu_modtype = Cypress_vD;
1582                         hwbug_bitmask |= HWBUG_ASIFLUSH_BROKEN;
1583                 } else {
1584                         srmmu_modtype = Cypress;
1585                 }
1586         }
1587         init_cypress_common();
1588 }
1589
1590 static void __cpuinit poke_swift(void)
1591 {
1592         unsigned long mreg;
1593
1594         /* Clear any crap from the cache or else... */
1595         swift_flush_cache_all();
1596
1597         /* Enable I & D caches */
1598         mreg = srmmu_get_mmureg();
1599         mreg |= (SWIFT_IE | SWIFT_DE);
1600         /*
1601          * The Swift branch folding logic is completely broken.  At
1602          * trap time, if things are just right, if can mistakenly
1603          * think that a trap is coming from kernel mode when in fact
1604          * it is coming from user mode (it mis-executes the branch in
1605          * the trap code).  So you see things like crashme completely
1606          * hosing your machine which is completely unacceptable.  Turn
1607          * this shit off... nice job Fujitsu.
1608          */
1609         mreg &= ~(SWIFT_BF);
1610         srmmu_set_mmureg(mreg);
1611 }
1612
1613 #define SWIFT_MASKID_ADDR  0x10003018
1614 static void __init init_swift(void)
1615 {
1616         unsigned long swift_rev;
1617
1618         __asm__ __volatile__("lda [%1] %2, %0\n\t"
1619                              "srl %0, 0x18, %0\n\t" :
1620                              "=r" (swift_rev) :
1621                              "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1622         srmmu_name = "Fujitsu Swift";
1623         switch(swift_rev) {
1624         case 0x11:
1625         case 0x20:
1626         case 0x23:
1627         case 0x30:
1628                 srmmu_modtype = Swift_lots_o_bugs;
1629                 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1630                 /*
1631                  * Gee george, I wonder why Sun is so hush hush about
1632                  * this hardware bug... really braindamage stuff going
1633                  * on here.  However I think we can find a way to avoid
1634                  * all of the workaround overhead under Linux.  Basically,
1635                  * any page fault can cause kernel pages to become user
1636                  * accessible (the mmu gets confused and clears some of
1637                  * the ACC bits in kernel ptes).  Aha, sounds pretty
1638                  * horrible eh?  But wait, after extensive testing it appears
1639                  * that if you use pgd_t level large kernel pte's (like the
1640                  * 4MB pages on the Pentium) the bug does not get tripped
1641                  * at all.  This avoids almost all of the major overhead.
1642                  * Welcome to a world where your vendor tells you to,
1643                  * "apply this kernel patch" instead of "sorry for the
1644                  * broken hardware, send it back and we'll give you
1645                  * properly functioning parts"
1646                  */
1647                 break;
1648         case 0x25:
1649         case 0x31:
1650                 srmmu_modtype = Swift_bad_c;
1651                 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1652                 /*
1653                  * You see Sun allude to this hardware bug but never
1654                  * admit things directly, they'll say things like,
1655                  * "the Swift chip cache problems" or similar.
1656                  */
1657                 break;
1658         default:
1659                 srmmu_modtype = Swift_ok;
1660                 break;
1661         };
1662
1663         BTFIXUPSET_CALL(flush_cache_all, swift_flush_cache_all, BTFIXUPCALL_NORM);
1664         BTFIXUPSET_CALL(flush_cache_mm, swift_flush_cache_mm, BTFIXUPCALL_NORM);
1665         BTFIXUPSET_CALL(flush_cache_page, swift_flush_cache_page, BTFIXUPCALL_NORM);
1666         BTFIXUPSET_CALL(flush_cache_range, swift_flush_cache_range, BTFIXUPCALL_NORM);
1667
1668
1669         BTFIXUPSET_CALL(flush_tlb_all, swift_flush_tlb_all, BTFIXUPCALL_NORM);
1670         BTFIXUPSET_CALL(flush_tlb_mm, swift_flush_tlb_mm, BTFIXUPCALL_NORM);
1671         BTFIXUPSET_CALL(flush_tlb_page, swift_flush_tlb_page, BTFIXUPCALL_NORM);
1672         BTFIXUPSET_CALL(flush_tlb_range, swift_flush_tlb_range, BTFIXUPCALL_NORM);
1673
1674         BTFIXUPSET_CALL(__flush_page_to_ram, swift_flush_page_to_ram, BTFIXUPCALL_NORM);
1675         BTFIXUPSET_CALL(flush_sig_insns, swift_flush_sig_insns, BTFIXUPCALL_NORM);
1676         BTFIXUPSET_CALL(flush_page_for_dma, swift_flush_page_for_dma, BTFIXUPCALL_NORM);
1677
1678         BTFIXUPSET_CALL(update_mmu_cache, swift_update_mmu_cache, BTFIXUPCALL_NORM);
1679
1680         flush_page_for_dma_global = 0;
1681
1682         /*
1683          * Are you now convinced that the Swift is one of the
1684          * biggest VLSI abortions of all time?  Bravo Fujitsu!
1685          * Fujitsu, the !#?!%$'d up processor people.  I bet if
1686          * you examined the microcode of the Swift you'd find
1687          * XXX's all over the place.
1688          */
1689         poke_srmmu = poke_swift;
1690 }
1691
1692 static void turbosparc_flush_cache_all(void)
1693 {
1694         flush_user_windows();
1695         turbosparc_idflash_clear();
1696 }
1697
1698 static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1699 {
1700         FLUSH_BEGIN(mm)
1701         flush_user_windows();
1702         turbosparc_idflash_clear();
1703         FLUSH_END
1704 }
1705
1706 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1707 {
1708         FLUSH_BEGIN(vma->vm_mm)
1709         flush_user_windows();
1710         turbosparc_idflash_clear();
1711         FLUSH_END
1712 }
1713
1714 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1715 {
1716         FLUSH_BEGIN(vma->vm_mm)
1717         flush_user_windows();
1718         if (vma->vm_flags & VM_EXEC)
1719                 turbosparc_flush_icache();
1720         turbosparc_flush_dcache();
1721         FLUSH_END
1722 }
1723
1724 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
1725 static void turbosparc_flush_page_to_ram(unsigned long page)
1726 {
1727 #ifdef TURBOSPARC_WRITEBACK
1728         volatile unsigned long clear;
1729
1730         if (srmmu_hwprobe(page))
1731                 turbosparc_flush_page_cache(page);
1732         clear = srmmu_get_fstatus();
1733 #endif
1734 }
1735
1736 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1737 {
1738 }
1739
1740 static void turbosparc_flush_page_for_dma(unsigned long page)
1741 {
1742         turbosparc_flush_dcache();
1743 }
1744
1745 static void turbosparc_flush_tlb_all(void)
1746 {
1747         srmmu_flush_whole_tlb();
1748 }
1749
1750 static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1751 {
1752         FLUSH_BEGIN(mm)
1753         srmmu_flush_whole_tlb();
1754         FLUSH_END
1755 }
1756
1757 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1758 {
1759         FLUSH_BEGIN(vma->vm_mm)
1760         srmmu_flush_whole_tlb();
1761         FLUSH_END
1762 }
1763
1764 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1765 {
1766         FLUSH_BEGIN(vma->vm_mm)
1767         srmmu_flush_whole_tlb();
1768         FLUSH_END
1769 }
1770
1771
1772 static void __cpuinit poke_turbosparc(void)
1773 {
1774         unsigned long mreg = srmmu_get_mmureg();
1775         unsigned long ccreg;
1776
1777         /* Clear any crap from the cache or else... */
1778         turbosparc_flush_cache_all();
1779         mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* Temporarily disable I & D caches */
1780         mreg &= ~(TURBOSPARC_PCENABLE);         /* Don't check parity */
1781         srmmu_set_mmureg(mreg);
1782
1783         ccreg = turbosparc_get_ccreg();
1784
1785 #ifdef TURBOSPARC_WRITEBACK
1786         ccreg |= (TURBOSPARC_SNENABLE);         /* Do DVMA snooping in Dcache */
1787         ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1788                         /* Write-back D-cache, emulate VLSI
1789                          * abortion number three, not number one */
1790 #else
1791         /* For now let's play safe, optimize later */
1792         ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1793                         /* Do DVMA snooping in Dcache, Write-thru D-cache */
1794         ccreg &= ~(TURBOSPARC_uS2);
1795                         /* Emulate VLSI abortion number three, not number one */
1796 #endif
1797
1798         switch (ccreg & 7) {
1799         case 0: /* No SE cache */
1800         case 7: /* Test mode */
1801                 break;
1802         default:
1803                 ccreg |= (TURBOSPARC_SCENABLE);
1804         }
1805         turbosparc_set_ccreg (ccreg);
1806
1807         mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1808         mreg |= (TURBOSPARC_ICSNOOP);           /* Icache snooping on */
1809         srmmu_set_mmureg(mreg);
1810 }
1811
1812 static void __init init_turbosparc(void)
1813 {
1814         srmmu_name = "Fujitsu TurboSparc";
1815         srmmu_modtype = TurboSparc;
1816
1817         BTFIXUPSET_CALL(flush_cache_all, turbosparc_flush_cache_all, BTFIXUPCALL_NORM);
1818         BTFIXUPSET_CALL(flush_cache_mm, turbosparc_flush_cache_mm, BTFIXUPCALL_NORM);
1819         BTFIXUPSET_CALL(flush_cache_page, turbosparc_flush_cache_page, BTFIXUPCALL_NORM);
1820         BTFIXUPSET_CALL(flush_cache_range, turbosparc_flush_cache_range, BTFIXUPCALL_NORM);
1821
1822         BTFIXUPSET_CALL(flush_tlb_all, turbosparc_flush_tlb_all, BTFIXUPCALL_NORM);
1823         BTFIXUPSET_CALL(flush_tlb_mm, turbosparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1824         BTFIXUPSET_CALL(flush_tlb_page, turbosparc_flush_tlb_page, BTFIXUPCALL_NORM);
1825         BTFIXUPSET_CALL(flush_tlb_range, turbosparc_flush_tlb_range, BTFIXUPCALL_NORM);
1826
1827         BTFIXUPSET_CALL(__flush_page_to_ram, turbosparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1828
1829         BTFIXUPSET_CALL(flush_sig_insns, turbosparc_flush_sig_insns, BTFIXUPCALL_NOP);
1830         BTFIXUPSET_CALL(flush_page_for_dma, turbosparc_flush_page_for_dma, BTFIXUPCALL_NORM);
1831
1832         poke_srmmu = poke_turbosparc;
1833 }
1834
1835 static void __cpuinit poke_tsunami(void)
1836 {
1837         unsigned long mreg = srmmu_get_mmureg();
1838
1839         tsunami_flush_icache();
1840         tsunami_flush_dcache();
1841         mreg &= ~TSUNAMI_ITD;
1842         mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1843         srmmu_set_mmureg(mreg);
1844 }
1845
1846 static void __init init_tsunami(void)
1847 {
1848         /*
1849          * Tsunami's pretty sane, Sun and TI actually got it
1850          * somewhat right this time.  Fujitsu should have
1851          * taken some lessons from them.
1852          */
1853
1854         srmmu_name = "TI Tsunami";
1855         srmmu_modtype = Tsunami;
1856
1857         BTFIXUPSET_CALL(flush_cache_all, tsunami_flush_cache_all, BTFIXUPCALL_NORM);
1858         BTFIXUPSET_CALL(flush_cache_mm, tsunami_flush_cache_mm, BTFIXUPCALL_NORM);
1859         BTFIXUPSET_CALL(flush_cache_page, tsunami_flush_cache_page, BTFIXUPCALL_NORM);
1860         BTFIXUPSET_CALL(flush_cache_range, tsunami_flush_cache_range, BTFIXUPCALL_NORM);
1861
1862
1863         BTFIXUPSET_CALL(flush_tlb_all, tsunami_flush_tlb_all, BTFIXUPCALL_NORM);
1864         BTFIXUPSET_CALL(flush_tlb_mm, tsunami_flush_tlb_mm, BTFIXUPCALL_NORM);
1865         BTFIXUPSET_CALL(flush_tlb_page, tsunami_flush_tlb_page, BTFIXUPCALL_NORM);
1866         BTFIXUPSET_CALL(flush_tlb_range, tsunami_flush_tlb_range, BTFIXUPCALL_NORM);
1867
1868         BTFIXUPSET_CALL(__flush_page_to_ram, tsunami_flush_page_to_ram, BTFIXUPCALL_NOP);
1869         BTFIXUPSET_CALL(flush_sig_insns, tsunami_flush_sig_insns, BTFIXUPCALL_NORM);
1870         BTFIXUPSET_CALL(flush_page_for_dma, tsunami_flush_page_for_dma, BTFIXUPCALL_NORM);
1871
1872         poke_srmmu = poke_tsunami;
1873
1874         tsunami_setup_blockops();
1875 }
1876
1877 static void __cpuinit poke_viking(void)
1878 {
1879         unsigned long mreg = srmmu_get_mmureg();
1880         static int smp_catch;
1881
1882         if(viking_mxcc_present) {
1883                 unsigned long mxcc_control = mxcc_get_creg();
1884
1885                 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1886                 mxcc_control &= ~(MXCC_CTL_RRC);
1887                 mxcc_set_creg(mxcc_control);
1888
1889                 /*
1890                  * We don't need memory parity checks.
1891                  * XXX This is a mess, have to dig out later. ecd.
1892                 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1893                  */
1894
1895                 /* We do cache ptables on MXCC. */
1896                 mreg |= VIKING_TCENABLE;
1897         } else {
1898                 unsigned long bpreg;
1899
1900                 mreg &= ~(VIKING_TCENABLE);
1901                 if(smp_catch++) {
1902                         /* Must disable mixed-cmd mode here for other cpu's. */
1903                         bpreg = viking_get_bpreg();
1904                         bpreg &= ~(VIKING_ACTION_MIX);
1905                         viking_set_bpreg(bpreg);
1906
1907                         /* Just in case PROM does something funny. */
1908                         msi_set_sync();
1909                 }
1910         }
1911
1912         mreg |= VIKING_SPENABLE;
1913         mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1914         mreg |= VIKING_SBENABLE;
1915         mreg &= ~(VIKING_ACENABLE);
1916         srmmu_set_mmureg(mreg);
1917 }
1918
1919 static void __init init_viking(void)
1920 {
1921         unsigned long mreg = srmmu_get_mmureg();
1922
1923         /* Ahhh, the viking.  SRMMU VLSI abortion number two... */
1924         if(mreg & VIKING_MMODE) {
1925                 srmmu_name = "TI Viking";
1926                 viking_mxcc_present = 0;
1927                 msi_set_sync();
1928
1929                 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1930                 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1931                 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1932
1933                 /*
1934                  * We need this to make sure old viking takes no hits
1935                  * on it's cache for dma snoops to workaround the
1936                  * "load from non-cacheable memory" interrupt bug.
1937                  * This is only necessary because of the new way in
1938                  * which we use the IOMMU.
1939                  */
1940                 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page, BTFIXUPCALL_NORM);
1941
1942                 flush_page_for_dma_global = 0;
1943         } else {
1944                 srmmu_name = "TI Viking/MXCC";
1945                 viking_mxcc_present = 1;
1946
1947                 srmmu_cache_pagetables = 1;
1948
1949                 /* MXCC vikings lack the DMA snooping bug. */
1950                 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page_for_dma, BTFIXUPCALL_NOP);
1951         }
1952
1953         BTFIXUPSET_CALL(flush_cache_all, viking_flush_cache_all, BTFIXUPCALL_NORM);
1954         BTFIXUPSET_CALL(flush_cache_mm, viking_flush_cache_mm, BTFIXUPCALL_NORM);
1955         BTFIXUPSET_CALL(flush_cache_page, viking_flush_cache_page, BTFIXUPCALL_NORM);
1956         BTFIXUPSET_CALL(flush_cache_range, viking_flush_cache_range, BTFIXUPCALL_NORM);
1957
1958 #ifdef CONFIG_SMP
1959         if (sparc_cpu_model == sun4d) {
1960                 BTFIXUPSET_CALL(flush_tlb_all, sun4dsmp_flush_tlb_all, BTFIXUPCALL_NORM);
1961                 BTFIXUPSET_CALL(flush_tlb_mm, sun4dsmp_flush_tlb_mm, BTFIXUPCALL_NORM);
1962                 BTFIXUPSET_CALL(flush_tlb_page, sun4dsmp_flush_tlb_page, BTFIXUPCALL_NORM);
1963                 BTFIXUPSET_CALL(flush_tlb_range, sun4dsmp_flush_tlb_range, BTFIXUPCALL_NORM);
1964         } else
1965 #endif
1966         {
1967                 BTFIXUPSET_CALL(flush_tlb_all, viking_flush_tlb_all, BTFIXUPCALL_NORM);
1968                 BTFIXUPSET_CALL(flush_tlb_mm, viking_flush_tlb_mm, BTFIXUPCALL_NORM);
1969                 BTFIXUPSET_CALL(flush_tlb_page, viking_flush_tlb_page, BTFIXUPCALL_NORM);
1970                 BTFIXUPSET_CALL(flush_tlb_range, viking_flush_tlb_range, BTFIXUPCALL_NORM);
1971         }
1972
1973         BTFIXUPSET_CALL(__flush_page_to_ram, viking_flush_page_to_ram, BTFIXUPCALL_NOP);
1974         BTFIXUPSET_CALL(flush_sig_insns, viking_flush_sig_insns, BTFIXUPCALL_NOP);
1975
1976         poke_srmmu = poke_viking;
1977 }
1978
1979 /* Probe for the srmmu chip version. */
1980 static void __init get_srmmu_type(void)
1981 {
1982         unsigned long mreg, psr;
1983         unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1984
1985         srmmu_modtype = SRMMU_INVAL_MOD;
1986         hwbug_bitmask = 0;
1987
1988         mreg = srmmu_get_mmureg(); psr = get_psr();
1989         mod_typ = (mreg & 0xf0000000) >> 28;
1990         mod_rev = (mreg & 0x0f000000) >> 24;
1991         psr_typ = (psr >> 28) & 0xf;
1992         psr_vers = (psr >> 24) & 0xf;
1993
1994         /* First, check for HyperSparc or Cypress. */
1995         if(mod_typ == 1) {
1996                 switch(mod_rev) {
1997                 case 7:
1998                         /* UP or MP Hypersparc */
1999                         init_hypersparc();
2000                         break;
2001                 case 0:
2002                 case 2:
2003                         /* Uniprocessor Cypress */
2004                         init_cypress_604();
2005                         break;
2006                 case 10:
2007                 case 11:
2008                 case 12:
2009                         /* _REALLY OLD_ Cypress MP chips... */
2010                 case 13:
2011                 case 14:
2012                 case 15:
2013                         /* MP Cypress mmu/cache-controller */
2014                         init_cypress_605(mod_rev);
2015                         break;
2016                 default:
2017                         /* Some other Cypress revision, assume a 605. */
2018                         init_cypress_605(mod_rev);
2019                         break;
2020                 };
2021                 return;
2022         }
2023
2024         /*
2025          * Now Fujitsu TurboSparc. It might happen that it is
2026          * in Swift emulation mode, so we will check later...
2027          */
2028         if (psr_typ == 0 && psr_vers == 5) {
2029                 init_turbosparc();
2030                 return;
2031         }
2032
2033         /* Next check for Fujitsu Swift. */
2034         if(psr_typ == 0 && psr_vers == 4) {
2035                 int cpunode;
2036                 char node_str[128];
2037
2038                 /* Look if it is not a TurboSparc emulating Swift... */
2039                 cpunode = prom_getchild(prom_root_node);
2040                 while((cpunode = prom_getsibling(cpunode)) != 0) {
2041                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
2042                         if(!strcmp(node_str, "cpu")) {
2043                                 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
2044                                     prom_getintdefault(cpunode, "psr-version", 1) == 5) {
2045                                         init_turbosparc();
2046                                         return;
2047                                 }
2048                                 break;
2049                         }
2050                 }
2051
2052                 init_swift();
2053                 return;
2054         }
2055
2056         /* Now the Viking family of srmmu. */
2057         if(psr_typ == 4 &&
2058            ((psr_vers == 0) ||
2059             ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
2060                 init_viking();
2061                 return;
2062         }
2063
2064         /* Finally the Tsunami. */
2065         if(psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
2066                 init_tsunami();
2067                 return;
2068         }
2069
2070         /* Oh well */
2071         srmmu_is_bad();
2072 }
2073
2074 /* don't laugh, static pagetables */
2075 static void srmmu_check_pgt_cache(int low, int high)
2076 {
2077 }
2078
2079 extern unsigned long spwin_mmu_patchme, fwin_mmu_patchme,
2080         tsetup_mmu_patchme, rtrap_mmu_patchme;
2081
2082 extern unsigned long spwin_srmmu_stackchk, srmmu_fwin_stackchk,
2083         tsetup_srmmu_stackchk, srmmu_rett_stackchk;
2084
2085 extern unsigned long srmmu_fault;
2086
2087 #define PATCH_BRANCH(insn, dest) do { \
2088                 iaddr = &(insn); \
2089                 daddr = &(dest); \
2090                 *iaddr = SPARC_BRANCH((unsigned long) daddr, (unsigned long) iaddr); \
2091         } while(0)
2092
2093 static void __init patch_window_trap_handlers(void)
2094 {
2095         unsigned long *iaddr, *daddr;
2096
2097         PATCH_BRANCH(spwin_mmu_patchme, spwin_srmmu_stackchk);
2098         PATCH_BRANCH(fwin_mmu_patchme, srmmu_fwin_stackchk);
2099         PATCH_BRANCH(tsetup_mmu_patchme, tsetup_srmmu_stackchk);
2100         PATCH_BRANCH(rtrap_mmu_patchme, srmmu_rett_stackchk);
2101         PATCH_BRANCH(sparc_ttable[SP_TRAP_TFLT].inst_three, srmmu_fault);
2102         PATCH_BRANCH(sparc_ttable[SP_TRAP_DFLT].inst_three, srmmu_fault);
2103         PATCH_BRANCH(sparc_ttable[SP_TRAP_DACC].inst_three, srmmu_fault);
2104 }
2105
2106 #ifdef CONFIG_SMP
2107 /* Local cross-calls. */
2108 static void smp_flush_page_for_dma(unsigned long page)
2109 {
2110         xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_for_dma), page);
2111         local_flush_page_for_dma(page);
2112 }
2113
2114 #endif
2115
2116 static pte_t srmmu_pgoff_to_pte(unsigned long pgoff)
2117 {
2118         return __pte((pgoff << SRMMU_PTE_FILE_SHIFT) | SRMMU_FILE);
2119 }
2120
2121 static unsigned long srmmu_pte_to_pgoff(pte_t pte)
2122 {
2123         return pte_val(pte) >> SRMMU_PTE_FILE_SHIFT;
2124 }
2125
2126 static pgprot_t srmmu_pgprot_noncached(pgprot_t prot)
2127 {
2128         prot &= ~__pgprot(SRMMU_CACHE);
2129
2130         return prot;
2131 }
2132
2133 /* Load up routines and constants for sun4m and sun4d mmu */
2134 void __init ld_mmu_srmmu(void)
2135 {
2136         extern void ld_mmu_iommu(void);
2137         extern void ld_mmu_iounit(void);
2138         extern void ___xchg32_sun4md(void);
2139
2140         BTFIXUPSET_SIMM13(pgdir_shift, SRMMU_PGDIR_SHIFT);
2141         BTFIXUPSET_SETHI(pgdir_size, SRMMU_PGDIR_SIZE);
2142         BTFIXUPSET_SETHI(pgdir_mask, SRMMU_PGDIR_MASK);
2143
2144         BTFIXUPSET_SIMM13(ptrs_per_pmd, SRMMU_PTRS_PER_PMD);
2145         BTFIXUPSET_SIMM13(ptrs_per_pgd, SRMMU_PTRS_PER_PGD);
2146
2147         BTFIXUPSET_INT(page_none, pgprot_val(SRMMU_PAGE_NONE));
2148         PAGE_SHARED = pgprot_val(SRMMU_PAGE_SHARED);
2149         BTFIXUPSET_INT(page_copy, pgprot_val(SRMMU_PAGE_COPY));
2150         BTFIXUPSET_INT(page_readonly, pgprot_val(SRMMU_PAGE_RDONLY));
2151         BTFIXUPSET_INT(page_kernel, pgprot_val(SRMMU_PAGE_KERNEL));
2152         page_kernel = pgprot_val(SRMMU_PAGE_KERNEL);
2153
2154         /* Functions */
2155         BTFIXUPSET_CALL(pgprot_noncached, srmmu_pgprot_noncached, BTFIXUPCALL_NORM);
2156 #ifndef CONFIG_SMP
2157         BTFIXUPSET_CALL(___xchg32, ___xchg32_sun4md, BTFIXUPCALL_SWAPG1G2);
2158 #endif
2159         BTFIXUPSET_CALL(do_check_pgt_cache, srmmu_check_pgt_cache, BTFIXUPCALL_NOP);
2160
2161         BTFIXUPSET_CALL(set_pte, srmmu_set_pte, BTFIXUPCALL_SWAPO0O1);
2162         BTFIXUPSET_CALL(switch_mm, srmmu_switch_mm, BTFIXUPCALL_NORM);
2163
2164         BTFIXUPSET_CALL(pte_pfn, srmmu_pte_pfn, BTFIXUPCALL_NORM);
2165         BTFIXUPSET_CALL(pmd_page, srmmu_pmd_page, BTFIXUPCALL_NORM);
2166         BTFIXUPSET_CALL(pgd_page_vaddr, srmmu_pgd_page, BTFIXUPCALL_NORM);
2167
2168         BTFIXUPSET_SETHI(none_mask, 0xF0000000);
2169
2170         BTFIXUPSET_CALL(pte_present, srmmu_pte_present, BTFIXUPCALL_NORM);
2171         BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_SWAPO0G0);
2172
2173         BTFIXUPSET_CALL(pmd_bad, srmmu_pmd_bad, BTFIXUPCALL_NORM);
2174         BTFIXUPSET_CALL(pmd_present, srmmu_pmd_present, BTFIXUPCALL_NORM);
2175         BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_SWAPO0G0);
2176
2177         BTFIXUPSET_CALL(pgd_none, srmmu_pgd_none, BTFIXUPCALL_NORM);
2178         BTFIXUPSET_CALL(pgd_bad, srmmu_pgd_bad, BTFIXUPCALL_NORM);
2179         BTFIXUPSET_CALL(pgd_present, srmmu_pgd_present, BTFIXUPCALL_NORM);
2180         BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_SWAPO0G0);
2181
2182         BTFIXUPSET_CALL(mk_pte, srmmu_mk_pte, BTFIXUPCALL_NORM);
2183         BTFIXUPSET_CALL(mk_pte_phys, srmmu_mk_pte_phys, BTFIXUPCALL_NORM);
2184         BTFIXUPSET_CALL(mk_pte_io, srmmu_mk_pte_io, BTFIXUPCALL_NORM);
2185         BTFIXUPSET_CALL(pgd_set, srmmu_pgd_set, BTFIXUPCALL_NORM);
2186         BTFIXUPSET_CALL(pmd_set, srmmu_pmd_set, BTFIXUPCALL_NORM);
2187         BTFIXUPSET_CALL(pmd_populate, srmmu_pmd_populate, BTFIXUPCALL_NORM);
2188
2189         BTFIXUPSET_INT(pte_modify_mask, SRMMU_CHG_MASK);
2190         BTFIXUPSET_CALL(pmd_offset, srmmu_pmd_offset, BTFIXUPCALL_NORM);
2191         BTFIXUPSET_CALL(pte_offset_kernel, srmmu_pte_offset, BTFIXUPCALL_NORM);
2192
2193         BTFIXUPSET_CALL(free_pte_fast, srmmu_free_pte_fast, BTFIXUPCALL_NORM);
2194         BTFIXUPSET_CALL(pte_free, srmmu_pte_free, BTFIXUPCALL_NORM);
2195         BTFIXUPSET_CALL(pte_alloc_one_kernel, srmmu_pte_alloc_one_kernel, BTFIXUPCALL_NORM);
2196         BTFIXUPSET_CALL(pte_alloc_one, srmmu_pte_alloc_one, BTFIXUPCALL_NORM);
2197         BTFIXUPSET_CALL(free_pmd_fast, srmmu_pmd_free, BTFIXUPCALL_NORM);
2198         BTFIXUPSET_CALL(pmd_alloc_one, srmmu_pmd_alloc_one, BTFIXUPCALL_NORM);
2199         BTFIXUPSET_CALL(free_pgd_fast, srmmu_free_pgd_fast, BTFIXUPCALL_NORM);
2200         BTFIXUPSET_CALL(get_pgd_fast, srmmu_get_pgd_fast, BTFIXUPCALL_NORM);
2201
2202         BTFIXUPSET_HALF(pte_writei, SRMMU_WRITE);
2203         BTFIXUPSET_HALF(pte_dirtyi, SRMMU_DIRTY);
2204         BTFIXUPSET_HALF(pte_youngi, SRMMU_REF);
2205         BTFIXUPSET_HALF(pte_filei, SRMMU_FILE);
2206         BTFIXUPSET_HALF(pte_wrprotecti, SRMMU_WRITE);
2207         BTFIXUPSET_HALF(pte_mkcleani, SRMMU_DIRTY);
2208         BTFIXUPSET_HALF(pte_mkoldi, SRMMU_REF);
2209         BTFIXUPSET_CALL(pte_mkwrite, srmmu_pte_mkwrite, BTFIXUPCALL_ORINT(SRMMU_WRITE));
2210         BTFIXUPSET_CALL(pte_mkdirty, srmmu_pte_mkdirty, BTFIXUPCALL_ORINT(SRMMU_DIRTY));
2211         BTFIXUPSET_CALL(pte_mkyoung, srmmu_pte_mkyoung, BTFIXUPCALL_ORINT(SRMMU_REF));
2212         BTFIXUPSET_CALL(update_mmu_cache, srmmu_update_mmu_cache, BTFIXUPCALL_NOP);
2213         BTFIXUPSET_CALL(destroy_context, srmmu_destroy_context, BTFIXUPCALL_NORM);
2214
2215         BTFIXUPSET_CALL(sparc_mapiorange, srmmu_mapiorange, BTFIXUPCALL_NORM);
2216         BTFIXUPSET_CALL(sparc_unmapiorange, srmmu_unmapiorange, BTFIXUPCALL_NORM);
2217
2218         BTFIXUPSET_CALL(__swp_type, srmmu_swp_type, BTFIXUPCALL_NORM);
2219         BTFIXUPSET_CALL(__swp_offset, srmmu_swp_offset, BTFIXUPCALL_NORM);
2220         BTFIXUPSET_CALL(__swp_entry, srmmu_swp_entry, BTFIXUPCALL_NORM);
2221
2222         BTFIXUPSET_CALL(mmu_info, srmmu_mmu_info, BTFIXUPCALL_NORM);
2223
2224         BTFIXUPSET_CALL(alloc_thread_info, srmmu_alloc_thread_info, BTFIXUPCALL_NORM);
2225         BTFIXUPSET_CALL(free_thread_info, srmmu_free_thread_info, BTFIXUPCALL_NORM);
2226
2227         BTFIXUPSET_CALL(pte_to_pgoff, srmmu_pte_to_pgoff, BTFIXUPCALL_NORM);
2228         BTFIXUPSET_CALL(pgoff_to_pte, srmmu_pgoff_to_pte, BTFIXUPCALL_NORM);
2229
2230         get_srmmu_type();
2231         patch_window_trap_handlers();
2232
2233 #ifdef CONFIG_SMP
2234         /* El switcheroo... */
2235
2236         BTFIXUPCOPY_CALL(local_flush_cache_all, flush_cache_all);
2237         BTFIXUPCOPY_CALL(local_flush_cache_mm, flush_cache_mm);
2238         BTFIXUPCOPY_CALL(local_flush_cache_range, flush_cache_range);
2239         BTFIXUPCOPY_CALL(local_flush_cache_page, flush_cache_page);
2240         BTFIXUPCOPY_CALL(local_flush_tlb_all, flush_tlb_all);
2241         BTFIXUPCOPY_CALL(local_flush_tlb_mm, flush_tlb_mm);
2242         BTFIXUPCOPY_CALL(local_flush_tlb_range, flush_tlb_range);
2243         BTFIXUPCOPY_CALL(local_flush_tlb_page, flush_tlb_page);
2244         BTFIXUPCOPY_CALL(local_flush_page_to_ram, __flush_page_to_ram);
2245         BTFIXUPCOPY_CALL(local_flush_sig_insns, flush_sig_insns);
2246         BTFIXUPCOPY_CALL(local_flush_page_for_dma, flush_page_for_dma);
2247
2248         BTFIXUPSET_CALL(flush_cache_all, smp_flush_cache_all, BTFIXUPCALL_NORM);
2249         BTFIXUPSET_CALL(flush_cache_mm, smp_flush_cache_mm, BTFIXUPCALL_NORM);
2250         BTFIXUPSET_CALL(flush_cache_range, smp_flush_cache_range, BTFIXUPCALL_NORM);
2251         BTFIXUPSET_CALL(flush_cache_page, smp_flush_cache_page, BTFIXUPCALL_NORM);
2252         if (sparc_cpu_model != sun4d) {
2253                 BTFIXUPSET_CALL(flush_tlb_all, smp_flush_tlb_all, BTFIXUPCALL_NORM);
2254                 BTFIXUPSET_CALL(flush_tlb_mm, smp_flush_tlb_mm, BTFIXUPCALL_NORM);
2255                 BTFIXUPSET_CALL(flush_tlb_range, smp_flush_tlb_range, BTFIXUPCALL_NORM);
2256                 BTFIXUPSET_CALL(flush_tlb_page, smp_flush_tlb_page, BTFIXUPCALL_NORM);
2257         }
2258         BTFIXUPSET_CALL(__flush_page_to_ram, smp_flush_page_to_ram, BTFIXUPCALL_NORM);
2259         BTFIXUPSET_CALL(flush_sig_insns, smp_flush_sig_insns, BTFIXUPCALL_NORM);
2260         BTFIXUPSET_CALL(flush_page_for_dma, smp_flush_page_for_dma, BTFIXUPCALL_NORM);
2261
2262         if (poke_srmmu == poke_viking) {
2263                 /* Avoid unnecessary cross calls. */
2264                 BTFIXUPCOPY_CALL(flush_cache_all, local_flush_cache_all);
2265                 BTFIXUPCOPY_CALL(flush_cache_mm, local_flush_cache_mm);
2266                 BTFIXUPCOPY_CALL(flush_cache_range, local_flush_cache_range);
2267                 BTFIXUPCOPY_CALL(flush_cache_page, local_flush_cache_page);
2268                 BTFIXUPCOPY_CALL(__flush_page_to_ram, local_flush_page_to_ram);
2269                 BTFIXUPCOPY_CALL(flush_sig_insns, local_flush_sig_insns);
2270                 BTFIXUPCOPY_CALL(flush_page_for_dma, local_flush_page_for_dma);
2271         }
2272 #endif
2273
2274         if (sparc_cpu_model == sun4d)
2275                 ld_mmu_iounit();
2276         else
2277                 ld_mmu_iommu();
2278 #ifdef CONFIG_SMP
2279         if (sparc_cpu_model == sun4d)
2280                 sun4d_init_smp();
2281         else
2282                 sun4m_init_smp();
2283 #endif
2284 }