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   1 /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
   2  * irq.c: UltraSparc IRQ handling/init/registry.
   3  *
   4  * Copyright (C) 1997  David S. Miller  (davem@caip.rutgers.edu)
   5  * Copyright (C) 1998  Eddie C. Dost    (ecd@skynet.be)
   6  * Copyright (C) 1998  Jakub Jelinek    (jj@ultra.linux.cz)
   7  */
   8
   9 #include <linux/config.h>
  10 #include <linux/module.h>
  11 #include <linux/sched.h>
  12 #include <linux/ptrace.h>
  13 #include <linux/errno.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/signal.h>
  16 #include <linux/mm.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/slab.h>
  19 #include <linux/random.h>
  20 #include <linux/init.h>
  21 #include <linux/delay.h>
  22 #include <linux/proc_fs.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/bootmem.h>
  25
  26 #include <asm/ptrace.h>
  27 #include <asm/processor.h>
  28 #include <asm/atomic.h>
  29 #include <asm/system.h>
  30 #include <asm/irq.h>
  31 #include <asm/io.h>
  32 #include <asm/sbus.h>
  33 #include <asm/iommu.h>
  34 #include <asm/upa.h>
  35 #include <asm/oplib.h>
  36 #include <asm/timer.h>
  37 #include <asm/smp.h>
  38 #include <asm/starfire.h>
  39 #include <asm/uaccess.h>
  40 #include <asm/cache.h>
  41 #include <asm/cpudata.h>
  42 #include <asm/auxio.h>
  43 #include <asm/head.h>
  44
  45 #ifdef CONFIG_SMP
  46 static void distribute_irqs(void);
  47 #endif
  48
  49 /* UPA nodes send interrupt packet to UltraSparc with first data reg
  50  * value low 5 (7 on Starfire) bits holding the IRQ identifier being
  51  * delivered.  We must translate this into a non-vector IRQ so we can
  52  * set the softint on this cpu.
  53  *
  54  * To make processing these packets efficient and race free we use
  55  * an array of irq buckets below.  The interrupt vector handler in
  56  * entry.S feeds incoming packets into per-cpu pil-indexed lists.
  57  * The IVEC handler does not need to act atomically, the PIL dispatch
  58  * code uses CAS to get an atomic snapshot of the list and clear it
  59  * at the same time.
  60  */
  61
  62 struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
  63
  64 /* This has to be in the main kernel image, it cannot be
  65  * turned into per-cpu data.  The reason is that the main
  66  * kernel image is locked into the TLB and this structure
  67  * is accessed from the vectored interrupt trap handler.  If
  68  * access to this structure takes a TLB miss it could cause
  69  * the 5-level sparc v9 trap stack to overflow.
  70  */
  71 struct irq_work_struct {
  72         unsigned int    irq_worklists[16];
  73 };
  74 struct irq_work_struct __irq_work[NR_CPUS];
  75 #define irq_work(__cpu, __pil)  &(__irq_work[(__cpu)].irq_worklists[(__pil)])
  76
  77 static struct irqaction *irq_action[NR_IRQS+1];
  78
  79 /* This only synchronizes entities which modify IRQ handler
  80  * state and some selected user-level spots that want to
  81  * read things in the table.  IRQ handler processing orders
  82  * its' accesses such that no locking is needed.
  83  */
  84 static DEFINE_SPINLOCK(irq_action_lock);
  85
  86 static void register_irq_proc (unsigned int irq);
  87
  88 /*
  89  * Upper 2b of irqaction->flags holds the ino.
  90  * irqaction->mask holds the smp affinity information.
  91  */
  92 #define put_ino_in_irqaction(action, irq) \
  93         action->flags &= 0xffffffffffffUL; \
  94         if (__bucket(irq) == &pil0_dummy_bucket) \
  95                 action->flags |= 0xdeadUL << 48;  \
  96         else \
  97                 action->flags |= __irq_ino(irq) << 48;
  98 #define get_ino_in_irqaction(action)    (action->flags >> 48)
  99
 100 #define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff)
 101 #define get_smpaff_in_irqaction(action)         ((action)->mask)
 102
 103 int show_interrupts(struct seq_file *p, void *v)
 104 {
 105         unsigned long flags;
 106         int i = *(loff_t *) v;
 107         struct irqaction *action;
 108 #ifdef CONFIG_SMP
 109         int j;
 110 #endif
 111
 112         spin_lock_irqsave(&irq_action_lock, flags);
 113         if (i <= NR_IRQS) {
 114                 if (!(action = *(i + irq_action)))
 115                         goto out_unlock;
 116                 seq_printf(p, "%3d: ", i);
 117 #ifndef CONFIG_SMP
 118                 seq_printf(p, "%10u ", kstat_irqs(i));
 119 #else
 120                 for (j = 0; j < NR_CPUS; j++) {
 121                         if (!cpu_online(j))
 122                                 continue;
 123                         seq_printf(p, "%10u ",
 124                                    kstat_cpu(j).irqs[i]);
 125                 }
 126 #endif
 127                 seq_printf(p, " %s:%lx", action->name,
 128                            get_ino_in_irqaction(action));
 129                 for (action = action->next; action; action = action->next) {
 130                         seq_printf(p, ", %s:%lx", action->name,
 131                                    get_ino_in_irqaction(action));
 132                 }
 133                 seq_putc(p, '\n');
 134         }
 135 out_unlock:
 136         spin_unlock_irqrestore(&irq_action_lock, flags);
 137
 138         return 0;
 139 }
 140
 141 /* Now these are always passed a true fully specified sun4u INO. */
 142 void enable_irq(unsigned int irq)
 143 {
 144         struct ino_bucket *bucket = __bucket(irq);
 145         unsigned long imap;
 146         unsigned long tid;
 147
 148         imap = bucket->imap;
 149         if (imap == 0UL)
 150                 return;
 151
 152         preempt_disable();
 153
 154         if (tlb_type == hypervisor) {
 155                 /* XXX SUN4V: implement me... XXX */
 156         } else {
 157                 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 158                         unsigned long ver;
 159
 160                         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 161                         if ((ver >> 32) == __JALAPENO_ID ||
 162                             (ver >> 32) == __SERRANO_ID) {
 163                                 /* We set it to our JBUS ID. */
 164                                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
 165                                                      : "=r" (tid)
 166                                                      : "i" (ASI_JBUS_CONFIG));
 167                                 tid = ((tid & (0x1fUL<<17)) << 9);
 168                                 tid &= IMAP_TID_JBUS;
 169                         } else {
 170                                 /* We set it to our Safari AID. */
 171                                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
 172                                                      : "=r" (tid)
 173                                                      : "i"(ASI_SAFARI_CONFIG));
 174                                 tid = ((tid & (0x3ffUL<<17)) << 9);
 175                                 tid &= IMAP_AID_SAFARI;
 176                         }
 177                 } else if (this_is_starfire == 0) {
 178                         /* We set it to our UPA MID. */
 179                         __asm__ __volatile__("ldxa [%%g0] %1, %0"
 180                                              : "=r" (tid)
 181                                              : "i" (ASI_UPA_CONFIG));
 182                         tid = ((tid & UPA_CONFIG_MID) << 9);
 183                         tid &= IMAP_TID_UPA;
 184                 } else {
 185                         tid = (starfire_translate(imap,
 186                                                   smp_processor_id()) << 26);
 187                         tid &= IMAP_TID_UPA;
 188                 }
 189
 190                 /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product
 191                  * of this SYSIO's preconfigured IGN in the SYSIO Control
 192                  * Register, the hardware just mirrors that value here.
 193                  * However for Graphics and UPA Slave devices the full
 194                  * IMAP_INR field can be set by the programmer here.
 195                  *
 196                  * Things like FFB can now be handled via the new IRQ
 197                  * mechanism.
 198                  */
 199                 upa_writel(tid | IMAP_VALID, imap);
 200         }
 201
 202         preempt_enable();
 203 }
 204
 205 /* This now gets passed true ino's as well. */
 206 void disable_irq(unsigned int irq)
 207 {
 208         struct ino_bucket *bucket = __bucket(irq);
 209         unsigned long imap;
 210
 211         imap = bucket->imap;
 212         if (imap != 0UL) {
 213                 u32 tmp;
 214
 215                 /* NOTE: We do not want to futz with the IRQ clear registers
 216                  *       and move the state to IDLE, the SCSI code does call
 217                  *       disable_irq() to assure atomicity in the queue cmd
 218                  *       SCSI adapter driver code.  Thus we'd lose interrupts.
 219                  */
 220                 tmp = upa_readl(imap);
 221                 tmp &= ~IMAP_VALID;
 222                 upa_writel(tmp, imap);
 223         }
 224 }
 225
 226 /* The timer is the one "weird" interrupt which is generated by
 227  * the CPU %tick register and not by some normal vectored interrupt
 228  * source.  To handle this special case, we use this dummy INO bucket.
 229  */
 230 static struct irq_desc pil0_dummy_desc;
 231 static struct ino_bucket pil0_dummy_bucket = {
 232         .irq_info       =       &pil0_dummy_desc,
 233 };
 234
 235 static void build_irq_error(const char *msg, unsigned int ino, int pil, int inofixup,
 236                             unsigned long iclr, unsigned long imap,
 237                             struct ino_bucket *bucket)
 238 {
 239         prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> "
 240                     "(%d:%d:%016lx:%016lx), halting...\n",
 241                     ino, bucket->pil, bucket->iclr, bucket->imap,
 242                     pil, inofixup, iclr, imap);
 243         prom_halt();
 244 }
 245
 246 unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap)
 247 {
 248         struct ino_bucket *bucket;
 249         int ino;
 250
 251         if (pil == 0) {
 252                 if (iclr != 0UL || imap != 0UL) {
 253                         prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n",
 254                                     iclr, imap);
 255                         prom_halt();
 256                 }
 257                 return __irq(&pil0_dummy_bucket);
 258         }
 259
 260         /* RULE: Both must be specified in all other cases. */
 261         if (iclr == 0UL || imap == 0UL) {
 262                 prom_printf("Invalid build_irq %d %d %016lx %016lx\n",
 263                             pil, inofixup, iclr, imap);
 264                 prom_halt();
 265         }
 266
 267         ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
 268         if (ino > NUM_IVECS) {
 269                 prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n",
 270                             ino, pil, inofixup, iclr, imap);
 271                 prom_halt();
 272         }
 273
 274         bucket = &ivector_table[ino];
 275         if (bucket->flags & IBF_ACTIVE)
 276                 build_irq_error("IRQ: Trying to build active INO bucket.\n",
 277                                 ino, pil, inofixup, iclr, imap, bucket);
 278
 279         if (bucket->irq_info) {
 280                 if (bucket->imap != imap || bucket->iclr != iclr)
 281                         build_irq_error("IRQ: Trying to reinit INO bucket.\n",
 282                                         ino, pil, inofixup, iclr, imap, bucket);
 283
 284                 goto out;
 285         }
 286
 287         bucket->irq_info = kmalloc(sizeof(struct irq_desc), GFP_ATOMIC);
 288         if (!bucket->irq_info) {
 289                 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
 290                 prom_halt();
 291         }
 292         memset(bucket->irq_info, 0, sizeof(struct irq_desc));
 293
 294         /* Ok, looks good, set it up.  Don't touch the irq_chain or
 295          * the pending flag.
 296          */
 297         bucket->imap  = imap;
 298         bucket->iclr  = iclr;
 299         bucket->pil   = pil;
 300         bucket->flags = 0;
 301
 302 out:
 303         return __irq(bucket);
 304 }
 305
 306 static void atomic_bucket_insert(struct ino_bucket *bucket)
 307 {
 308         unsigned long pstate;
 309         unsigned int *ent;
 310
 311         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 312         __asm__ __volatile__("wrpr %0, %1, %%pstate"
 313                              : : "r" (pstate), "i" (PSTATE_IE));
 314         ent = irq_work(smp_processor_id(), bucket->pil);
 315         bucket->irq_chain = *ent;
 316         *ent = __irq(bucket);
 317         __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
 318 }
 319
 320 static int check_irq_sharing(int pil, unsigned long irqflags)
 321 {
 322         struct irqaction *action, *tmp;
 323
 324         action = *(irq_action + pil);
 325         if (action) {
 326                 if ((action->flags & SA_SHIRQ) && (irqflags & SA_SHIRQ)) {
 327                         for (tmp = action; tmp->next; tmp = tmp->next)
 328                                 ;
 329                 } else {
 330                         return -EBUSY;
 331                 }
 332         }
 333         return 0;
 334 }
 335
 336 static void append_irq_action(int pil, struct irqaction *action)
 337 {
 338         struct irqaction **pp = irq_action + pil;
 339
 340         while (*pp)
 341                 pp = &((*pp)->next);
 342         *pp = action;
 343 }
 344
 345 static struct irqaction *get_action_slot(struct ino_bucket *bucket)
 346 {
 347         struct irq_desc *desc = bucket->irq_info;
 348         int max_irq, i;
 349
 350         max_irq = 1;
 351         if (bucket->flags & IBF_PCI)
 352                 max_irq = MAX_IRQ_DESC_ACTION;
 353         for (i = 0; i < max_irq; i++) {
 354                 struct irqaction *p = &desc->action[i];
 355                 u32 mask = (1 << i);
 356
 357                 if (desc->action_active_mask & mask)
 358                         continue;
 359
 360                 desc->action_active_mask |= mask;
 361                 return p;
 362         }
 363         return NULL;
 364 }
 365
 366 int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *),
 367                 unsigned long irqflags, const char *name, void *dev_id)
 368 {
 369         struct irqaction *action;
 370         struct ino_bucket *bucket = __bucket(irq);
 371         unsigned long flags;
 372         int pending = 0;
 373
 374         if (unlikely(!handler))
 375                 return -EINVAL;
 376
 377         if (unlikely(!bucket->irq_info))
 378                 return -ENODEV;
 379
 380         if ((bucket != &pil0_dummy_bucket) && (irqflags & SA_SAMPLE_RANDOM)) {
 381                 /*
 382                  * This function might sleep, we want to call it first,
 383                  * outside of the atomic block. In SA_STATIC_ALLOC case,
 384                  * random driver's kmalloc will fail, but it is safe.
 385                  * If already initialized, random driver will not reinit.
 386                  * Yes, this might clear the entropy pool if the wrong
 387                  * driver is attempted to be loaded, without actually
 388                  * installing a new handler, but is this really a problem,
 389                  * only the sysadmin is able to do this.
 390                  */
 391                 rand_initialize_irq(irq);
 392         }
 393
 394         spin_lock_irqsave(&irq_action_lock, flags);
 395
 396         if (check_irq_sharing(bucket->pil, irqflags)) {
 397                 spin_unlock_irqrestore(&irq_action_lock, flags);
 398                 return -EBUSY;
 399         }
 400
 401         action = get_action_slot(bucket);
 402         if (!action) {
 403                 spin_unlock_irqrestore(&irq_action_lock, flags);
 404                 return -ENOMEM;
 405         }
 406
 407         bucket->flags |= IBF_ACTIVE;
 408         pending = 0;
 409         if (bucket != &pil0_dummy_bucket) {
 410                 pending = bucket->pending;
 411                 if (pending)
 412                         bucket->pending = 0;
 413         }
 414
 415         action->handler = handler;
 416         action->flags = irqflags;
 417         action->name = name;
 418         action->next = NULL;
 419         action->dev_id = dev_id;
 420         put_ino_in_irqaction(action, irq);
 421         put_smpaff_in_irqaction(action, CPU_MASK_NONE);
 422
 423         append_irq_action(bucket->pil, action);
 424
 425         enable_irq(irq);
 426
 427         /* We ate the IVEC already, this makes sure it does not get lost. */
 428         if (pending) {
 429                 atomic_bucket_insert(bucket);
 430                 set_softint(1 << bucket->pil);
 431         }
 432
 433         spin_unlock_irqrestore(&irq_action_lock, flags);
 434
 435         if (bucket != &pil0_dummy_bucket)
 436                 register_irq_proc(__irq_ino(irq));
 437
 438 #ifdef CONFIG_SMP
 439         distribute_irqs();
 440 #endif
 441         return 0;
 442 }
 443
 444 EXPORT_SYMBOL(request_irq);
 445
 446 static struct irqaction *unlink_irq_action(unsigned int irq, void *dev_id)
 447 {
 448         struct ino_bucket *bucket = __bucket(irq);
 449         struct irqaction *action, **pp;
 450
 451         pp = irq_action + bucket->pil;
 452         action = *pp;
 453         if (unlikely(!action))
 454                 return NULL;
 455
 456         if (unlikely(!action->handler)) {
 457                 printk("Freeing free IRQ %d\n", bucket->pil);
 458                 return NULL;
 459         }
 460
 461         while (action && action->dev_id != dev_id) {
 462                 pp = &action->next;
 463                 action = *pp;
 464         }
 465
 466         if (likely(action))
 467                 *pp = action->next;
 468
 469         return action;
 470 }
 471
 472 void free_irq(unsigned int irq, void *dev_id)
 473 {
 474         struct irqaction *action;
 475         struct ino_bucket *bucket;
 476         unsigned long flags;
 477
 478         spin_lock_irqsave(&irq_action_lock, flags);
 479
 480         action = unlink_irq_action(irq, dev_id);
 481
 482         spin_unlock_irqrestore(&irq_action_lock, flags);
 483
 484         if (unlikely(!action))
 485                 return;
 486
 487         synchronize_irq(irq);
 488
 489         spin_lock_irqsave(&irq_action_lock, flags);
 490
 491         bucket = __bucket(irq);
 492         if (bucket != &pil0_dummy_bucket) {
 493                 struct irq_desc *desc = bucket->irq_info;
 494                 unsigned long imap = bucket->imap;
 495                 int ent, i;
 496
 497                 for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
 498                         struct irqaction *p = &desc->action[i];
 499
 500                         if (p == action) {
 501                                 desc->action_active_mask &= ~(1 << i);
 502                                 break;
 503                         }
 504                 }
 505
 506                 if (!desc->action_active_mask) {
 507                         /* This unique interrupt source is now inactive. */
 508                         bucket->flags &= ~IBF_ACTIVE;
 509
 510                         /* See if any other buckets share this bucket's IMAP
 511                          * and are still active.
 512                          */
 513                         for (ent = 0; ent < NUM_IVECS; ent++) {
 514                                 struct ino_bucket *bp = &ivector_table[ent];
 515                                 if (bp != bucket        &&
 516                                     bp->imap == imap    &&
 517                                     (bp->flags & IBF_ACTIVE) != 0)
 518                                         break;
 519                         }
 520
 521                         /* Only disable when no other sub-irq levels of
 522                          * the same IMAP are active.
 523                          */
 524                         if (ent == NUM_IVECS)
 525                                 disable_irq(irq);
 526                 }
 527         }
 528
 529         spin_unlock_irqrestore(&irq_action_lock, flags);
 530 }
 531
 532 EXPORT_SYMBOL(free_irq);
 533
 534 #ifdef CONFIG_SMP
 535 void synchronize_irq(unsigned int irq)
 536 {
 537         struct ino_bucket *bucket = __bucket(irq);
 538
 539 #if 0
 540         /* The following is how I wish I could implement this.
 541          * Unfortunately the ICLR registers are read-only, you can
 542          * only write ICLR_foo values to them.  To get the current
 543          * IRQ status you would need to get at the IRQ diag registers
 544          * in the PCI/SBUS controller and the layout of those vary
 545          * from one controller to the next, sigh... -DaveM
 546          */
 547         unsigned long iclr = bucket->iclr;
 548
 549         while (1) {
 550                 u32 tmp = upa_readl(iclr);
 551
 552                 if (tmp == ICLR_TRANSMIT ||
 553                     tmp == ICLR_PENDING) {
 554                         cpu_relax();
 555                         continue;
 556                 }
 557                 break;
 558         }
 559 #else
 560         /* So we have to do this with a INPROGRESS bit just like x86.  */
 561         while (bucket->flags & IBF_INPROGRESS)
 562                 cpu_relax();
 563 #endif
 564 }
 565 #endif /* CONFIG_SMP */
 566
 567 static void process_bucket(int irq, struct ino_bucket *bp, struct pt_regs *regs)
 568 {
 569         struct irq_desc *desc = bp->irq_info;
 570         unsigned char flags = bp->flags;
 571         u32 action_mask, i;
 572         int random;
 573
 574         bp->flags |= IBF_INPROGRESS;
 575
 576         if (unlikely(!(flags & IBF_ACTIVE))) {
 577                 bp->pending = 1;
 578                 goto out;
 579         }
 580
 581         if (desc->pre_handler)
 582                 desc->pre_handler(bp,
 583                                   desc->pre_handler_arg1,
 584                                   desc->pre_handler_arg2);
 585
 586         action_mask = desc->action_active_mask;
 587         random = 0;
 588         for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
 589                 struct irqaction *p = &desc->action[i];
 590                 u32 mask = (1 << i);
 591
 592                 if (!(action_mask & mask))
 593                         continue;
 594
 595                 action_mask &= ~mask;
 596
 597                 if (p->handler(__irq(bp), p->dev_id, regs) == IRQ_HANDLED)
 598                         random |= p->flags;
 599
 600                 if (!action_mask)
 601                         break;
 602         }
 603         if (bp->pil != 0) {
 604                 upa_writel(ICLR_IDLE, bp->iclr);
 605                 /* Test and add entropy */
 606                 if (random & SA_SAMPLE_RANDOM)
 607                         add_interrupt_randomness(irq);
 608         }
 609 out:
 610         bp->flags &= ~IBF_INPROGRESS;
 611 }
 612
 613 void handler_irq(int irq, struct pt_regs *regs)
 614 {
 615         struct ino_bucket *bp;
 616         int cpu = smp_processor_id();
 617
 618 #ifndef CONFIG_SMP
 619         /*
 620          * Check for TICK_INT on level 14 softint.
 621          */
 622         {
 623                 unsigned long clr_mask = 1 << irq;
 624                 unsigned long tick_mask = tick_ops->softint_mask;
 625
 626                 if ((irq == 14) && (get_softint() & tick_mask)) {
 627                         irq = 0;
 628                         clr_mask = tick_mask;
 629                 }
 630                 clear_softint(clr_mask);
 631         }
 632 #else
 633         clear_softint(1 << irq);
 634 #endif
 635
 636         irq_enter();
 637         kstat_this_cpu.irqs[irq]++;
 638
 639         /* Sliiiick... */
 640 #ifndef CONFIG_SMP
 641         bp = ((irq != 0) ?
 642               __bucket(xchg32(irq_work(cpu, irq), 0)) :
 643               &pil0_dummy_bucket);
 644 #else
 645         bp = __bucket(xchg32(irq_work(cpu, irq), 0));
 646 #endif
 647         while (bp) {
 648                 struct ino_bucket *nbp = __bucket(bp->irq_chain);
 649
 650                 bp->irq_chain = 0;
 651                 process_bucket(irq, bp, regs);
 652                 bp = nbp;
 653         }
 654         irq_exit();
 655 }
 656
 657 #ifdef CONFIG_BLK_DEV_FD
 658 extern irqreturn_t floppy_interrupt(int, void *, struct pt_regs *);;
 659
 660 /* XXX No easy way to include asm/floppy.h XXX */
 661 extern unsigned char *pdma_vaddr;
 662 extern unsigned long pdma_size;
 663 extern volatile int doing_pdma;
 664 extern unsigned long fdc_status;
 665
 666 irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie, struct pt_regs *regs)
 667 {
 668         if (likely(doing_pdma)) {
 669                 void __iomem *stat = (void __iomem *) fdc_status;
 670                 unsigned char *vaddr = pdma_vaddr;
 671                 unsigned long size = pdma_size;
 672                 u8 val;
 673
 674                 while (size) {
 675                         val = readb(stat);
 676                         if (unlikely(!(val & 0x80))) {
 677                                 pdma_vaddr = vaddr;
 678                                 pdma_size = size;
 679                                 return IRQ_HANDLED;
 680                         }
 681                         if (unlikely(!(val & 0x20))) {
 682                                 pdma_vaddr = vaddr;
 683                                 pdma_size = size;
 684                                 doing_pdma = 0;
 685                                 goto main_interrupt;
 686                         }
 687                         if (val & 0x40) {
 688                                 /* read */
 689                                 *vaddr++ = readb(stat + 1);
 690                         } else {
 691                                 unsigned char data = *vaddr++;
 692
 693                                 /* write */
 694                                 writeb(data, stat + 1);
 695                         }
 696                         size--;
 697                 }
 698
 699                 pdma_vaddr = vaddr;
 700                 pdma_size = size;
 701
 702                 /* Send Terminal Count pulse to floppy controller. */
 703                 val = readb(auxio_register);
 704                 val |= AUXIO_AUX1_FTCNT;
 705                 writeb(val, auxio_register);
 706                 val &= ~AUXIO_AUX1_FTCNT;
 707                 writeb(val, auxio_register);
 708
 709                 doing_pdma = 0;
 710         }
 711
 712 main_interrupt:
 713         return floppy_interrupt(irq, dev_cookie, regs);
 714 }
 715 EXPORT_SYMBOL(sparc_floppy_irq);
 716 #endif
 717
 718 /* We really don't need these at all on the Sparc.  We only have
 719  * stubs here because they are exported to modules.
 720  */
 721 unsigned long probe_irq_on(void)
 722 {
 723         return 0;
 724 }
 725
 726 EXPORT_SYMBOL(probe_irq_on);
 727
 728 int probe_irq_off(unsigned long mask)
 729 {
 730         return 0;
 731 }
 732
 733 EXPORT_SYMBOL(probe_irq_off);
 734
 735 #ifdef CONFIG_SMP
 736 static int retarget_one_irq(struct irqaction *p, int goal_cpu)
 737 {
 738         struct ino_bucket *bucket = get_ino_in_irqaction(p) + ivector_table;
 739         unsigned long imap = bucket->imap;
 740         unsigned int tid;
 741
 742         while (!cpu_online(goal_cpu)) {
 743                 if (++goal_cpu >= NR_CPUS)
 744                         goal_cpu = 0;
 745         }
 746
 747         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 748                 tid = goal_cpu << 26;
 749                 tid &= IMAP_AID_SAFARI;
 750         } else if (this_is_starfire == 0) {
 751                 tid = goal_cpu << 26;
 752                 tid &= IMAP_TID_UPA;
 753         } else {
 754                 tid = (starfire_translate(imap, goal_cpu) << 26);
 755                 tid &= IMAP_TID_UPA;
 756         }
 757         upa_writel(tid | IMAP_VALID, imap);
 758
 759         do {
 760                 if (++goal_cpu >= NR_CPUS)
 761                         goal_cpu = 0;
 762         } while (!cpu_online(goal_cpu));
 763
 764         return goal_cpu;
 765 }
 766
 767 /* Called from request_irq. */
 768 static void distribute_irqs(void)
 769 {
 770         unsigned long flags;
 771         int cpu, level;
 772
 773         spin_lock_irqsave(&irq_action_lock, flags);
 774         cpu = 0;
 775
 776         /*
 777          * Skip the timer at [0], and very rare error/power intrs at [15].
 778          * Also level [12], it causes problems on Ex000 systems.
 779          */
 780         for (level = 1; level < NR_IRQS; level++) {
 781                 struct irqaction *p = irq_action[level];
 782
 783                 if (level == 12)
 784                         continue;
 785
 786                 while(p) {
 787                         cpu = retarget_one_irq(p, cpu);
 788                         p = p->next;
 789                 }
 790         }
 791         spin_unlock_irqrestore(&irq_action_lock, flags);
 792 }
 793 #endif
 794
 795 struct sun5_timer {
 796         u64     count0;
 797         u64     limit0;
 798         u64     count1;
 799         u64     limit1;
 800 };
 801
 802 static struct sun5_timer *prom_timers;
 803 static u64 prom_limit0, prom_limit1;
 804
 805 static void map_prom_timers(void)
 806 {
 807         unsigned int addr[3];
 808         int tnode, err;
 809
 810         /* PROM timer node hangs out in the top level of device siblings... */
 811         tnode = prom_finddevice("/counter-timer");
 812
 813         /* Assume if node is not present, PROM uses different tick mechanism
 814          * which we should not care about.
 815          */
 816         if (tnode == 0 || tnode == -1) {
 817                 prom_timers = (struct sun5_timer *) 0;
 818                 return;
 819         }
 820
 821         /* If PROM is really using this, it must be mapped by him. */
 822         err = prom_getproperty(tnode, "address", (char *)addr, sizeof(addr));
 823         if (err == -1) {
 824                 prom_printf("PROM does not have timer mapped, trying to continue.\n");
 825                 prom_timers = (struct sun5_timer *) 0;
 826                 return;
 827         }
 828         prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
 829 }
 830
 831 static void kill_prom_timer(void)
 832 {
 833         if (!prom_timers)
 834                 return;
 835
 836         /* Save them away for later. */
 837         prom_limit0 = prom_timers->limit0;
 838         prom_limit1 = prom_timers->limit1;
 839
 840         /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
 841          * We turn both off here just to be paranoid.
 842          */
 843         prom_timers->limit0 = 0;
 844         prom_timers->limit1 = 0;
 845
 846         /* Wheee, eat the interrupt packet too... */
 847         __asm__ __volatile__(
 848 "       mov     0x40, %%g2\n"
 849 "       ldxa    [%%g0] %0, %%g1\n"
 850 "       ldxa    [%%g2] %1, %%g1\n"
 851 "       stxa    %%g0, [%%g0] %0\n"
 852 "       membar  #Sync\n"
 853         : /* no outputs */
 854         : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
 855         : "g1", "g2");
 856 }
 857
 858 void init_irqwork_curcpu(void)
 859 {
 860         int cpu = hard_smp_processor_id();
 861
 862         memset(__irq_work + cpu, 0, sizeof(struct irq_work_struct));
 863 }
 864
 865 static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type)
 866 {
 867         register unsigned long func __asm__("%o5");
 868         register unsigned long arg0 __asm__("%o0");
 869         register unsigned long arg1 __asm__("%o1");
 870         register unsigned long arg2 __asm__("%o2");
 871
 872         func = HV_FAST_CPU_QCONF;
 873         arg0 = type;
 874         arg1 = paddr;
 875         arg2 = 128; /* XXX Implied by Niagara queue offsets. XXX */
 876         __asm__ __volatile__("ta        %8"
 877                              : "=&r" (func), "=&r" (arg0),
 878                                "=&r" (arg1), "=&r" (arg2)
 879                              : "0" (func), "1" (arg0),
 880                                "2" (arg1), "3" (arg2),
 881                                "i" (HV_FAST_TRAP));
 882
 883         if (arg0 != HV_EOK) {
 884                 prom_printf("SUN4V: cpu_qconf(%lu) failed with error %lu\n",
 885                             type, func);
 886                 prom_halt();
 887         }
 888 }
 889
 890 static void __cpuinit sun4v_register_mondo_queues(int this_cpu)
 891 {
 892         struct trap_per_cpu *tb = &trap_block[this_cpu];
 893
 894         register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO);
 895         register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO);
 896         register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR);
 897         register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR);
 898 }
 899
 900 static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, int use_bootmem)
 901 {
 902         void *page;
 903
 904         if (use_bootmem)
 905                 page = alloc_bootmem_low_pages(PAGE_SIZE);
 906         else
 907                 page = (void *) get_zeroed_page(GFP_ATOMIC);
 908
 909         if (!page) {
 910                 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
 911                 prom_halt();
 912         }
 913
 914         *pa_ptr = __pa(page);
 915 }
 916
 917 static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, int use_bootmem)
 918 {
 919         void *page;
 920
 921         if (use_bootmem)
 922                 page = alloc_bootmem_low_pages(PAGE_SIZE);
 923         else
 924                 page = (void *) get_zeroed_page(GFP_ATOMIC);
 925
 926         if (!page) {
 927                 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
 928                 prom_halt();
 929         }
 930
 931         *pa_ptr = __pa(page);
 932 }
 933
 934 static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem)
 935 {
 936 #ifdef CONFIG_SMP
 937         void *page;
 938
 939         BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
 940
 941         if (use_bootmem)
 942                 page = alloc_bootmem_low_pages(PAGE_SIZE);
 943         else
 944                 page = (void *) get_zeroed_page(GFP_ATOMIC);
 945
 946         if (!page) {
 947                 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
 948                 prom_halt();
 949         }
 950
 951         tb->cpu_mondo_block_pa = __pa(page);
 952         tb->cpu_list_pa = __pa(page + 64);
 953 #endif
 954 }
 955
 956 /* Allocate and register the mondo and error queues for this cpu.  */
 957 void __cpuinit sun4v_init_mondo_queues(int use_bootmem)
 958 {
 959         int cpu = hard_smp_processor_id();
 960         struct trap_per_cpu *tb = &trap_block[cpu];
 961
 962         alloc_one_mondo(&tb->cpu_mondo_pa, use_bootmem);
 963         alloc_one_mondo(&tb->dev_mondo_pa, use_bootmem);
 964         alloc_one_mondo(&tb->resum_mondo_pa, use_bootmem);
 965         alloc_one_kbuf(&tb->resum_kernel_buf_pa, use_bootmem);
 966         alloc_one_mondo(&tb->nonresum_mondo_pa, use_bootmem);
 967         alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, use_bootmem);
 968
 969         init_cpu_send_mondo_info(tb, use_bootmem);
 970
 971         sun4v_register_mondo_queues(cpu);
 972 }
 973
 974 /* Only invoked on boot processor. */
 975 void __init init_IRQ(void)
 976 {
 977         map_prom_timers();
 978         kill_prom_timer();
 979         memset(&ivector_table[0], 0, sizeof(ivector_table));
 980
 981         if (tlb_type == hypervisor)
 982                 sun4v_init_mondo_queues(1);
 983
 984         /* We need to clear any IRQ's pending in the soft interrupt
 985          * registers, a spurious one could be left around from the
 986          * PROM timer which we just disabled.
 987          */
 988         clear_softint(get_softint());
 989
 990         /* Now that ivector table is initialized, it is safe
 991          * to receive IRQ vector traps.  We will normally take
 992          * one or two right now, in case some device PROM used
 993          * to boot us wants to speak to us.  We just ignore them.
 994          */
 995         __asm__ __volatile__("rdpr      %%pstate, %%g1\n\t"
 996                              "or        %%g1, %0, %%g1\n\t"
 997                              "wrpr      %%g1, 0x0, %%pstate"
 998                              : /* No outputs */
 999                              : "i" (PSTATE_IE)
1000                              : "g1");
1001 }
1002
1003 static struct proc_dir_entry * root_irq_dir;
1004 static struct proc_dir_entry * irq_dir [NUM_IVECS];
1005
1006 #ifdef CONFIG_SMP
1007
1008 static int irq_affinity_read_proc (char *page, char **start, off_t off,
1009                         int count, int *eof, void *data)
1010 {
1011         struct ino_bucket *bp = ivector_table + (long)data;
1012         struct irq_desc *desc = bp->irq_info;
1013         struct irqaction *ap = desc->action;
1014         cpumask_t mask;
1015         int len;
1016
1017         mask = get_smpaff_in_irqaction(ap);
1018         if (cpus_empty(mask))
1019                 mask = cpu_online_map;
1020
1021         len = cpumask_scnprintf(page, count, mask);
1022         if (count - len < 2)
1023                 return -EINVAL;
1024         len += sprintf(page + len, "\n");
1025         return len;
1026 }
1027
1028 static inline void set_intr_affinity(int irq, cpumask_t hw_aff)
1029 {
1030         struct ino_bucket *bp = ivector_table + irq;
1031         struct irq_desc *desc = bp->irq_info;
1032         struct irqaction *ap = desc->action;
1033
1034         /* Users specify affinity in terms of hw cpu ids.
1035          * As soon as we do this, handler_irq() might see and take action.
1036          */
1037         put_smpaff_in_irqaction(ap, hw_aff);
1038
1039         /* Migration is simply done by the next cpu to service this
1040          * interrupt.
1041          */
1042 }
1043
1044 static int irq_affinity_write_proc (struct file *file, const char __user *buffer,
1045                                         unsigned long count, void *data)
1046 {
1047         int irq = (long) data, full_count = count, err;
1048         cpumask_t new_value;
1049
1050         err = cpumask_parse(buffer, count, new_value);
1051
1052         /*
1053          * Do not allow disabling IRQs completely - it's a too easy
1054          * way to make the system unusable accidentally :-) At least
1055          * one online CPU still has to be targeted.
1056          */
1057         cpus_and(new_value, new_value, cpu_online_map);
1058         if (cpus_empty(new_value))
1059                 return -EINVAL;
1060
1061         set_intr_affinity(irq, new_value);
1062
1063         return full_count;
1064 }
1065
1066 #endif
1067
1068 #define MAX_NAMELEN 10
1069
1070 static void register_irq_proc (unsigned int irq)
1071 {
1072         char name [MAX_NAMELEN];
1073
1074         if (!root_irq_dir || irq_dir[irq])
1075                 return;
1076
1077         memset(name, 0, MAX_NAMELEN);
1078         sprintf(name, "%x", irq);
1079
1080         /* create /proc/irq/1234 */
1081         irq_dir[irq] = proc_mkdir(name, root_irq_dir);
1082
1083 #ifdef CONFIG_SMP
1084         /* XXX SMP affinity not supported on starfire yet. */
1085         if (this_is_starfire == 0) {
1086                 struct proc_dir_entry *entry;
1087
1088                 /* create /proc/irq/1234/smp_affinity */
1089                 entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]);
1090
1091                 if (entry) {
1092                         entry->nlink = 1;
1093                         entry->data = (void *)(long)irq;
1094                         entry->read_proc = irq_affinity_read_proc;
1095                         entry->write_proc = irq_affinity_write_proc;
1096                 }
1097         }
1098 #endif
1099 }
1100
1101 void init_irq_proc (void)
1102 {
1103         /* create /proc/irq */
1104         root_irq_dir = proc_mkdir("irq", NULL);
1105 }
1106