/home/lenb/src/to-linus-stable branch 'acpi-2.6.12'
[linux-2.6] / arch / i386 / kernel / io_apic.c
1 /*
2  *      Intel IO-APIC support for multi-Pentium hosts.
3  *
4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5  *
6  *      Many thanks to Stig Venaas for trying out countless experimental
7  *      patches and reporting/debugging problems patiently!
8  *
9  *      (c) 1999, Multiple IO-APIC support, developed by
10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
13  *      and Ingo Molnar <mingo@redhat.com>
14  *
15  *      Fixes
16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
17  *                                      thanks to Eric Gilmore
18  *                                      and Rolf G. Tews
19  *                                      for testing these extensively
20  *      Paul Diefenbaugh        :       Added full ACPI support
21  */
22
23 #include <linux/mm.h>
24 #include <linux/irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/sched.h>
29 #include <linux/config.h>
30 #include <linux/smp_lock.h>
31 #include <linux/mc146818rtc.h>
32 #include <linux/compiler.h>
33 #include <linux/acpi.h>
34 #include <linux/module.h>
35 #include <linux/sysdev.h>
36 #include <asm/io.h>
37 #include <asm/smp.h>
38 #include <asm/desc.h>
39 #include <asm/timer.h>
40 #include <asm/i8259.h>
41
42 #include <mach_apic.h>
43
44 #include "io_ports.h"
45
46 int (*ioapic_renumber_irq)(int ioapic, int irq);
47 atomic_t irq_mis_count;
48
49 static DEFINE_SPINLOCK(ioapic_lock);
50
51 /*
52  *      Is the SiS APIC rmw bug present ?
53  *      -1 = don't know, 0 = no, 1 = yes
54  */
55 int sis_apic_bug = -1;
56
57 /*
58  * # of IRQ routing registers
59  */
60 int nr_ioapic_registers[MAX_IO_APICS];
61
62 /*
63  * Rough estimation of how many shared IRQs there are, can
64  * be changed anytime.
65  */
66 #define MAX_PLUS_SHARED_IRQS NR_IRQS
67 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
68
69 /*
70  * This is performance-critical, we want to do it O(1)
71  *
72  * the indexing order of this array favors 1:1 mappings
73  * between pins and IRQs.
74  */
75
76 static struct irq_pin_list {
77         int apic, pin, next;
78 } irq_2_pin[PIN_MAP_SIZE];
79
80 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
81 #ifdef CONFIG_PCI_MSI
82 #define vector_to_irq(vector)   \
83         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
84 #else
85 #define vector_to_irq(vector)   (vector)
86 #endif
87
88 /*
89  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
90  * shared ISA-space IRQs, so we have to support them. We are super
91  * fast in the common case, and fast for shared ISA-space IRQs.
92  */
93 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
94 {
95         static int first_free_entry = NR_IRQS;
96         struct irq_pin_list *entry = irq_2_pin + irq;
97
98         while (entry->next)
99                 entry = irq_2_pin + entry->next;
100
101         if (entry->pin != -1) {
102                 entry->next = first_free_entry;
103                 entry = irq_2_pin + entry->next;
104                 if (++first_free_entry >= PIN_MAP_SIZE)
105                         panic("io_apic.c: whoops");
106         }
107         entry->apic = apic;
108         entry->pin = pin;
109 }
110
111 /*
112  * Reroute an IRQ to a different pin.
113  */
114 static void __init replace_pin_at_irq(unsigned int irq,
115                                       int oldapic, int oldpin,
116                                       int newapic, int newpin)
117 {
118         struct irq_pin_list *entry = irq_2_pin + irq;
119
120         while (1) {
121                 if (entry->apic == oldapic && entry->pin == oldpin) {
122                         entry->apic = newapic;
123                         entry->pin = newpin;
124                 }
125                 if (!entry->next)
126                         break;
127                 entry = irq_2_pin + entry->next;
128         }
129 }
130
131 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
132 {
133         struct irq_pin_list *entry = irq_2_pin + irq;
134         unsigned int pin, reg;
135
136         for (;;) {
137                 pin = entry->pin;
138                 if (pin == -1)
139                         break;
140                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
141                 reg &= ~disable;
142                 reg |= enable;
143                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
144                 if (!entry->next)
145                         break;
146                 entry = irq_2_pin + entry->next;
147         }
148 }
149
150 /* mask = 1 */
151 static void __mask_IO_APIC_irq (unsigned int irq)
152 {
153         __modify_IO_APIC_irq(irq, 0x00010000, 0);
154 }
155
156 /* mask = 0 */
157 static void __unmask_IO_APIC_irq (unsigned int irq)
158 {
159         __modify_IO_APIC_irq(irq, 0, 0x00010000);
160 }
161
162 /* mask = 1, trigger = 0 */
163 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
164 {
165         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
166 }
167
168 /* mask = 0, trigger = 1 */
169 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
170 {
171         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
172 }
173
174 static void mask_IO_APIC_irq (unsigned int irq)
175 {
176         unsigned long flags;
177
178         spin_lock_irqsave(&ioapic_lock, flags);
179         __mask_IO_APIC_irq(irq);
180         spin_unlock_irqrestore(&ioapic_lock, flags);
181 }
182
183 static void unmask_IO_APIC_irq (unsigned int irq)
184 {
185         unsigned long flags;
186
187         spin_lock_irqsave(&ioapic_lock, flags);
188         __unmask_IO_APIC_irq(irq);
189         spin_unlock_irqrestore(&ioapic_lock, flags);
190 }
191
192 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
193 {
194         struct IO_APIC_route_entry entry;
195         unsigned long flags;
196         
197         /* Check delivery_mode to be sure we're not clearing an SMI pin */
198         spin_lock_irqsave(&ioapic_lock, flags);
199         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
200         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
201         spin_unlock_irqrestore(&ioapic_lock, flags);
202         if (entry.delivery_mode == dest_SMI)
203                 return;
204
205         /*
206          * Disable it in the IO-APIC irq-routing table:
207          */
208         memset(&entry, 0, sizeof(entry));
209         entry.mask = 1;
210         spin_lock_irqsave(&ioapic_lock, flags);
211         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
212         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
213         spin_unlock_irqrestore(&ioapic_lock, flags);
214 }
215
216 static void clear_IO_APIC (void)
217 {
218         int apic, pin;
219
220         for (apic = 0; apic < nr_ioapics; apic++)
221                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
222                         clear_IO_APIC_pin(apic, pin);
223 }
224
225 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
226 {
227         unsigned long flags;
228         int pin;
229         struct irq_pin_list *entry = irq_2_pin + irq;
230         unsigned int apicid_value;
231         
232         apicid_value = cpu_mask_to_apicid(cpumask);
233         /* Prepare to do the io_apic_write */
234         apicid_value = apicid_value << 24;
235         spin_lock_irqsave(&ioapic_lock, flags);
236         for (;;) {
237                 pin = entry->pin;
238                 if (pin == -1)
239                         break;
240                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
241                 if (!entry->next)
242                         break;
243                 entry = irq_2_pin + entry->next;
244         }
245         spin_unlock_irqrestore(&ioapic_lock, flags);
246 }
247
248 #if defined(CONFIG_IRQBALANCE)
249 # include <asm/processor.h>     /* kernel_thread() */
250 # include <linux/kernel_stat.h> /* kstat */
251 # include <linux/slab.h>                /* kmalloc() */
252 # include <linux/timer.h>       /* time_after() */
253  
254 # ifdef CONFIG_BALANCED_IRQ_DEBUG
255 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
256 #  define Dprintk(x...) do { TDprintk(x); } while (0)
257 # else
258 #  define TDprintk(x...) 
259 #  define Dprintk(x...) 
260 # endif
261
262 cpumask_t __cacheline_aligned pending_irq_balance_cpumask[NR_IRQS];
263
264 #define IRQBALANCE_CHECK_ARCH -999
265 static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
266 static int physical_balance = 0;
267
268 static struct irq_cpu_info {
269         unsigned long * last_irq;
270         unsigned long * irq_delta;
271         unsigned long irq;
272 } irq_cpu_data[NR_CPUS];
273
274 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
275 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
276 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
277
278 #define IDLE_ENOUGH(cpu,now) \
279         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
280
281 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
282
283 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
284
285 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
286 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
287 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
288 #define BALANCED_IRQ_LESS_DELTA         (HZ)
289
290 static long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
291
292 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
293                         unsigned long now, int direction)
294 {
295         int search_idle = 1;
296         int cpu = curr_cpu;
297
298         goto inside;
299
300         do {
301                 if (unlikely(cpu == curr_cpu))
302                         search_idle = 0;
303 inside:
304                 if (direction == 1) {
305                         cpu++;
306                         if (cpu >= NR_CPUS)
307                                 cpu = 0;
308                 } else {
309                         cpu--;
310                         if (cpu == -1)
311                                 cpu = NR_CPUS-1;
312                 }
313         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
314                         (search_idle && !IDLE_ENOUGH(cpu,now)));
315
316         return cpu;
317 }
318
319 static inline void balance_irq(int cpu, int irq)
320 {
321         unsigned long now = jiffies;
322         cpumask_t allowed_mask;
323         unsigned int new_cpu;
324                 
325         if (irqbalance_disabled)
326                 return; 
327
328         cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
329         new_cpu = move(cpu, allowed_mask, now, 1);
330         if (cpu != new_cpu) {
331                 irq_desc_t *desc = irq_desc + irq;
332                 unsigned long flags;
333
334                 spin_lock_irqsave(&desc->lock, flags);
335                 pending_irq_balance_cpumask[irq] = cpumask_of_cpu(new_cpu);
336                 spin_unlock_irqrestore(&desc->lock, flags);
337         }
338 }
339
340 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
341 {
342         int i, j;
343         Dprintk("Rotating IRQs among CPUs.\n");
344         for (i = 0; i < NR_CPUS; i++) {
345                 for (j = 0; cpu_online(i) && (j < NR_IRQS); j++) {
346                         if (!irq_desc[j].action)
347                                 continue;
348                         /* Is it a significant load ?  */
349                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
350                                                 useful_load_threshold)
351                                 continue;
352                         balance_irq(i, j);
353                 }
354         }
355         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
356                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);       
357         return;
358 }
359
360 static void do_irq_balance(void)
361 {
362         int i, j;
363         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
364         unsigned long move_this_load = 0;
365         int max_loaded = 0, min_loaded = 0;
366         int load;
367         unsigned long useful_load_threshold = balanced_irq_interval + 10;
368         int selected_irq;
369         int tmp_loaded, first_attempt = 1;
370         unsigned long tmp_cpu_irq;
371         unsigned long imbalance = 0;
372         cpumask_t allowed_mask, target_cpu_mask, tmp;
373
374         for (i = 0; i < NR_CPUS; i++) {
375                 int package_index;
376                 CPU_IRQ(i) = 0;
377                 if (!cpu_online(i))
378                         continue;
379                 package_index = CPU_TO_PACKAGEINDEX(i);
380                 for (j = 0; j < NR_IRQS; j++) {
381                         unsigned long value_now, delta;
382                         /* Is this an active IRQ? */
383                         if (!irq_desc[j].action)
384                                 continue;
385                         if ( package_index == i )
386                                 IRQ_DELTA(package_index,j) = 0;
387                         /* Determine the total count per processor per IRQ */
388                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
389
390                         /* Determine the activity per processor per IRQ */
391                         delta = value_now - LAST_CPU_IRQ(i,j);
392
393                         /* Update last_cpu_irq[][] for the next time */
394                         LAST_CPU_IRQ(i,j) = value_now;
395
396                         /* Ignore IRQs whose rate is less than the clock */
397                         if (delta < useful_load_threshold)
398                                 continue;
399                         /* update the load for the processor or package total */
400                         IRQ_DELTA(package_index,j) += delta;
401
402                         /* Keep track of the higher numbered sibling as well */
403                         if (i != package_index)
404                                 CPU_IRQ(i) += delta;
405                         /*
406                          * We have sibling A and sibling B in the package
407                          *
408                          * cpu_irq[A] = load for cpu A + load for cpu B
409                          * cpu_irq[B] = load for cpu B
410                          */
411                         CPU_IRQ(package_index) += delta;
412                 }
413         }
414         /* Find the least loaded processor package */
415         for (i = 0; i < NR_CPUS; i++) {
416                 if (!cpu_online(i))
417                         continue;
418                 if (i != CPU_TO_PACKAGEINDEX(i))
419                         continue;
420                 if (min_cpu_irq > CPU_IRQ(i)) {
421                         min_cpu_irq = CPU_IRQ(i);
422                         min_loaded = i;
423                 }
424         }
425         max_cpu_irq = ULONG_MAX;
426
427 tryanothercpu:
428         /* Look for heaviest loaded processor.
429          * We may come back to get the next heaviest loaded processor.
430          * Skip processors with trivial loads.
431          */
432         tmp_cpu_irq = 0;
433         tmp_loaded = -1;
434         for (i = 0; i < NR_CPUS; i++) {
435                 if (!cpu_online(i))
436                         continue;
437                 if (i != CPU_TO_PACKAGEINDEX(i))
438                         continue;
439                 if (max_cpu_irq <= CPU_IRQ(i)) 
440                         continue;
441                 if (tmp_cpu_irq < CPU_IRQ(i)) {
442                         tmp_cpu_irq = CPU_IRQ(i);
443                         tmp_loaded = i;
444                 }
445         }
446
447         if (tmp_loaded == -1) {
448          /* In the case of small number of heavy interrupt sources, 
449           * loading some of the cpus too much. We use Ingo's original 
450           * approach to rotate them around.
451           */
452                 if (!first_attempt && imbalance >= useful_load_threshold) {
453                         rotate_irqs_among_cpus(useful_load_threshold);
454                         return;
455                 }
456                 goto not_worth_the_effort;
457         }
458         
459         first_attempt = 0;              /* heaviest search */
460         max_cpu_irq = tmp_cpu_irq;      /* load */
461         max_loaded = tmp_loaded;        /* processor */
462         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
463         
464         Dprintk("max_loaded cpu = %d\n", max_loaded);
465         Dprintk("min_loaded cpu = %d\n", min_loaded);
466         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
467         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
468         Dprintk("load imbalance = %lu\n", imbalance);
469
470         /* if imbalance is less than approx 10% of max load, then
471          * observe diminishing returns action. - quit
472          */
473         if (imbalance < (max_cpu_irq >> 3)) {
474                 Dprintk("Imbalance too trivial\n");
475                 goto not_worth_the_effort;
476         }
477
478 tryanotherirq:
479         /* if we select an IRQ to move that can't go where we want, then
480          * see if there is another one to try.
481          */
482         move_this_load = 0;
483         selected_irq = -1;
484         for (j = 0; j < NR_IRQS; j++) {
485                 /* Is this an active IRQ? */
486                 if (!irq_desc[j].action)
487                         continue;
488                 if (imbalance <= IRQ_DELTA(max_loaded,j))
489                         continue;
490                 /* Try to find the IRQ that is closest to the imbalance
491                  * without going over.
492                  */
493                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
494                         move_this_load = IRQ_DELTA(max_loaded,j);
495                         selected_irq = j;
496                 }
497         }
498         if (selected_irq == -1) {
499                 goto tryanothercpu;
500         }
501
502         imbalance = move_this_load;
503         
504         /* For physical_balance case, we accumlated both load
505          * values in the one of the siblings cpu_irq[],
506          * to use the same code for physical and logical processors
507          * as much as possible. 
508          *
509          * NOTE: the cpu_irq[] array holds the sum of the load for
510          * sibling A and sibling B in the slot for the lowest numbered
511          * sibling (A), _AND_ the load for sibling B in the slot for
512          * the higher numbered sibling.
513          *
514          * We seek the least loaded sibling by making the comparison
515          * (A+B)/2 vs B
516          */
517         load = CPU_IRQ(min_loaded) >> 1;
518         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
519                 if (load > CPU_IRQ(j)) {
520                         /* This won't change cpu_sibling_map[min_loaded] */
521                         load = CPU_IRQ(j);
522                         min_loaded = j;
523                 }
524         }
525
526         cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
527         target_cpu_mask = cpumask_of_cpu(min_loaded);
528         cpus_and(tmp, target_cpu_mask, allowed_mask);
529
530         if (!cpus_empty(tmp)) {
531                 irq_desc_t *desc = irq_desc + selected_irq;
532                 unsigned long flags;
533
534                 Dprintk("irq = %d moved to cpu = %d\n",
535                                 selected_irq, min_loaded);
536                 /* mark for change destination */
537                 spin_lock_irqsave(&desc->lock, flags);
538                 pending_irq_balance_cpumask[selected_irq] =
539                                         cpumask_of_cpu(min_loaded);
540                 spin_unlock_irqrestore(&desc->lock, flags);
541                 /* Since we made a change, come back sooner to 
542                  * check for more variation.
543                  */
544                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
545                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);       
546                 return;
547         }
548         goto tryanotherirq;
549
550 not_worth_the_effort:
551         /*
552          * if we did not find an IRQ to move, then adjust the time interval
553          * upward
554          */
555         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
556                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);       
557         Dprintk("IRQ worth rotating not found\n");
558         return;
559 }
560
561 static int balanced_irq(void *unused)
562 {
563         int i;
564         unsigned long prev_balance_time = jiffies;
565         long time_remaining = balanced_irq_interval;
566
567         daemonize("kirqd");
568         
569         /* push everything to CPU 0 to give us a starting point.  */
570         for (i = 0 ; i < NR_IRQS ; i++) {
571                 pending_irq_balance_cpumask[i] = cpumask_of_cpu(0);
572         }
573
574         for ( ; ; ) {
575                 set_current_state(TASK_INTERRUPTIBLE);
576                 time_remaining = schedule_timeout(time_remaining);
577                 try_to_freeze();
578                 if (time_after(jiffies,
579                                 prev_balance_time+balanced_irq_interval)) {
580                         preempt_disable();
581                         do_irq_balance();
582                         prev_balance_time = jiffies;
583                         time_remaining = balanced_irq_interval;
584                         preempt_enable();
585                 }
586         }
587         return 0;
588 }
589
590 static int __init balanced_irq_init(void)
591 {
592         int i;
593         struct cpuinfo_x86 *c;
594         cpumask_t tmp;
595
596         cpus_shift_right(tmp, cpu_online_map, 2);
597         c = &boot_cpu_data;
598         /* When not overwritten by the command line ask subarchitecture. */
599         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
600                 irqbalance_disabled = NO_BALANCE_IRQ;
601         if (irqbalance_disabled)
602                 return 0;
603         
604          /* disable irqbalance completely if there is only one processor online */
605         if (num_online_cpus() < 2) {
606                 irqbalance_disabled = 1;
607                 return 0;
608         }
609         /*
610          * Enable physical balance only if more than 1 physical processor
611          * is present
612          */
613         if (smp_num_siblings > 1 && !cpus_empty(tmp))
614                 physical_balance = 1;
615
616         for (i = 0; i < NR_CPUS; i++) {
617                 if (!cpu_online(i))
618                         continue;
619                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
620                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
621                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
622                         printk(KERN_ERR "balanced_irq_init: out of memory");
623                         goto failed;
624                 }
625                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
626                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
627         }
628         
629         printk(KERN_INFO "Starting balanced_irq\n");
630         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0) 
631                 return 0;
632         else 
633                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
634 failed:
635         for (i = 0; i < NR_CPUS; i++) {
636                 kfree(irq_cpu_data[i].irq_delta);
637                 kfree(irq_cpu_data[i].last_irq);
638         }
639         return 0;
640 }
641
642 int __init irqbalance_disable(char *str)
643 {
644         irqbalance_disabled = 1;
645         return 0;
646 }
647
648 __setup("noirqbalance", irqbalance_disable);
649
650 static inline void move_irq(int irq)
651 {
652         /* note - we hold the desc->lock */
653         if (unlikely(!cpus_empty(pending_irq_balance_cpumask[irq]))) {
654                 set_ioapic_affinity_irq(irq, pending_irq_balance_cpumask[irq]);
655                 cpus_clear(pending_irq_balance_cpumask[irq]);
656         }
657 }
658
659 late_initcall(balanced_irq_init);
660
661 #else /* !CONFIG_IRQBALANCE */
662 static inline void move_irq(int irq) { }
663 #endif /* CONFIG_IRQBALANCE */
664
665 #ifndef CONFIG_SMP
666 void fastcall send_IPI_self(int vector)
667 {
668         unsigned int cfg;
669
670         /*
671          * Wait for idle.
672          */
673         apic_wait_icr_idle();
674         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
675         /*
676          * Send the IPI. The write to APIC_ICR fires this off.
677          */
678         apic_write_around(APIC_ICR, cfg);
679 }
680 #endif /* !CONFIG_SMP */
681
682
683 /*
684  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
685  * specific CPU-side IRQs.
686  */
687
688 #define MAX_PIRQS 8
689 static int pirq_entries [MAX_PIRQS];
690 static int pirqs_enabled;
691 int skip_ioapic_setup;
692
693 static int __init ioapic_setup(char *str)
694 {
695         skip_ioapic_setup = 1;
696         return 1;
697 }
698
699 __setup("noapic", ioapic_setup);
700
701 static int __init ioapic_pirq_setup(char *str)
702 {
703         int i, max;
704         int ints[MAX_PIRQS+1];
705
706         get_options(str, ARRAY_SIZE(ints), ints);
707
708         for (i = 0; i < MAX_PIRQS; i++)
709                 pirq_entries[i] = -1;
710
711         pirqs_enabled = 1;
712         apic_printk(APIC_VERBOSE, KERN_INFO
713                         "PIRQ redirection, working around broken MP-BIOS.\n");
714         max = MAX_PIRQS;
715         if (ints[0] < MAX_PIRQS)
716                 max = ints[0];
717
718         for (i = 0; i < max; i++) {
719                 apic_printk(APIC_VERBOSE, KERN_DEBUG
720                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
721                 /*
722                  * PIRQs are mapped upside down, usually.
723                  */
724                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
725         }
726         return 1;
727 }
728
729 __setup("pirq=", ioapic_pirq_setup);
730
731 /*
732  * Find the IRQ entry number of a certain pin.
733  */
734 static int find_irq_entry(int apic, int pin, int type)
735 {
736         int i;
737
738         for (i = 0; i < mp_irq_entries; i++)
739                 if (mp_irqs[i].mpc_irqtype == type &&
740                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
741                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
742                     mp_irqs[i].mpc_dstirq == pin)
743                         return i;
744
745         return -1;
746 }
747
748 /*
749  * Find the pin to which IRQ[irq] (ISA) is connected
750  */
751 static int find_isa_irq_pin(int irq, int type)
752 {
753         int i;
754
755         for (i = 0; i < mp_irq_entries; i++) {
756                 int lbus = mp_irqs[i].mpc_srcbus;
757
758                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
759                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
760                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
761                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
762                     ) &&
763                     (mp_irqs[i].mpc_irqtype == type) &&
764                     (mp_irqs[i].mpc_srcbusirq == irq))
765
766                         return mp_irqs[i].mpc_dstirq;
767         }
768         return -1;
769 }
770
771 /*
772  * Find a specific PCI IRQ entry.
773  * Not an __init, possibly needed by modules
774  */
775 static int pin_2_irq(int idx, int apic, int pin);
776
777 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
778 {
779         int apic, i, best_guess = -1;
780
781         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
782                 "slot:%d, pin:%d.\n", bus, slot, pin);
783         if (mp_bus_id_to_pci_bus[bus] == -1) {
784                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
785                 return -1;
786         }
787         for (i = 0; i < mp_irq_entries; i++) {
788                 int lbus = mp_irqs[i].mpc_srcbus;
789
790                 for (apic = 0; apic < nr_ioapics; apic++)
791                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
792                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
793                                 break;
794
795                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
796                     !mp_irqs[i].mpc_irqtype &&
797                     (bus == lbus) &&
798                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
799                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
800
801                         if (!(apic || IO_APIC_IRQ(irq)))
802                                 continue;
803
804                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
805                                 return irq;
806                         /*
807                          * Use the first all-but-pin matching entry as a
808                          * best-guess fuzzy result for broken mptables.
809                          */
810                         if (best_guess < 0)
811                                 best_guess = irq;
812                 }
813         }
814         return best_guess;
815 }
816 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
817
818 /*
819  * This function currently is only a helper for the i386 smp boot process where 
820  * we need to reprogram the ioredtbls to cater for the cpus which have come online
821  * so mask in all cases should simply be TARGET_CPUS
822  */
823 void __init setup_ioapic_dest(void)
824 {
825         int pin, ioapic, irq, irq_entry;
826
827         if (skip_ioapic_setup == 1)
828                 return;
829
830         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
831                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
832                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
833                         if (irq_entry == -1)
834                                 continue;
835                         irq = pin_2_irq(irq_entry, ioapic, pin);
836                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
837                 }
838
839         }
840 }
841
842 /*
843  * EISA Edge/Level control register, ELCR
844  */
845 static int EISA_ELCR(unsigned int irq)
846 {
847         if (irq < 16) {
848                 unsigned int port = 0x4d0 + (irq >> 3);
849                 return (inb(port) >> (irq & 7)) & 1;
850         }
851         apic_printk(APIC_VERBOSE, KERN_INFO
852                         "Broken MPtable reports ISA irq %d\n", irq);
853         return 0;
854 }
855
856 /* EISA interrupts are always polarity zero and can be edge or level
857  * trigger depending on the ELCR value.  If an interrupt is listed as
858  * EISA conforming in the MP table, that means its trigger type must
859  * be read in from the ELCR */
860
861 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
862 #define default_EISA_polarity(idx)      (0)
863
864 /* ISA interrupts are always polarity zero edge triggered,
865  * when listed as conforming in the MP table. */
866
867 #define default_ISA_trigger(idx)        (0)
868 #define default_ISA_polarity(idx)       (0)
869
870 /* PCI interrupts are always polarity one level triggered,
871  * when listed as conforming in the MP table. */
872
873 #define default_PCI_trigger(idx)        (1)
874 #define default_PCI_polarity(idx)       (1)
875
876 /* MCA interrupts are always polarity zero level triggered,
877  * when listed as conforming in the MP table. */
878
879 #define default_MCA_trigger(idx)        (1)
880 #define default_MCA_polarity(idx)       (0)
881
882 /* NEC98 interrupts are always polarity zero edge triggered,
883  * when listed as conforming in the MP table. */
884
885 #define default_NEC98_trigger(idx)     (0)
886 #define default_NEC98_polarity(idx)    (0)
887
888 static int __init MPBIOS_polarity(int idx)
889 {
890         int bus = mp_irqs[idx].mpc_srcbus;
891         int polarity;
892
893         /*
894          * Determine IRQ line polarity (high active or low active):
895          */
896         switch (mp_irqs[idx].mpc_irqflag & 3)
897         {
898                 case 0: /* conforms, ie. bus-type dependent polarity */
899                 {
900                         switch (mp_bus_id_to_type[bus])
901                         {
902                                 case MP_BUS_ISA: /* ISA pin */
903                                 {
904                                         polarity = default_ISA_polarity(idx);
905                                         break;
906                                 }
907                                 case MP_BUS_EISA: /* EISA pin */
908                                 {
909                                         polarity = default_EISA_polarity(idx);
910                                         break;
911                                 }
912                                 case MP_BUS_PCI: /* PCI pin */
913                                 {
914                                         polarity = default_PCI_polarity(idx);
915                                         break;
916                                 }
917                                 case MP_BUS_MCA: /* MCA pin */
918                                 {
919                                         polarity = default_MCA_polarity(idx);
920                                         break;
921                                 }
922                                 case MP_BUS_NEC98: /* NEC 98 pin */
923                                 {
924                                         polarity = default_NEC98_polarity(idx);
925                                         break;
926                                 }
927                                 default:
928                                 {
929                                         printk(KERN_WARNING "broken BIOS!!\n");
930                                         polarity = 1;
931                                         break;
932                                 }
933                         }
934                         break;
935                 }
936                 case 1: /* high active */
937                 {
938                         polarity = 0;
939                         break;
940                 }
941                 case 2: /* reserved */
942                 {
943                         printk(KERN_WARNING "broken BIOS!!\n");
944                         polarity = 1;
945                         break;
946                 }
947                 case 3: /* low active */
948                 {
949                         polarity = 1;
950                         break;
951                 }
952                 default: /* invalid */
953                 {
954                         printk(KERN_WARNING "broken BIOS!!\n");
955                         polarity = 1;
956                         break;
957                 }
958         }
959         return polarity;
960 }
961
962 static int MPBIOS_trigger(int idx)
963 {
964         int bus = mp_irqs[idx].mpc_srcbus;
965         int trigger;
966
967         /*
968          * Determine IRQ trigger mode (edge or level sensitive):
969          */
970         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
971         {
972                 case 0: /* conforms, ie. bus-type dependent */
973                 {
974                         switch (mp_bus_id_to_type[bus])
975                         {
976                                 case MP_BUS_ISA: /* ISA pin */
977                                 {
978                                         trigger = default_ISA_trigger(idx);
979                                         break;
980                                 }
981                                 case MP_BUS_EISA: /* EISA pin */
982                                 {
983                                         trigger = default_EISA_trigger(idx);
984                                         break;
985                                 }
986                                 case MP_BUS_PCI: /* PCI pin */
987                                 {
988                                         trigger = default_PCI_trigger(idx);
989                                         break;
990                                 }
991                                 case MP_BUS_MCA: /* MCA pin */
992                                 {
993                                         trigger = default_MCA_trigger(idx);
994                                         break;
995                                 }
996                                 case MP_BUS_NEC98: /* NEC 98 pin */
997                                 {
998                                         trigger = default_NEC98_trigger(idx);
999                                         break;
1000                                 }
1001                                 default:
1002                                 {
1003                                         printk(KERN_WARNING "broken BIOS!!\n");
1004                                         trigger = 1;
1005                                         break;
1006                                 }
1007                         }
1008                         break;
1009                 }
1010                 case 1: /* edge */
1011                 {
1012                         trigger = 0;
1013                         break;
1014                 }
1015                 case 2: /* reserved */
1016                 {
1017                         printk(KERN_WARNING "broken BIOS!!\n");
1018                         trigger = 1;
1019                         break;
1020                 }
1021                 case 3: /* level */
1022                 {
1023                         trigger = 1;
1024                         break;
1025                 }
1026                 default: /* invalid */
1027                 {
1028                         printk(KERN_WARNING "broken BIOS!!\n");
1029                         trigger = 0;
1030                         break;
1031                 }
1032         }
1033         return trigger;
1034 }
1035
1036 static inline int irq_polarity(int idx)
1037 {
1038         return MPBIOS_polarity(idx);
1039 }
1040
1041 static inline int irq_trigger(int idx)
1042 {
1043         return MPBIOS_trigger(idx);
1044 }
1045
1046 static int pin_2_irq(int idx, int apic, int pin)
1047 {
1048         int irq, i;
1049         int bus = mp_irqs[idx].mpc_srcbus;
1050
1051         /*
1052          * Debugging check, we are in big trouble if this message pops up!
1053          */
1054         if (mp_irqs[idx].mpc_dstirq != pin)
1055                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1056
1057         switch (mp_bus_id_to_type[bus])
1058         {
1059                 case MP_BUS_ISA: /* ISA pin */
1060                 case MP_BUS_EISA:
1061                 case MP_BUS_MCA:
1062                 case MP_BUS_NEC98:
1063                 {
1064                         irq = mp_irqs[idx].mpc_srcbusirq;
1065                         break;
1066                 }
1067                 case MP_BUS_PCI: /* PCI pin */
1068                 {
1069                         /*
1070                          * PCI IRQs are mapped in order
1071                          */
1072                         i = irq = 0;
1073                         while (i < apic)
1074                                 irq += nr_ioapic_registers[i++];
1075                         irq += pin;
1076
1077                         /*
1078                          * For MPS mode, so far only needed by ES7000 platform
1079                          */
1080                         if (ioapic_renumber_irq)
1081                                 irq = ioapic_renumber_irq(apic, irq);
1082
1083                         break;
1084                 }
1085                 default:
1086                 {
1087                         printk(KERN_ERR "unknown bus type %d.\n",bus); 
1088                         irq = 0;
1089                         break;
1090                 }
1091         }
1092
1093         /*
1094          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1095          */
1096         if ((pin >= 16) && (pin <= 23)) {
1097                 if (pirq_entries[pin-16] != -1) {
1098                         if (!pirq_entries[pin-16]) {
1099                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1100                                                 "disabling PIRQ%d\n", pin-16);
1101                         } else {
1102                                 irq = pirq_entries[pin-16];
1103                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1104                                                 "using PIRQ%d -> IRQ %d\n",
1105                                                 pin-16, irq);
1106                         }
1107                 }
1108         }
1109         return irq;
1110 }
1111
1112 static inline int IO_APIC_irq_trigger(int irq)
1113 {
1114         int apic, idx, pin;
1115
1116         for (apic = 0; apic < nr_ioapics; apic++) {
1117                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1118                         idx = find_irq_entry(apic,pin,mp_INT);
1119                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1120                                 return irq_trigger(idx);
1121                 }
1122         }
1123         /*
1124          * nonexistent IRQs are edge default
1125          */
1126         return 0;
1127 }
1128
1129 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1130 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
1131
1132 int assign_irq_vector(int irq)
1133 {
1134         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1135
1136         BUG_ON(irq >= NR_IRQ_VECTORS);
1137         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
1138                 return IO_APIC_VECTOR(irq);
1139 next:
1140         current_vector += 8;
1141         if (current_vector == SYSCALL_VECTOR)
1142                 goto next;
1143
1144         if (current_vector >= FIRST_SYSTEM_VECTOR) {
1145                 offset++;
1146                 if (!(offset%8))
1147                         return -ENOSPC;
1148                 current_vector = FIRST_DEVICE_VECTOR + offset;
1149         }
1150
1151         vector_irq[current_vector] = irq;
1152         if (irq != AUTO_ASSIGN)
1153                 IO_APIC_VECTOR(irq) = current_vector;
1154
1155         return current_vector;
1156 }
1157
1158 static struct hw_interrupt_type ioapic_level_type;
1159 static struct hw_interrupt_type ioapic_edge_type;
1160
1161 #define IOAPIC_AUTO     -1
1162 #define IOAPIC_EDGE     0
1163 #define IOAPIC_LEVEL    1
1164
1165 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1166 {
1167         if (use_pci_vector() && !platform_legacy_irq(irq)) {
1168                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1169                                 trigger == IOAPIC_LEVEL)
1170                         irq_desc[vector].handler = &ioapic_level_type;
1171                 else
1172                         irq_desc[vector].handler = &ioapic_edge_type;
1173                 set_intr_gate(vector, interrupt[vector]);
1174         } else  {
1175                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1176                                 trigger == IOAPIC_LEVEL)
1177                         irq_desc[irq].handler = &ioapic_level_type;
1178                 else
1179                         irq_desc[irq].handler = &ioapic_edge_type;
1180                 set_intr_gate(vector, interrupt[irq]);
1181         }
1182 }
1183
1184 static void __init setup_IO_APIC_irqs(void)
1185 {
1186         struct IO_APIC_route_entry entry;
1187         int apic, pin, idx, irq, first_notcon = 1, vector;
1188         unsigned long flags;
1189
1190         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1191
1192         for (apic = 0; apic < nr_ioapics; apic++) {
1193         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1194
1195                 /*
1196                  * add it to the IO-APIC irq-routing table:
1197                  */
1198                 memset(&entry,0,sizeof(entry));
1199
1200                 entry.delivery_mode = INT_DELIVERY_MODE;
1201                 entry.dest_mode = INT_DEST_MODE;
1202                 entry.mask = 0;                         /* enable IRQ */
1203                 entry.dest.logical.logical_dest = 
1204                                         cpu_mask_to_apicid(TARGET_CPUS);
1205
1206                 idx = find_irq_entry(apic,pin,mp_INT);
1207                 if (idx == -1) {
1208                         if (first_notcon) {
1209                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1210                                                 " IO-APIC (apicid-pin) %d-%d",
1211                                                 mp_ioapics[apic].mpc_apicid,
1212                                                 pin);
1213                                 first_notcon = 0;
1214                         } else
1215                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1216                                         mp_ioapics[apic].mpc_apicid, pin);
1217                         continue;
1218                 }
1219
1220                 entry.trigger = irq_trigger(idx);
1221                 entry.polarity = irq_polarity(idx);
1222
1223                 if (irq_trigger(idx)) {
1224                         entry.trigger = 1;
1225                         entry.mask = 1;
1226                 }
1227
1228                 irq = pin_2_irq(idx, apic, pin);
1229                 /*
1230                  * skip adding the timer int on secondary nodes, which causes
1231                  * a small but painful rift in the time-space continuum
1232                  */
1233                 if (multi_timer_check(apic, irq))
1234                         continue;
1235                 else
1236                         add_pin_to_irq(irq, apic, pin);
1237
1238                 if (!apic && !IO_APIC_IRQ(irq))
1239                         continue;
1240
1241                 if (IO_APIC_IRQ(irq)) {
1242                         vector = assign_irq_vector(irq);
1243                         entry.vector = vector;
1244                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1245                 
1246                         if (!apic && (irq < 16))
1247                                 disable_8259A_irq(irq);
1248                 }
1249                 spin_lock_irqsave(&ioapic_lock, flags);
1250                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1251                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1252                 spin_unlock_irqrestore(&ioapic_lock, flags);
1253         }
1254         }
1255
1256         if (!first_notcon)
1257                 apic_printk(APIC_VERBOSE, " not connected.\n");
1258 }
1259
1260 /*
1261  * Set up the 8259A-master output pin:
1262  */
1263 static void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
1264 {
1265         struct IO_APIC_route_entry entry;
1266         unsigned long flags;
1267
1268         memset(&entry,0,sizeof(entry));
1269
1270         disable_8259A_irq(0);
1271
1272         /* mask LVT0 */
1273         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1274
1275         /*
1276          * We use logical delivery to get the timer IRQ
1277          * to the first CPU.
1278          */
1279         entry.dest_mode = INT_DEST_MODE;
1280         entry.mask = 0;                                 /* unmask IRQ now */
1281         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1282         entry.delivery_mode = INT_DELIVERY_MODE;
1283         entry.polarity = 0;
1284         entry.trigger = 0;
1285         entry.vector = vector;
1286
1287         /*
1288          * The timer IRQ doesn't have to know that behind the
1289          * scene we have a 8259A-master in AEOI mode ...
1290          */
1291         irq_desc[0].handler = &ioapic_edge_type;
1292
1293         /*
1294          * Add it to the IO-APIC irq-routing table:
1295          */
1296         spin_lock_irqsave(&ioapic_lock, flags);
1297         io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1298         io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1299         spin_unlock_irqrestore(&ioapic_lock, flags);
1300
1301         enable_8259A_irq(0);
1302 }
1303
1304 static inline void UNEXPECTED_IO_APIC(void)
1305 {
1306 }
1307
1308 void __init print_IO_APIC(void)
1309 {
1310         int apic, i;
1311         union IO_APIC_reg_00 reg_00;
1312         union IO_APIC_reg_01 reg_01;
1313         union IO_APIC_reg_02 reg_02;
1314         union IO_APIC_reg_03 reg_03;
1315         unsigned long flags;
1316
1317         if (apic_verbosity == APIC_QUIET)
1318                 return;
1319
1320         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1321         for (i = 0; i < nr_ioapics; i++)
1322                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1323                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1324
1325         /*
1326          * We are a bit conservative about what we expect.  We have to
1327          * know about every hardware change ASAP.
1328          */
1329         printk(KERN_INFO "testing the IO APIC.......................\n");
1330
1331         for (apic = 0; apic < nr_ioapics; apic++) {
1332
1333         spin_lock_irqsave(&ioapic_lock, flags);
1334         reg_00.raw = io_apic_read(apic, 0);
1335         reg_01.raw = io_apic_read(apic, 1);
1336         if (reg_01.bits.version >= 0x10)
1337                 reg_02.raw = io_apic_read(apic, 2);
1338         if (reg_01.bits.version >= 0x20)
1339                 reg_03.raw = io_apic_read(apic, 3);
1340         spin_unlock_irqrestore(&ioapic_lock, flags);
1341
1342         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1343         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1344         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1345         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1346         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1347         if (reg_00.bits.ID >= get_physical_broadcast())
1348                 UNEXPECTED_IO_APIC();
1349         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1350                 UNEXPECTED_IO_APIC();
1351
1352         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1353         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1354         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1355                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1356                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1357                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1358                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1359                 (reg_01.bits.entries != 0x2E) &&
1360                 (reg_01.bits.entries != 0x3F)
1361         )
1362                 UNEXPECTED_IO_APIC();
1363
1364         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1365         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1366         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1367                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1368                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1369                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1370                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1371         )
1372                 UNEXPECTED_IO_APIC();
1373         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1374                 UNEXPECTED_IO_APIC();
1375
1376         /*
1377          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1378          * but the value of reg_02 is read as the previous read register
1379          * value, so ignore it if reg_02 == reg_01.
1380          */
1381         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1382                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1383                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1384                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1385                         UNEXPECTED_IO_APIC();
1386         }
1387
1388         /*
1389          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1390          * or reg_03, but the value of reg_0[23] is read as the previous read
1391          * register value, so ignore it if reg_03 == reg_0[12].
1392          */
1393         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1394             reg_03.raw != reg_01.raw) {
1395                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1396                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1397                 if (reg_03.bits.__reserved_1)
1398                         UNEXPECTED_IO_APIC();
1399         }
1400
1401         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1402
1403         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1404                           " Stat Dest Deli Vect:   \n");
1405
1406         for (i = 0; i <= reg_01.bits.entries; i++) {
1407                 struct IO_APIC_route_entry entry;
1408
1409                 spin_lock_irqsave(&ioapic_lock, flags);
1410                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1411                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1412                 spin_unlock_irqrestore(&ioapic_lock, flags);
1413
1414                 printk(KERN_DEBUG " %02x %03X %02X  ",
1415                         i,
1416                         entry.dest.logical.logical_dest,
1417                         entry.dest.physical.physical_dest
1418                 );
1419
1420                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1421                         entry.mask,
1422                         entry.trigger,
1423                         entry.irr,
1424                         entry.polarity,
1425                         entry.delivery_status,
1426                         entry.dest_mode,
1427                         entry.delivery_mode,
1428                         entry.vector
1429                 );
1430         }
1431         }
1432         if (use_pci_vector())
1433                 printk(KERN_INFO "Using vector-based indexing\n");
1434         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1435         for (i = 0; i < NR_IRQS; i++) {
1436                 struct irq_pin_list *entry = irq_2_pin + i;
1437                 if (entry->pin < 0)
1438                         continue;
1439                 if (use_pci_vector() && !platform_legacy_irq(i))
1440                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1441                 else
1442                         printk(KERN_DEBUG "IRQ%d ", i);
1443                 for (;;) {
1444                         printk("-> %d:%d", entry->apic, entry->pin);
1445                         if (!entry->next)
1446                                 break;
1447                         entry = irq_2_pin + entry->next;
1448                 }
1449                 printk("\n");
1450         }
1451
1452         printk(KERN_INFO ".................................... done.\n");
1453
1454         return;
1455 }
1456
1457 #if 0
1458
1459 static void print_APIC_bitfield (int base)
1460 {
1461         unsigned int v;
1462         int i, j;
1463
1464         if (apic_verbosity == APIC_QUIET)
1465                 return;
1466
1467         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1468         for (i = 0; i < 8; i++) {
1469                 v = apic_read(base + i*0x10);
1470                 for (j = 0; j < 32; j++) {
1471                         if (v & (1<<j))
1472                                 printk("1");
1473                         else
1474                                 printk("0");
1475                 }
1476                 printk("\n");
1477         }
1478 }
1479
1480 void /*__init*/ print_local_APIC(void * dummy)
1481 {
1482         unsigned int v, ver, maxlvt;
1483
1484         if (apic_verbosity == APIC_QUIET)
1485                 return;
1486
1487         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1488                 smp_processor_id(), hard_smp_processor_id());
1489         v = apic_read(APIC_ID);
1490         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1491         v = apic_read(APIC_LVR);
1492         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1493         ver = GET_APIC_VERSION(v);
1494         maxlvt = get_maxlvt();
1495
1496         v = apic_read(APIC_TASKPRI);
1497         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1498
1499         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1500                 v = apic_read(APIC_ARBPRI);
1501                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1502                         v & APIC_ARBPRI_MASK);
1503                 v = apic_read(APIC_PROCPRI);
1504                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1505         }
1506
1507         v = apic_read(APIC_EOI);
1508         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1509         v = apic_read(APIC_RRR);
1510         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1511         v = apic_read(APIC_LDR);
1512         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1513         v = apic_read(APIC_DFR);
1514         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1515         v = apic_read(APIC_SPIV);
1516         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1517
1518         printk(KERN_DEBUG "... APIC ISR field:\n");
1519         print_APIC_bitfield(APIC_ISR);
1520         printk(KERN_DEBUG "... APIC TMR field:\n");
1521         print_APIC_bitfield(APIC_TMR);
1522         printk(KERN_DEBUG "... APIC IRR field:\n");
1523         print_APIC_bitfield(APIC_IRR);
1524
1525         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1526                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1527                         apic_write(APIC_ESR, 0);
1528                 v = apic_read(APIC_ESR);
1529                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1530         }
1531
1532         v = apic_read(APIC_ICR);
1533         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1534         v = apic_read(APIC_ICR2);
1535         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1536
1537         v = apic_read(APIC_LVTT);
1538         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1539
1540         if (maxlvt > 3) {                       /* PC is LVT#4. */
1541                 v = apic_read(APIC_LVTPC);
1542                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1543         }
1544         v = apic_read(APIC_LVT0);
1545         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1546         v = apic_read(APIC_LVT1);
1547         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1548
1549         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1550                 v = apic_read(APIC_LVTERR);
1551                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1552         }
1553
1554         v = apic_read(APIC_TMICT);
1555         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1556         v = apic_read(APIC_TMCCT);
1557         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1558         v = apic_read(APIC_TDCR);
1559         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1560         printk("\n");
1561 }
1562
1563 void print_all_local_APICs (void)
1564 {
1565         on_each_cpu(print_local_APIC, NULL, 1, 1);
1566 }
1567
1568 void /*__init*/ print_PIC(void)
1569 {
1570         unsigned int v;
1571         unsigned long flags;
1572
1573         if (apic_verbosity == APIC_QUIET)
1574                 return;
1575
1576         printk(KERN_DEBUG "\nprinting PIC contents\n");
1577
1578         spin_lock_irqsave(&i8259A_lock, flags);
1579
1580         v = inb(0xa1) << 8 | inb(0x21);
1581         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1582
1583         v = inb(0xa0) << 8 | inb(0x20);
1584         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1585
1586         outb(0x0b,0xa0);
1587         outb(0x0b,0x20);
1588         v = inb(0xa0) << 8 | inb(0x20);
1589         outb(0x0a,0xa0);
1590         outb(0x0a,0x20);
1591
1592         spin_unlock_irqrestore(&i8259A_lock, flags);
1593
1594         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1595
1596         v = inb(0x4d1) << 8 | inb(0x4d0);
1597         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1598 }
1599
1600 #endif  /*  0  */
1601
1602 static void __init enable_IO_APIC(void)
1603 {
1604         union IO_APIC_reg_01 reg_01;
1605         int i;
1606         unsigned long flags;
1607
1608         for (i = 0; i < PIN_MAP_SIZE; i++) {
1609                 irq_2_pin[i].pin = -1;
1610                 irq_2_pin[i].next = 0;
1611         }
1612         if (!pirqs_enabled)
1613                 for (i = 0; i < MAX_PIRQS; i++)
1614                         pirq_entries[i] = -1;
1615
1616         /*
1617          * The number of IO-APIC IRQ registers (== #pins):
1618          */
1619         for (i = 0; i < nr_ioapics; i++) {
1620                 spin_lock_irqsave(&ioapic_lock, flags);
1621                 reg_01.raw = io_apic_read(i, 1);
1622                 spin_unlock_irqrestore(&ioapic_lock, flags);
1623                 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1624         }
1625
1626         /*
1627          * Do not trust the IO-APIC being empty at bootup
1628          */
1629         clear_IO_APIC();
1630 }
1631
1632 /*
1633  * Not an __init, needed by the reboot code
1634  */
1635 void disable_IO_APIC(void)
1636 {
1637         int pin;
1638         /*
1639          * Clear the IO-APIC before rebooting:
1640          */
1641         clear_IO_APIC();
1642
1643         /*
1644          * If the i82559 is routed through an IOAPIC
1645          * Put that IOAPIC in virtual wire mode
1646          * so legacy interrups can be delivered.
1647          */
1648         pin = find_isa_irq_pin(0, mp_ExtINT);
1649         if (pin != -1) {
1650                 struct IO_APIC_route_entry entry;
1651                 unsigned long flags;
1652
1653                 memset(&entry, 0, sizeof(entry));
1654                 entry.mask            = 0; /* Enabled */
1655                 entry.trigger         = 0; /* Edge */
1656                 entry.irr             = 0;
1657                 entry.polarity        = 0; /* High */
1658                 entry.delivery_status = 0;
1659                 entry.dest_mode       = 0; /* Physical */
1660                 entry.delivery_mode   = 7; /* ExtInt */
1661                 entry.vector          = 0;
1662                 entry.dest.physical.physical_dest = 0;
1663
1664
1665                 /*
1666                  * Add it to the IO-APIC irq-routing table:
1667                  */
1668                 spin_lock_irqsave(&ioapic_lock, flags);
1669                 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1670                 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1671                 spin_unlock_irqrestore(&ioapic_lock, flags);
1672         }
1673         disconnect_bsp_APIC(pin != -1);
1674 }
1675
1676 /*
1677  * function to set the IO-APIC physical IDs based on the
1678  * values stored in the MPC table.
1679  *
1680  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1681  */
1682
1683 #ifndef CONFIG_X86_NUMAQ
1684 static void __init setup_ioapic_ids_from_mpc(void)
1685 {
1686         union IO_APIC_reg_00 reg_00;
1687         physid_mask_t phys_id_present_map;
1688         int apic;
1689         int i;
1690         unsigned char old_id;
1691         unsigned long flags;
1692
1693         /*
1694          * Don't check I/O APIC IDs for xAPIC systems.  They have
1695          * no meaning without the serial APIC bus.
1696          */
1697         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && boot_cpu_data.x86 < 15))
1698                 return;
1699         /*
1700          * This is broken; anything with a real cpu count has to
1701          * circumvent this idiocy regardless.
1702          */
1703         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1704
1705         /*
1706          * Set the IOAPIC ID to the value stored in the MPC table.
1707          */
1708         for (apic = 0; apic < nr_ioapics; apic++) {
1709
1710                 /* Read the register 0 value */
1711                 spin_lock_irqsave(&ioapic_lock, flags);
1712                 reg_00.raw = io_apic_read(apic, 0);
1713                 spin_unlock_irqrestore(&ioapic_lock, flags);
1714                 
1715                 old_id = mp_ioapics[apic].mpc_apicid;
1716
1717                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1718                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1719                                 apic, mp_ioapics[apic].mpc_apicid);
1720                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1721                                 reg_00.bits.ID);
1722                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1723                 }
1724
1725                 /*
1726                  * Sanity check, is the ID really free? Every APIC in a
1727                  * system must have a unique ID or we get lots of nice
1728                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1729                  */
1730                 if (check_apicid_used(phys_id_present_map,
1731                                         mp_ioapics[apic].mpc_apicid)) {
1732                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1733                                 apic, mp_ioapics[apic].mpc_apicid);
1734                         for (i = 0; i < get_physical_broadcast(); i++)
1735                                 if (!physid_isset(i, phys_id_present_map))
1736                                         break;
1737                         if (i >= get_physical_broadcast())
1738                                 panic("Max APIC ID exceeded!\n");
1739                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1740                                 i);
1741                         physid_set(i, phys_id_present_map);
1742                         mp_ioapics[apic].mpc_apicid = i;
1743                 } else {
1744                         physid_mask_t tmp;
1745                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1746                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1747                                         "phys_id_present_map\n",
1748                                         mp_ioapics[apic].mpc_apicid);
1749                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1750                 }
1751
1752
1753                 /*
1754                  * We need to adjust the IRQ routing table
1755                  * if the ID changed.
1756                  */
1757                 if (old_id != mp_ioapics[apic].mpc_apicid)
1758                         for (i = 0; i < mp_irq_entries; i++)
1759                                 if (mp_irqs[i].mpc_dstapic == old_id)
1760                                         mp_irqs[i].mpc_dstapic
1761                                                 = mp_ioapics[apic].mpc_apicid;
1762
1763                 /*
1764                  * Read the right value from the MPC table and
1765                  * write it into the ID register.
1766                  */
1767                 apic_printk(APIC_VERBOSE, KERN_INFO
1768                         "...changing IO-APIC physical APIC ID to %d ...",
1769                         mp_ioapics[apic].mpc_apicid);
1770
1771                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1772                 spin_lock_irqsave(&ioapic_lock, flags);
1773                 io_apic_write(apic, 0, reg_00.raw);
1774                 spin_unlock_irqrestore(&ioapic_lock, flags);
1775
1776                 /*
1777                  * Sanity check
1778                  */
1779                 spin_lock_irqsave(&ioapic_lock, flags);
1780                 reg_00.raw = io_apic_read(apic, 0);
1781                 spin_unlock_irqrestore(&ioapic_lock, flags);
1782                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1783                         printk("could not set ID!\n");
1784                 else
1785                         apic_printk(APIC_VERBOSE, " ok.\n");
1786         }
1787 }
1788 #else
1789 static void __init setup_ioapic_ids_from_mpc(void) { }
1790 #endif
1791
1792 /*
1793  * There is a nasty bug in some older SMP boards, their mptable lies
1794  * about the timer IRQ. We do the following to work around the situation:
1795  *
1796  *      - timer IRQ defaults to IO-APIC IRQ
1797  *      - if this function detects that timer IRQs are defunct, then we fall
1798  *        back to ISA timer IRQs
1799  */
1800 static int __init timer_irq_works(void)
1801 {
1802         unsigned long t1 = jiffies;
1803
1804         local_irq_enable();
1805         /* Let ten ticks pass... */
1806         mdelay((10 * 1000) / HZ);
1807
1808         /*
1809          * Expect a few ticks at least, to be sure some possible
1810          * glue logic does not lock up after one or two first
1811          * ticks in a non-ExtINT mode.  Also the local APIC
1812          * might have cached one ExtINT interrupt.  Finally, at
1813          * least one tick may be lost due to delays.
1814          */
1815         if (jiffies - t1 > 4)
1816                 return 1;
1817
1818         return 0;
1819 }
1820
1821 /*
1822  * In the SMP+IOAPIC case it might happen that there are an unspecified
1823  * number of pending IRQ events unhandled. These cases are very rare,
1824  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1825  * better to do it this way as thus we do not have to be aware of
1826  * 'pending' interrupts in the IRQ path, except at this point.
1827  */
1828 /*
1829  * Edge triggered needs to resend any interrupt
1830  * that was delayed but this is now handled in the device
1831  * independent code.
1832  */
1833
1834 /*
1835  * Starting up a edge-triggered IO-APIC interrupt is
1836  * nasty - we need to make sure that we get the edge.
1837  * If it is already asserted for some reason, we need
1838  * return 1 to indicate that is was pending.
1839  *
1840  * This is not complete - we should be able to fake
1841  * an edge even if it isn't on the 8259A...
1842  */
1843 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1844 {
1845         int was_pending = 0;
1846         unsigned long flags;
1847
1848         spin_lock_irqsave(&ioapic_lock, flags);
1849         if (irq < 16) {
1850                 disable_8259A_irq(irq);
1851                 if (i8259A_irq_pending(irq))
1852                         was_pending = 1;
1853         }
1854         __unmask_IO_APIC_irq(irq);
1855         spin_unlock_irqrestore(&ioapic_lock, flags);
1856
1857         return was_pending;
1858 }
1859
1860 /*
1861  * Once we have recorded IRQ_PENDING already, we can mask the
1862  * interrupt for real. This prevents IRQ storms from unhandled
1863  * devices.
1864  */
1865 static void ack_edge_ioapic_irq(unsigned int irq)
1866 {
1867         move_irq(irq);
1868         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1869                                         == (IRQ_PENDING | IRQ_DISABLED))
1870                 mask_IO_APIC_irq(irq);
1871         ack_APIC_irq();
1872 }
1873
1874 /*
1875  * Level triggered interrupts can just be masked,
1876  * and shutting down and starting up the interrupt
1877  * is the same as enabling and disabling them -- except
1878  * with a startup need to return a "was pending" value.
1879  *
1880  * Level triggered interrupts are special because we
1881  * do not touch any IO-APIC register while handling
1882  * them. We ack the APIC in the end-IRQ handler, not
1883  * in the start-IRQ-handler. Protection against reentrance
1884  * from the same interrupt is still provided, both by the
1885  * generic IRQ layer and by the fact that an unacked local
1886  * APIC does not accept IRQs.
1887  */
1888 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1889 {
1890         unmask_IO_APIC_irq(irq);
1891
1892         return 0; /* don't check for pending */
1893 }
1894
1895 static void end_level_ioapic_irq (unsigned int irq)
1896 {
1897         unsigned long v;
1898         int i;
1899
1900         move_irq(irq);
1901 /*
1902  * It appears there is an erratum which affects at least version 0x11
1903  * of I/O APIC (that's the 82093AA and cores integrated into various
1904  * chipsets).  Under certain conditions a level-triggered interrupt is
1905  * erroneously delivered as edge-triggered one but the respective IRR
1906  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1907  * message but it will never arrive and further interrupts are blocked
1908  * from the source.  The exact reason is so far unknown, but the
1909  * phenomenon was observed when two consecutive interrupt requests
1910  * from a given source get delivered to the same CPU and the source is
1911  * temporarily disabled in between.
1912  *
1913  * A workaround is to simulate an EOI message manually.  We achieve it
1914  * by setting the trigger mode to edge and then to level when the edge
1915  * trigger mode gets detected in the TMR of a local APIC for a
1916  * level-triggered interrupt.  We mask the source for the time of the
1917  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1918  * The idea is from Manfred Spraul.  --macro
1919  */
1920         i = IO_APIC_VECTOR(irq);
1921
1922         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1923
1924         ack_APIC_irq();
1925
1926         if (!(v & (1 << (i & 0x1f)))) {
1927                 atomic_inc(&irq_mis_count);
1928                 spin_lock(&ioapic_lock);
1929                 __mask_and_edge_IO_APIC_irq(irq);
1930                 __unmask_and_level_IO_APIC_irq(irq);
1931                 spin_unlock(&ioapic_lock);
1932         }
1933 }
1934
1935 #ifdef CONFIG_PCI_MSI
1936 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1937 {
1938         int irq = vector_to_irq(vector);
1939
1940         return startup_edge_ioapic_irq(irq);
1941 }
1942
1943 static void ack_edge_ioapic_vector(unsigned int vector)
1944 {
1945         int irq = vector_to_irq(vector);
1946
1947         ack_edge_ioapic_irq(irq);
1948 }
1949
1950 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1951 {
1952         int irq = vector_to_irq(vector);
1953
1954         return startup_level_ioapic_irq (irq);
1955 }
1956
1957 static void end_level_ioapic_vector (unsigned int vector)
1958 {
1959         int irq = vector_to_irq(vector);
1960
1961         end_level_ioapic_irq(irq);
1962 }
1963
1964 static void mask_IO_APIC_vector (unsigned int vector)
1965 {
1966         int irq = vector_to_irq(vector);
1967
1968         mask_IO_APIC_irq(irq);
1969 }
1970
1971 static void unmask_IO_APIC_vector (unsigned int vector)
1972 {
1973         int irq = vector_to_irq(vector);
1974
1975         unmask_IO_APIC_irq(irq);
1976 }
1977
1978 static void set_ioapic_affinity_vector (unsigned int vector,
1979                                         cpumask_t cpu_mask)
1980 {
1981         int irq = vector_to_irq(vector);
1982
1983         set_ioapic_affinity_irq(irq, cpu_mask);
1984 }
1985 #endif
1986
1987 /*
1988  * Level and edge triggered IO-APIC interrupts need different handling,
1989  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1990  * handled with the level-triggered descriptor, but that one has slightly
1991  * more overhead. Level-triggered interrupts cannot be handled with the
1992  * edge-triggered handler, without risking IRQ storms and other ugly
1993  * races.
1994  */
1995 static struct hw_interrupt_type ioapic_edge_type = {
1996         .typename       = "IO-APIC-edge",
1997         .startup        = startup_edge_ioapic,
1998         .shutdown       = shutdown_edge_ioapic,
1999         .enable         = enable_edge_ioapic,
2000         .disable        = disable_edge_ioapic,
2001         .ack            = ack_edge_ioapic,
2002         .end            = end_edge_ioapic,
2003         .set_affinity   = set_ioapic_affinity,
2004 };
2005
2006 static struct hw_interrupt_type ioapic_level_type = {
2007         .typename       = "IO-APIC-level",
2008         .startup        = startup_level_ioapic,
2009         .shutdown       = shutdown_level_ioapic,
2010         .enable         = enable_level_ioapic,
2011         .disable        = disable_level_ioapic,
2012         .ack            = mask_and_ack_level_ioapic,
2013         .end            = end_level_ioapic,
2014         .set_affinity   = set_ioapic_affinity,
2015 };
2016
2017 static inline void init_IO_APIC_traps(void)
2018 {
2019         int irq;
2020
2021         /*
2022          * NOTE! The local APIC isn't very good at handling
2023          * multiple interrupts at the same interrupt level.
2024          * As the interrupt level is determined by taking the
2025          * vector number and shifting that right by 4, we
2026          * want to spread these out a bit so that they don't
2027          * all fall in the same interrupt level.
2028          *
2029          * Also, we've got to be careful not to trash gate
2030          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2031          */
2032         for (irq = 0; irq < NR_IRQS ; irq++) {
2033                 int tmp = irq;
2034                 if (use_pci_vector()) {
2035                         if (!platform_legacy_irq(tmp))
2036                                 if ((tmp = vector_to_irq(tmp)) == -1)
2037                                         continue;
2038                 }
2039                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2040                         /*
2041                          * Hmm.. We don't have an entry for this,
2042                          * so default to an old-fashioned 8259
2043                          * interrupt if we can..
2044                          */
2045                         if (irq < 16)
2046                                 make_8259A_irq(irq);
2047                         else
2048                                 /* Strange. Oh, well.. */
2049                                 irq_desc[irq].handler = &no_irq_type;
2050                 }
2051         }
2052 }
2053
2054 static void enable_lapic_irq (unsigned int irq)
2055 {
2056         unsigned long v;
2057
2058         v = apic_read(APIC_LVT0);
2059         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2060 }
2061
2062 static void disable_lapic_irq (unsigned int irq)
2063 {
2064         unsigned long v;
2065
2066         v = apic_read(APIC_LVT0);
2067         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2068 }
2069
2070 static void ack_lapic_irq (unsigned int irq)
2071 {
2072         ack_APIC_irq();
2073 }
2074
2075 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2076
2077 static struct hw_interrupt_type lapic_irq_type = {
2078         .typename       = "local-APIC-edge",
2079         .startup        = NULL, /* startup_irq() not used for IRQ0 */
2080         .shutdown       = NULL, /* shutdown_irq() not used for IRQ0 */
2081         .enable         = enable_lapic_irq,
2082         .disable        = disable_lapic_irq,
2083         .ack            = ack_lapic_irq,
2084         .end            = end_lapic_irq
2085 };
2086
2087 static void setup_nmi (void)
2088 {
2089         /*
2090          * Dirty trick to enable the NMI watchdog ...
2091          * We put the 8259A master into AEOI mode and
2092          * unmask on all local APICs LVT0 as NMI.
2093          *
2094          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2095          * is from Maciej W. Rozycki - so we do not have to EOI from
2096          * the NMI handler or the timer interrupt.
2097          */ 
2098         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2099
2100         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2101
2102         apic_printk(APIC_VERBOSE, " done.\n");
2103 }
2104
2105 /*
2106  * This looks a bit hackish but it's about the only one way of sending
2107  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2108  * not support the ExtINT mode, unfortunately.  We need to send these
2109  * cycles as some i82489DX-based boards have glue logic that keeps the
2110  * 8259A interrupt line asserted until INTA.  --macro
2111  */
2112 static inline void unlock_ExtINT_logic(void)
2113 {
2114         int pin, i;
2115         struct IO_APIC_route_entry entry0, entry1;
2116         unsigned char save_control, save_freq_select;
2117         unsigned long flags;
2118
2119         pin = find_isa_irq_pin(8, mp_INT);
2120         if (pin == -1)
2121                 return;
2122
2123         spin_lock_irqsave(&ioapic_lock, flags);
2124         *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
2125         *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
2126         spin_unlock_irqrestore(&ioapic_lock, flags);
2127         clear_IO_APIC_pin(0, pin);
2128
2129         memset(&entry1, 0, sizeof(entry1));
2130
2131         entry1.dest_mode = 0;                   /* physical delivery */
2132         entry1.mask = 0;                        /* unmask IRQ now */
2133         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2134         entry1.delivery_mode = dest_ExtINT;
2135         entry1.polarity = entry0.polarity;
2136         entry1.trigger = 0;
2137         entry1.vector = 0;
2138
2139         spin_lock_irqsave(&ioapic_lock, flags);
2140         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2141         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2142         spin_unlock_irqrestore(&ioapic_lock, flags);
2143
2144         save_control = CMOS_READ(RTC_CONTROL);
2145         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2146         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2147                    RTC_FREQ_SELECT);
2148         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2149
2150         i = 100;
2151         while (i-- > 0) {
2152                 mdelay(10);
2153                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2154                         i -= 10;
2155         }
2156
2157         CMOS_WRITE(save_control, RTC_CONTROL);
2158         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2159         clear_IO_APIC_pin(0, pin);
2160
2161         spin_lock_irqsave(&ioapic_lock, flags);
2162         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2163         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2164         spin_unlock_irqrestore(&ioapic_lock, flags);
2165 }
2166
2167 /*
2168  * This code may look a bit paranoid, but it's supposed to cooperate with
2169  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2170  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2171  * fanatically on his truly buggy board.
2172  */
2173 static inline void check_timer(void)
2174 {
2175         int pin1, pin2;
2176         int vector;
2177
2178         /*
2179          * get/set the timer IRQ vector:
2180          */
2181         disable_8259A_irq(0);
2182         vector = assign_irq_vector(0);
2183         set_intr_gate(vector, interrupt[0]);
2184
2185         /*
2186          * Subtle, code in do_timer_interrupt() expects an AEOI
2187          * mode for the 8259A whenever interrupts are routed
2188          * through I/O APICs.  Also IRQ0 has to be enabled in
2189          * the 8259A which implies the virtual wire has to be
2190          * disabled in the local APIC.
2191          */
2192         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2193         init_8259A(1);
2194         timer_ack = 1;
2195         enable_8259A_irq(0);
2196
2197         pin1 = find_isa_irq_pin(0, mp_INT);
2198         pin2 = find_isa_irq_pin(0, mp_ExtINT);
2199
2200         printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
2201
2202         if (pin1 != -1) {
2203                 /*
2204                  * Ok, does IRQ0 through the IOAPIC work?
2205                  */
2206                 unmask_IO_APIC_irq(0);
2207                 if (timer_irq_works()) {
2208                         if (nmi_watchdog == NMI_IO_APIC) {
2209                                 disable_8259A_irq(0);
2210                                 setup_nmi();
2211                                 enable_8259A_irq(0);
2212                         }
2213                         return;
2214                 }
2215                 clear_IO_APIC_pin(0, pin1);
2216                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
2217         }
2218
2219         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2220         if (pin2 != -1) {
2221                 printk("\n..... (found pin %d) ...", pin2);
2222                 /*
2223                  * legacy devices should be connected to IO APIC #0
2224                  */
2225                 setup_ExtINT_IRQ0_pin(pin2, vector);
2226                 if (timer_irq_works()) {
2227                         printk("works.\n");
2228                         if (pin1 != -1)
2229                                 replace_pin_at_irq(0, 0, pin1, 0, pin2);
2230                         else
2231                                 add_pin_to_irq(0, 0, pin2);
2232                         if (nmi_watchdog == NMI_IO_APIC) {
2233                                 setup_nmi();
2234                         }
2235                         return;
2236                 }
2237                 /*
2238                  * Cleanup, just in case ...
2239                  */
2240                 clear_IO_APIC_pin(0, pin2);
2241         }
2242         printk(" failed.\n");
2243
2244         if (nmi_watchdog == NMI_IO_APIC) {
2245                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2246                 nmi_watchdog = 0;
2247         }
2248
2249         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2250
2251         disable_8259A_irq(0);
2252         irq_desc[0].handler = &lapic_irq_type;
2253         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2254         enable_8259A_irq(0);
2255
2256         if (timer_irq_works()) {
2257                 printk(" works.\n");
2258                 return;
2259         }
2260         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2261         printk(" failed.\n");
2262
2263         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2264
2265         timer_ack = 0;
2266         init_8259A(0);
2267         make_8259A_irq(0);
2268         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2269
2270         unlock_ExtINT_logic();
2271
2272         if (timer_irq_works()) {
2273                 printk(" works.\n");
2274                 return;
2275         }
2276         printk(" failed :(.\n");
2277         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2278                 "report.  Then try booting with the 'noapic' option");
2279 }
2280
2281 /*
2282  *
2283  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2284  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2285  *   Linux doesn't really care, as it's not actually used
2286  *   for any interrupt handling anyway.
2287  */
2288 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2289
2290 void __init setup_IO_APIC(void)
2291 {
2292         enable_IO_APIC();
2293
2294         if (acpi_ioapic)
2295                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2296         else
2297                 io_apic_irqs = ~PIC_IRQS;
2298
2299         printk("ENABLING IO-APIC IRQs\n");
2300
2301         /*
2302          * Set up IO-APIC IRQ routing.
2303          */
2304         if (!acpi_ioapic)
2305                 setup_ioapic_ids_from_mpc();
2306         sync_Arb_IDs();
2307         setup_IO_APIC_irqs();
2308         init_IO_APIC_traps();
2309         check_timer();
2310         if (!acpi_ioapic)
2311                 print_IO_APIC();
2312 }
2313
2314 /*
2315  *      Called after all the initialization is done. If we didnt find any
2316  *      APIC bugs then we can allow the modify fast path
2317  */
2318  
2319 static int __init io_apic_bug_finalize(void)
2320 {
2321         if(sis_apic_bug == -1)
2322                 sis_apic_bug = 0;
2323         return 0;
2324 }
2325
2326 late_initcall(io_apic_bug_finalize);
2327
2328 struct sysfs_ioapic_data {
2329         struct sys_device dev;
2330         struct IO_APIC_route_entry entry[0];
2331 };
2332 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2333
2334 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2335 {
2336         struct IO_APIC_route_entry *entry;
2337         struct sysfs_ioapic_data *data;
2338         unsigned long flags;
2339         int i;
2340         
2341         data = container_of(dev, struct sysfs_ioapic_data, dev);
2342         entry = data->entry;
2343         spin_lock_irqsave(&ioapic_lock, flags);
2344         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2345                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2346                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2347         }
2348         spin_unlock_irqrestore(&ioapic_lock, flags);
2349
2350         return 0;
2351 }
2352
2353 static int ioapic_resume(struct sys_device *dev)
2354 {
2355         struct IO_APIC_route_entry *entry;
2356         struct sysfs_ioapic_data *data;
2357         unsigned long flags;
2358         union IO_APIC_reg_00 reg_00;
2359         int i;
2360         
2361         data = container_of(dev, struct sysfs_ioapic_data, dev);
2362         entry = data->entry;
2363
2364         spin_lock_irqsave(&ioapic_lock, flags);
2365         reg_00.raw = io_apic_read(dev->id, 0);
2366         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2367                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2368                 io_apic_write(dev->id, 0, reg_00.raw);
2369         }
2370         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2371                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2372                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2373         }
2374         spin_unlock_irqrestore(&ioapic_lock, flags);
2375
2376         return 0;
2377 }
2378
2379 static struct sysdev_class ioapic_sysdev_class = {
2380         set_kset_name("ioapic"),
2381         .suspend = ioapic_suspend,
2382         .resume = ioapic_resume,
2383 };
2384
2385 static int __init ioapic_init_sysfs(void)
2386 {
2387         struct sys_device * dev;
2388         int i, size, error = 0;
2389
2390         error = sysdev_class_register(&ioapic_sysdev_class);
2391         if (error)
2392                 return error;
2393
2394         for (i = 0; i < nr_ioapics; i++ ) {
2395                 size = sizeof(struct sys_device) + nr_ioapic_registers[i] 
2396                         * sizeof(struct IO_APIC_route_entry);
2397                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2398                 if (!mp_ioapic_data[i]) {
2399                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2400                         continue;
2401                 }
2402                 memset(mp_ioapic_data[i], 0, size);
2403                 dev = &mp_ioapic_data[i]->dev;
2404                 dev->id = i; 
2405                 dev->cls = &ioapic_sysdev_class;
2406                 error = sysdev_register(dev);
2407                 if (error) {
2408                         kfree(mp_ioapic_data[i]);
2409                         mp_ioapic_data[i] = NULL;
2410                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2411                         continue;
2412                 }
2413         }
2414
2415         return 0;
2416 }
2417
2418 device_initcall(ioapic_init_sysfs);
2419
2420 /* --------------------------------------------------------------------------
2421                           ACPI-based IOAPIC Configuration
2422    -------------------------------------------------------------------------- */
2423
2424 #ifdef CONFIG_ACPI_BOOT
2425
2426 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2427 {
2428         union IO_APIC_reg_00 reg_00;
2429         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2430         physid_mask_t tmp;
2431         unsigned long flags;
2432         int i = 0;
2433
2434         /*
2435          * The P4 platform supports up to 256 APIC IDs on two separate APIC 
2436          * buses (one for LAPICs, one for IOAPICs), where predecessors only 
2437          * supports up to 16 on one shared APIC bus.
2438          * 
2439          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2440          *      advantage of new APIC bus architecture.
2441          */
2442
2443         if (physids_empty(apic_id_map))
2444                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2445
2446         spin_lock_irqsave(&ioapic_lock, flags);
2447         reg_00.raw = io_apic_read(ioapic, 0);
2448         spin_unlock_irqrestore(&ioapic_lock, flags);
2449
2450         if (apic_id >= get_physical_broadcast()) {
2451                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2452                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2453                 apic_id = reg_00.bits.ID;
2454         }
2455
2456         /*
2457          * Every APIC in a system must have a unique ID or we get lots of nice 
2458          * 'stuck on smp_invalidate_needed IPI wait' messages.
2459          */
2460         if (check_apicid_used(apic_id_map, apic_id)) {
2461
2462                 for (i = 0; i < get_physical_broadcast(); i++) {
2463                         if (!check_apicid_used(apic_id_map, i))
2464                                 break;
2465                 }
2466
2467                 if (i == get_physical_broadcast())
2468                         panic("Max apic_id exceeded!\n");
2469
2470                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2471                         "trying %d\n", ioapic, apic_id, i);
2472
2473                 apic_id = i;
2474         } 
2475
2476         tmp = apicid_to_cpu_present(apic_id);
2477         physids_or(apic_id_map, apic_id_map, tmp);
2478
2479         if (reg_00.bits.ID != apic_id) {
2480                 reg_00.bits.ID = apic_id;
2481
2482                 spin_lock_irqsave(&ioapic_lock, flags);
2483                 io_apic_write(ioapic, 0, reg_00.raw);
2484                 reg_00.raw = io_apic_read(ioapic, 0);
2485                 spin_unlock_irqrestore(&ioapic_lock, flags);
2486
2487                 /* Sanity check */
2488                 if (reg_00.bits.ID != apic_id)
2489                         panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
2490         }
2491
2492         apic_printk(APIC_VERBOSE, KERN_INFO
2493                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2494
2495         return apic_id;
2496 }
2497
2498
2499 int __init io_apic_get_version (int ioapic)
2500 {
2501         union IO_APIC_reg_01    reg_01;
2502         unsigned long flags;
2503
2504         spin_lock_irqsave(&ioapic_lock, flags);
2505         reg_01.raw = io_apic_read(ioapic, 1);
2506         spin_unlock_irqrestore(&ioapic_lock, flags);
2507
2508         return reg_01.bits.version;
2509 }
2510
2511
2512 int __init io_apic_get_redir_entries (int ioapic)
2513 {
2514         union IO_APIC_reg_01    reg_01;
2515         unsigned long flags;
2516
2517         spin_lock_irqsave(&ioapic_lock, flags);
2518         reg_01.raw = io_apic_read(ioapic, 1);
2519         spin_unlock_irqrestore(&ioapic_lock, flags);
2520
2521         return reg_01.bits.entries;
2522 }
2523
2524
2525 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2526 {
2527         struct IO_APIC_route_entry entry;
2528         unsigned long flags;
2529
2530         if (!IO_APIC_IRQ(irq)) {
2531                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2532                         ioapic);
2533                 return -EINVAL;
2534         }
2535
2536         /*
2537          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2538          * Note that we mask (disable) IRQs now -- these get enabled when the
2539          * corresponding device driver registers for this IRQ.
2540          */
2541
2542         memset(&entry,0,sizeof(entry));
2543
2544         entry.delivery_mode = INT_DELIVERY_MODE;
2545         entry.dest_mode = INT_DEST_MODE;
2546         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2547         entry.trigger = edge_level;
2548         entry.polarity = active_high_low;
2549         entry.mask  = 1;
2550
2551         /*
2552          * IRQs < 16 are already in the irq_2_pin[] map
2553          */
2554         if (irq >= 16)
2555                 add_pin_to_irq(irq, ioapic, pin);
2556
2557         entry.vector = assign_irq_vector(irq);
2558
2559         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2560                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2561                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2562                 edge_level, active_high_low);
2563
2564         ioapic_register_intr(irq, entry.vector, edge_level);
2565
2566         if (!ioapic && (irq < 16))
2567                 disable_8259A_irq(irq);
2568
2569         spin_lock_irqsave(&ioapic_lock, flags);
2570         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2571         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2572         spin_unlock_irqrestore(&ioapic_lock, flags);
2573
2574         return 0;
2575 }
2576
2577 #endif /*CONFIG_ACPI_BOOT*/