git.oblomov.eu Git - linux-2.6/blob - arch/x86/pci/i386.c

   1 /*
   2  *      Low-Level PCI Access for i386 machines
   3  *
   4  * Copyright 1993, 1994 Drew Eckhardt
   5  *      Visionary Computing
   6  *      (Unix and Linux consulting and custom programming)
   7  *      Drew@Colorado.EDU
   8  *      +1 (303) 786-7975
   9  *
  10  * Drew's work was sponsored by:
  11  *      iX Multiuser Multitasking Magazine
  12  *      Hannover, Germany
  13  *      hm@ix.de
  14  *
  15  * Copyright 1997--2000 Martin Mares <mj@ucw.cz>
  16  *
  17  * For more information, please consult the following manuals (look at
  18  * http://www.pcisig.com/ for how to get them):
  19  *
  20  * PCI BIOS Specification
  21  * PCI Local Bus Specification
  22  * PCI to PCI Bridge Specification
  23  * PCI System Design Guide
  24  *
  25  */
  26
  27 #include <linux/types.h>
  28 #include <linux/kernel.h>
  29 #include <linux/pci.h>
  30 #include <linux/init.h>
  31 #include <linux/ioport.h>
  32 #include <linux/errno.h>
  33 #include <linux/bootmem.h>
  34 #include <linux/acpi.h>
  35
  36 #include <asm/pat.h>
  37 #include <asm/hpet.h>
  38 #include <asm/io_apic.h>
  39
  40 #include "pci.h"
  41
  42 static int
  43 skip_isa_ioresource_align(struct pci_dev *dev) {
  44
  45         if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) &&
  46             !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
  47                 return 1;
  48         return 0;
  49 }
  50
  51 /*
  52  * We need to avoid collisions with `mirrored' VGA ports
  53  * and other strange ISA hardware, so we always want the
  54  * addresses to be allocated in the 0x000-0x0ff region
  55  * modulo 0x400.
  56  *
  57  * Why? Because some silly external IO cards only decode
  58  * the low 10 bits of the IO address. The 0x00-0xff region
  59  * is reserved for motherboard devices that decode all 16
  60  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  61  * but we want to try to avoid allocating at 0x2900-0x2bff
  62  * which might have be mirrored at 0x0100-0x03ff..
  63  */
  64 void
  65 pcibios_align_resource(void *data, struct resource *res,
  66                         resource_size_t size, resource_size_t align)
  67 {
  68         struct pci_dev *dev = data;
  69
  70         if (res->flags & IORESOURCE_IO) {
  71                 resource_size_t start = res->start;
  72
  73                 if (skip_isa_ioresource_align(dev))
  74                         return;
  75                 if (start & 0x300) {
  76                         start = (start + 0x3ff) & ~0x3ff;
  77                         res->start = start;
  78                 }
  79         }
  80 }
  81 EXPORT_SYMBOL(pcibios_align_resource);
  82
  83 static int check_res_with_valid(struct pci_dev *dev, struct resource *res)
  84 {
  85         unsigned long base;
  86         unsigned long size;
  87         int i;
  88
  89         base = res->start;
  90         size = (res->start == 0 && res->end == res->start) ? 0 :
  91                  (res->end - res->start + 1);
  92
  93         if (!base || !size)
  94                 return 0;
  95
  96 #ifdef CONFIG_HPET_TIMER
  97         /* for hpet */
  98         if (base == hpet_address && (res->flags & IORESOURCE_MEM)) {
  99                 dev_info(&dev->dev, "BAR has HPET at %08lx-%08lx\n",
 100                                  base, base + size - 1);
 101                 return 1;
 102         }
 103 #endif
 104
 105 #ifdef CONFIG_X86_IO_APIC
 106         for (i = 0; i < nr_ioapics; i++) {
 107                 unsigned long ioapic_phys = mp_ioapics[i].mp_apicaddr;
 108
 109                 if (base == ioapic_phys && (res->flags & IORESOURCE_MEM)) {
 110                         dev_info(&dev->dev, "BAR has ioapic at %08lx-%08lx\n",
 111                                          base, base + size - 1);
 112                         return 1;
 113                 }
 114         }
 115 #endif
 116
 117 #ifdef CONFIG_PCI_MMCONFIG
 118         for (i = 0; i < pci_mmcfg_config_num; i++) {
 119                 unsigned long addr;
 120
 121                 addr = pci_mmcfg_config[i].address;
 122                 if (base == addr && (res->flags & IORESOURCE_MEM)) {
 123                         dev_info(&dev->dev, "BAR has MMCONFIG at %08lx-%08lx\n",
 124                                          base, base + size - 1);
 125                         return 1;
 126                 }
 127         }
 128 #endif
 129
 130         return 0;
 131 }
 132
 133 static int check_platform(struct pci_dev *dev, struct resource *res)
 134 {
 135         struct resource *root = NULL;
 136
 137         /*
 138          * forcibly insert it into the
 139          * resource tree
 140          */
 141         if (res->flags & IORESOURCE_MEM)
 142                 root = &iomem_resource;
 143         else if (res->flags & IORESOURCE_IO)
 144                 root = &ioport_resource;
 145
 146         if (root && check_res_with_valid(dev, res)) {
 147                 insert_resource(root, res);
 148
 149                 return 1;
 150         }
 151
 152         return 0;
 153 }
 154 /*
 155  *  Handle resources of PCI devices.  If the world were perfect, we could
 156  *  just allocate all the resource regions and do nothing more.  It isn't.
 157  *  On the other hand, we cannot just re-allocate all devices, as it would
 158  *  require us to know lots of host bridge internals.  So we attempt to
 159  *  keep as much of the original configuration as possible, but tweak it
 160  *  when it's found to be wrong.
 161  *
 162  *  Known BIOS problems we have to work around:
 163  *      - I/O or memory regions not configured
 164  *      - regions configured, but not enabled in the command register
 165  *      - bogus I/O addresses above 64K used
 166  *      - expansion ROMs left enabled (this may sound harmless, but given
 167  *        the fact the PCI specs explicitly allow address decoders to be
 168  *        shared between expansion ROMs and other resource regions, it's
 169  *        at least dangerous)
 170  *
 171  *  Our solution:
 172  *      (1) Allocate resources for all buses behind PCI-to-PCI bridges.
 173  *          This gives us fixed barriers on where we can allocate.
 174  *      (2) Allocate resources for all enabled devices.  If there is
 175  *          a collision, just mark the resource as unallocated. Also
 176  *          disable expansion ROMs during this step.
 177  *      (3) Try to allocate resources for disabled devices.  If the
 178  *          resources were assigned correctly, everything goes well,
 179  *          if they weren't, they won't disturb allocation of other
 180  *          resources.
 181  *      (4) Assign new addresses to resources which were either
 182  *          not configured at all or misconfigured.  If explicitly
 183  *          requested by the user, configure expansion ROM address
 184  *          as well.
 185  */
 186
 187 static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
 188 {
 189         struct pci_bus *bus;
 190         struct pci_dev *dev;
 191         int idx;
 192         struct resource *r, *pr;
 193
 194         /* Depth-First Search on bus tree */
 195         list_for_each_entry(bus, bus_list, node) {
 196                 if ((dev = bus->self)) {
 197                         for (idx = PCI_BRIDGE_RESOURCES;
 198                             idx < PCI_NUM_RESOURCES; idx++) {
 199                                 r = &dev->resource[idx];
 200                                 if (!r->flags)
 201                                         continue;
 202                                 pr = pci_find_parent_resource(dev, r);
 203                                 if (!r->start || !pr ||
 204                                     request_resource(pr, r) < 0) {
 205                                         if (check_platform(dev, r))
 206                                                 continue;
 207                                         dev_err(&dev->dev, "BAR %d: can't "
 208                                                 "allocate resource\n", idx);
 209                                         /*
 210                                          * Something is wrong with the region.
 211                                          * Invalidate the resource to prevent
 212                                          * child resource allocations in this
 213                                          * range.
 214                                          */
 215                                         r->flags = 0;
 216                                 }
 217                         }
 218                 }
 219                 pcibios_allocate_bus_resources(&bus->children);
 220         }
 221 }
 222
 223 static void __init pcibios_allocate_resources(int pass)
 224 {
 225         struct pci_dev *dev = NULL;
 226         int idx, disabled;
 227         u16 command;
 228         struct resource *r, *pr;
 229
 230         for_each_pci_dev(dev) {
 231                 pci_read_config_word(dev, PCI_COMMAND, &command);
 232                 for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) {
 233                         r = &dev->resource[idx];
 234                         if (r->parent)          /* Already allocated */
 235                                 continue;
 236                         if (!r->start)          /* Address not assigned at all */
 237                                 continue;
 238                         if (r->flags & IORESOURCE_IO)
 239                                 disabled = !(command & PCI_COMMAND_IO);
 240                         else
 241                                 disabled = !(command & PCI_COMMAND_MEMORY);
 242                         if (pass == disabled) {
 243                                 dev_dbg(&dev->dev, "resource %#08llx-%#08llx "
 244                                         "(f=%lx, d=%d, p=%d)\n",
 245                                         (unsigned long long) r->start,
 246                                         (unsigned long long) r->end,
 247                                         r->flags, disabled, pass);
 248                                 pr = pci_find_parent_resource(dev, r);
 249                                 if (!pr || request_resource(pr, r) < 0) {
 250                                         if (check_platform(dev, r))
 251                                                 continue;
 252                                         dev_err(&dev->dev, "BAR %d: can't "
 253                                                 "allocate resource\n", idx);
 254                                         /* We'll assign a new address later */
 255                                         r->end -= r->start;
 256                                         r->start = 0;
 257                                 }
 258                         }
 259                 }
 260                 if (!pass) {
 261                         r = &dev->resource[PCI_ROM_RESOURCE];
 262                         if (r->flags & IORESOURCE_ROM_ENABLE) {
 263                                 /* Turn the ROM off, leave the resource region,
 264                                  * but keep it unregistered. */
 265                                 u32 reg;
 266                                 dev_dbg(&dev->dev, "disabling ROM\n");
 267                                 r->flags &= ~IORESOURCE_ROM_ENABLE;
 268                                 pci_read_config_dword(dev,
 269                                                 dev->rom_base_reg, &reg);
 270                                 pci_write_config_dword(dev, dev->rom_base_reg,
 271                                                 reg & ~PCI_ROM_ADDRESS_ENABLE);
 272                         }
 273                 }
 274         }
 275 }
 276
 277 static int __init pcibios_assign_resources(void)
 278 {
 279         struct pci_dev *dev = NULL;
 280         struct resource *r, *pr;
 281
 282         if (!(pci_probe & PCI_ASSIGN_ROMS)) {
 283                 /*
 284                  * Try to use BIOS settings for ROMs, otherwise let
 285                  * pci_assign_unassigned_resources() allocate the new
 286                  * addresses.
 287                  */
 288                 for_each_pci_dev(dev) {
 289                         r = &dev->resource[PCI_ROM_RESOURCE];
 290                         if (!r->flags || !r->start)
 291                                 continue;
 292                         pr = pci_find_parent_resource(dev, r);
 293                         if (!pr || request_resource(pr, r) < 0) {
 294                                 r->end -= r->start;
 295                                 r->start = 0;
 296                         }
 297                 }
 298         }
 299
 300         pci_assign_unassigned_resources();
 301
 302         return 0;
 303 }
 304
 305 void __init pcibios_resource_survey(void)
 306 {
 307         DBG("PCI: Allocating resources\n");
 308         pcibios_allocate_bus_resources(&pci_root_buses);
 309         pcibios_allocate_resources(0);
 310         pcibios_allocate_resources(1);
 311 }
 312
 313 /**
 314  * called in fs_initcall (one below subsys_initcall),
 315  * give a chance for motherboard reserve resources
 316  */
 317 fs_initcall(pcibios_assign_resources);
 318
 319 /*
 320  *  If we set up a device for bus mastering, we need to check the latency
 321  *  timer as certain crappy BIOSes forget to set it properly.
 322  */
 323 unsigned int pcibios_max_latency = 255;
 324
 325 void pcibios_set_master(struct pci_dev *dev)
 326 {
 327         u8 lat;
 328         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 329         if (lat < 16)
 330                 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
 331         else if (lat > pcibios_max_latency)
 332                 lat = pcibios_max_latency;
 333         else
 334                 return;
 335         dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
 336         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 337 }
 338
 339 static void pci_unmap_page_range(struct vm_area_struct *vma)
 340 {
 341         u64 addr = (u64)vma->vm_pgoff << PAGE_SHIFT;
 342         free_memtype(addr, addr + vma->vm_end - vma->vm_start);
 343 }
 344
 345 static void pci_track_mmap_page_range(struct vm_area_struct *vma)
 346 {
 347         u64 addr = (u64)vma->vm_pgoff << PAGE_SHIFT;
 348         unsigned long flags = pgprot_val(vma->vm_page_prot)
 349                                                 & _PAGE_CACHE_MASK;
 350
 351         reserve_memtype(addr, addr + vma->vm_end - vma->vm_start, flags, NULL);
 352 }
 353
 354 static struct vm_operations_struct pci_mmap_ops = {
 355         .open  = pci_track_mmap_page_range,
 356         .close = pci_unmap_page_range,
 357         .access = generic_access_phys,
 358 };
 359
 360 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 361                         enum pci_mmap_state mmap_state, int write_combine)
 362 {
 363         unsigned long prot;
 364         u64 addr = vma->vm_pgoff << PAGE_SHIFT;
 365         unsigned long len = vma->vm_end - vma->vm_start;
 366         unsigned long flags;
 367         unsigned long new_flags;
 368         int retval;
 369
 370         /* I/O space cannot be accessed via normal processor loads and
 371          * stores on this platform.
 372          */
 373         if (mmap_state == pci_mmap_io)
 374                 return -EINVAL;
 375
 376         prot = pgprot_val(vma->vm_page_prot);
 377         if (pat_enabled && write_combine)
 378                 prot |= _PAGE_CACHE_WC;
 379         else if (pat_enabled || boot_cpu_data.x86 > 3)
 380                 /*
 381                  * ioremap() and ioremap_nocache() defaults to UC MINUS for now.
 382                  * To avoid attribute conflicts, request UC MINUS here
 383                  * aswell.
 384                  */
 385                 prot |= _PAGE_CACHE_UC_MINUS;
 386
 387         vma->vm_page_prot = __pgprot(prot);
 388
 389         flags = pgprot_val(vma->vm_page_prot) & _PAGE_CACHE_MASK;
 390         retval = reserve_memtype(addr, addr + len, flags, &new_flags);
 391         if (retval)
 392                 return retval;
 393
 394         if (flags != new_flags) {
 395                 /*
 396                  * Do not fallback to certain memory types with certain
 397                  * requested type:
 398                  * - request is uncached, return cannot be write-back
 399                  * - request is uncached, return cannot be write-combine
 400                  * - request is write-combine, return cannot be write-back
 401                  */
 402                 if ((flags == _PAGE_CACHE_UC_MINUS &&
 403                      (new_flags == _PAGE_CACHE_WB)) ||
 404                     (flags == _PAGE_CACHE_WC &&
 405                      new_flags == _PAGE_CACHE_WB)) {
 406                         free_memtype(addr, addr+len);
 407                         return -EINVAL;
 408                 }
 409                 flags = new_flags;
 410         }
 411
 412         if (((vma->vm_pgoff < max_low_pfn_mapped) ||
 413              (vma->vm_pgoff >= (1UL<<(32 - PAGE_SHIFT)) &&
 414               vma->vm_pgoff < max_pfn_mapped)) &&
 415             ioremap_change_attr((unsigned long)__va(addr), len, flags)) {
 416                 free_memtype(addr, addr + len);
 417                 return -EINVAL;
 418         }
 419
 420         if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 421                                vma->vm_end - vma->vm_start,
 422                                vma->vm_page_prot))
 423                 return -EAGAIN;
 424
 425         vma->vm_ops = &pci_mmap_ops;
 426
 427         return 0;
 428 }