2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003, 2004 Ralf Baechle
7 * Copyright (C) 2004 Maciej W. Rozycki
9 #ifndef __ASM_CPU_FEATURES_H
10 #define __ASM_CPU_FEATURES_H
14 #include <asm/cpu-info.h>
15 #include <cpu-feature-overrides.h>
18 * SMP assumption: Options of CPU 0 are a superset of all processors.
19 * This is true for all known MIPS systems.
22 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
25 #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
27 #ifndef cpu_has_3k_cache
28 #define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
30 #define cpu_has_6k_cache 0
31 #define cpu_has_8k_cache 0
32 #ifndef cpu_has_4k_cache
33 #define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
35 #ifndef cpu_has_tx39_cache
36 #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
38 #ifndef cpu_has_sb1_cache
39 #define cpu_has_sb1_cache (cpu_data[0].options & MIPS_CPU_SB1_CACHE)
42 #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
45 #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
47 #ifndef cpu_has_counter
48 #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
51 #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
54 #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
57 #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
59 #ifndef cpu_has_cache_cdex_p
60 #define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
62 #ifndef cpu_has_cache_cdex_s
63 #define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
65 #ifndef cpu_has_prefetch
66 #define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
68 #ifndef cpu_has_mcheck
69 #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
72 #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
75 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
77 #ifndef cpu_has_mips16
78 #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
81 #define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
83 #ifndef cpu_has_mips3d
84 #define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
86 #ifndef cpu_has_smartmips
87 #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
89 #ifndef cpu_has_vtag_icache
90 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
92 #ifndef cpu_has_dc_aliases
93 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
95 #ifndef cpu_has_ic_fills_f_dc
96 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
98 #ifndef cpu_has_pindexed_dcache
99 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
103 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
104 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
105 * don't. For maintaining I-cache coherency this means we need to flush the
106 * D-cache all the way back to whever the I-cache does refills from, so the
107 * I-cache has a chance to see the new data at all. Then we have to flush the
109 * Note we may have been rescheduled and may no longer be running on the CPU
110 * that did the store so we can't optimize this into only doing the flush on
113 #ifndef cpu_icache_snoops_remote_store
115 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
117 #define cpu_icache_snoops_remote_store 1
121 # ifndef cpu_has_mips32r1
122 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
124 # ifndef cpu_has_mips32r2
125 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
127 # ifndef cpu_has_mips64r1
128 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
130 # ifndef cpu_has_mips64r2
131 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
137 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
138 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
139 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
140 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
143 #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
146 #ifdef CONFIG_MIPS_MT
147 #ifndef cpu_has_mipsmt
148 # define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
151 # define cpu_has_mipsmt 0
155 # ifndef cpu_has_nofpuex
156 # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
158 # ifndef cpu_has_64bits
159 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
161 # ifndef cpu_has_64bit_zero_reg
162 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
164 # ifndef cpu_has_64bit_gp_regs
165 # define cpu_has_64bit_gp_regs 0
167 # ifndef cpu_has_64bit_addresses
168 # define cpu_has_64bit_addresses 0
173 # ifndef cpu_has_nofpuex
174 # define cpu_has_nofpuex 0
176 # ifndef cpu_has_64bits
177 # define cpu_has_64bits 1
179 # ifndef cpu_has_64bit_zero_reg
180 # define cpu_has_64bit_zero_reg 1
182 # ifndef cpu_has_64bit_gp_regs
183 # define cpu_has_64bit_gp_regs 1
185 # ifndef cpu_has_64bit_addresses
186 # define cpu_has_64bit_addresses 1
190 #ifdef CONFIG_CPU_MIPSR2
191 # if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
192 # define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
194 # define cpu_has_vint 0
196 # if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
197 # define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
199 # define cpu_has_veic 0
202 # define cpu_has_vint 0
203 # define cpu_has_veic 0
206 #ifndef cpu_has_subset_pcaches
207 #define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES)
210 #ifndef cpu_dcache_line_size
211 #define cpu_dcache_line_size() current_cpu_data.dcache.linesz
213 #ifndef cpu_icache_line_size
214 #define cpu_icache_line_size() current_cpu_data.icache.linesz
216 #ifndef cpu_scache_line_size
217 #define cpu_scache_line_size() current_cpu_data.scache.linesz
220 #endif /* __ASM_CPU_FEATURES_H */