2 * Copyright (C) 2000 David J. Mckay (david.mckay@st.com)
4 * May be copied or modified under the terms of the GNU General Public
5 * License. See linux/COPYING for more information.
10 #ifndef __OVERDRIVE_H__
11 #define __OVERDRIVE_H__
13 #define OVERDRIVE_INT_CT 0xa3a00000
14 #define OVERDRIVE_INT_DT 0xa3b00000
16 #define OVERDRIVE_CTRL 0xa3000000
18 /* Shoving all these bits into the same register is not a good idea.
19 * As soon as I get a spare moment, I'll change the FPGA and put each
20 * bit in a separate register
23 #define VALID_CTRL_BITS 0x1f
25 #define ENABLE_RS232_MASK 0x1e
26 #define DISABLE_RS232_BIT 0x01
28 #define ENABLE_NMI_MASK 0x1d
29 #define DISABLE_NMI_BIT 0x02
31 #define RESET_PCI_MASK 0x1b
32 #define ENABLE_PCI_BIT 0x04
34 #define ENABLE_LED_MASK 0x17
35 #define DISABLE_LED_BIT 0x08
37 #define RESET_FPGA_MASK 0x0f
38 #define ENABLE_FPGA_BIT 0x10
41 #define FPGA_DCLK_ADDRESS 0xA3C00000
43 #define FPGA_DATA 0x01 /* W */
44 #define FPGA_CONFDONE 0x02 /* R */
45 #define FPGA_NOT_STATUS 0x04 /* R */
46 #define FPGA_INITDONE 0x08 /* R */
48 #define FPGA_TIMEOUT 100000
51 /* Interrupts for the overdrive. Note that these numbers have
52 * nothing to do with the actual IRQ numbers they appear on,
53 * this is all programmable. This is simply the position in the
57 #define OVERDRIVE_PCI_INTA 0
58 #define OVERDRIVE_PCI_INTB 1
59 #define OVERDRIVE_PCI_INTC 2
60 #define OVERDRIVE_PCI_INTD 3
61 #define OVERDRIVE_GALILEO_INT 4
62 #define OVERDRIVE_GALILEO_LOCAL_INT 5
63 #define OVERDRIVE_AUDIO_INT 6
64 #define OVERDRIVE_KEYBOARD_INT 7
66 /* Which Linux IRQ should we assign to each interrupt source? */
67 #define OVERDRIVE_PCI_IRQ1 2
68 #ifdef CONFIG_HACKED_NE2K
69 #define OVERDRIVE_PCI_IRQ2 7
71 #define OVERDRIVE_PCI_IRQ2 2
72 #undef OVERDRIVE_PCI_INTB
73 #define OVERDRIVE_PCI_INTB OVERDRIVE_PCI_INTA
77 /* Put the ESS solo audio chip on IRQ 4 */
78 #define OVERDRIVE_ESS_IRQ 4
80 /* Where the memory behind the PCI bus appears */
81 #define PCI_DRAM_BASE 0xb7000000
82 #define PCI_DRAM_SIZE (16*1024*1024)
83 #define PCI_DRAM_FINISH (PCI_DRAM_BASE+PCI_DRAM_SIZE-1)
85 /* Where the IO region appears in the memory */
86 #define PCI_GTIO_BASE 0xb8000000