1 #ifndef __ASM_SH_SYSTEM_H
2 #define __ASM_SH_SYSTEM_H
5 * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
6 * Copyright (C) 2002 Paul Mundt
11 * switch_to() should switch tasks to task nr n, first
14 #define switch_to(prev, next, last) do { \
16 register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp; \
17 register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc; \
18 register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev; \
19 register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next; \
20 register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp; \
21 register unsigned long __ts7 __asm__ ("r7") = next->thread.pc; \
22 __asm__ __volatile__ (".balign 4\n\t" \
23 "stc.l gbr, @-r15\n\t" \
24 "sts.l pr, @-r15\n\t" \
25 "mov.l r8, @-r15\n\t" \
26 "mov.l r9, @-r15\n\t" \
27 "mov.l r10, @-r15\n\t" \
28 "mov.l r11, @-r15\n\t" \
29 "mov.l r12, @-r15\n\t" \
30 "mov.l r13, @-r15\n\t" \
31 "mov.l r14, @-r15\n\t" \
32 "mov.l r15, @r1 ! save SP\n\t" \
33 "mov.l @r6, r15 ! change to new stack\n\t" \
35 "mov.l %0, @r2 ! save PC\n\t" \
37 "jmp @%0 ! call __switch_to\n\t" \
38 " lds r7, pr ! with return to new PC\n\t" \
41 ".long __switch_to\n" \
43 "mov.l @r15+, r14\n\t" \
44 "mov.l @r15+, r13\n\t" \
45 "mov.l @r15+, r12\n\t" \
46 "mov.l @r15+, r11\n\t" \
47 "mov.l @r15+, r10\n\t" \
48 "mov.l @r15+, r9\n\t" \
49 "mov.l @r15+, r8\n\t" \
50 "lds.l @r15+, pr\n\t" \
51 "ldc.l @r15+, gbr\n\t" \
53 : "r" (__ts1), "r" (__ts2), "r" (__ts4), \
54 "r" (__ts5), "r" (__ts6), "r" (__ts7) \
60 * On SMP systems, when the scheduler does migration-cost autodetection,
61 * it needs a way to flush as much of the CPU's caches as possible.
65 static inline void sched_cacheflush(void)
69 #define nop() __asm__ __volatile__ ("nop")
72 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
74 static __inline__ unsigned long tas(volatile int *m)
75 { /* #define tas(ptr) (xchg((ptr),1)) */
78 __asm__ __volatile__ ("tas.b @%1\n\t"
80 : "=r" (retval): "r" (m): "t", "memory");
84 extern void __xchg_called_with_bad_pointer(void);
86 #define mb() __asm__ __volatile__ ("": : :"memory")
88 #define wmb() __asm__ __volatile__ ("": : :"memory")
89 #define read_barrier_depends() do { } while(0)
93 #define smp_rmb() rmb()
94 #define smp_wmb() wmb()
95 #define smp_read_barrier_depends() read_barrier_depends()
97 #define smp_mb() barrier()
98 #define smp_rmb() barrier()
99 #define smp_wmb() barrier()
100 #define smp_read_barrier_depends() do { } while(0)
103 #define set_mb(var, value) do { xchg(&var, value); } while (0)
104 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
106 /* Interrupt Control */
107 static __inline__ void local_irq_enable(void)
109 unsigned long __dummy0, __dummy1;
111 __asm__ __volatile__("stc sr, %0\n\t"
113 "stc r6_bank, %1\n\t"
116 : "=&r" (__dummy0), "=r" (__dummy1)
121 static __inline__ void local_irq_disable(void)
123 unsigned long __dummy;
124 __asm__ __volatile__("stc sr, %0\n\t"
132 #define local_save_flags(x) \
133 __asm__("stc sr, %0; and #0xf0, %0" : "=&z" (x) :/**/: "memory" )
135 #define irqs_disabled() \
137 unsigned long flags; \
138 local_save_flags(flags); \
142 static __inline__ unsigned long local_irq_save(void)
144 unsigned long flags, __dummy;
146 __asm__ __volatile__("stc sr, %1\n\t"
152 : "=&z" (flags), "=&r" (__dummy)
159 static __inline__ void local_irq_restore(unsigned long x)
161 if ((x & 0x000000f0) != 0x000000f0)
165 local_save_flags(flags);
168 extern void dump_stack(void);
169 printk(KERN_ERR "BUG!\n");
176 #define local_irq_restore(x) do { \
177 if ((x & 0x000000f0) != 0x000000f0) \
178 local_irq_enable(); \
182 #define really_restore_flags(x) do { \
183 if ((x & 0x000000f0) != 0x000000f0) \
184 local_irq_enable(); \
186 local_irq_disable(); \
191 * When handling TLB or caches, we need to do it from P2 area.
193 #define jump_to_P2() \
195 unsigned long __dummy; \
196 __asm__ __volatile__( \
205 : "r" (0x20000000)); \
211 #define back_to_P1() \
213 unsigned long __dummy; \
214 __asm__ __volatile__( \
215 "nop;nop;nop;nop;nop;nop;nop\n\t" \
222 : "=&r" (__dummy)); \
225 /* For spinlocks etc */
226 #define local_irq_save(x) x = local_irq_save()
228 static __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
230 unsigned long flags, retval;
232 local_irq_save(flags);
235 local_irq_restore(flags);
239 static __inline__ unsigned long xchg_u8(volatile unsigned char * m, unsigned long val)
241 unsigned long flags, retval;
243 local_irq_save(flags);
246 local_irq_restore(flags);
250 static __inline__ unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
254 return xchg_u32(ptr, x);
257 return xchg_u8(ptr, x);
260 __xchg_called_with_bad_pointer();
265 * disable hlt during certain critical i/o operations
267 #define HAVE_DISABLE_HLT
268 void disable_hlt(void);
269 void enable_hlt(void);
271 #define arch_align_stack(x) (x)