1 /******************************************************************************
4 * Project: Gigabit Ethernet Adapters, Common Modules
5 * Version: $Revision: 1.56 $
6 * Date: $Date: 2003/09/23 09:01:00 $
7 * Purpose: Defines and Macros for the Gigabit Ethernet Adapter Product Family
9 ******************************************************************************/
11 /******************************************************************************
13 * (C)Copyright 1998-2002 SysKonnect.
14 * (C)Copyright 2002-2003 Marvell.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * The information in this file is provided "AS IS" without warranty.
23 ******************************************************************************/
25 #ifndef __INC_SKGEHW_H
26 #define __INC_SKGEHW_H
30 #endif /* __cplusplus */
32 /* defines ********************************************************************/
34 #define BIT_31 (1UL << 31)
35 #define BIT_30 (1L << 30)
36 #define BIT_29 (1L << 29)
37 #define BIT_28 (1L << 28)
38 #define BIT_27 (1L << 27)
39 #define BIT_26 (1L << 26)
40 #define BIT_25 (1L << 25)
41 #define BIT_24 (1L << 24)
42 #define BIT_23 (1L << 23)
43 #define BIT_22 (1L << 22)
44 #define BIT_21 (1L << 21)
45 #define BIT_20 (1L << 20)
46 #define BIT_19 (1L << 19)
47 #define BIT_18 (1L << 18)
48 #define BIT_17 (1L << 17)
49 #define BIT_16 (1L << 16)
50 #define BIT_15 (1L << 15)
51 #define BIT_14 (1L << 14)
52 #define BIT_13 (1L << 13)
53 #define BIT_12 (1L << 12)
54 #define BIT_11 (1L << 11)
55 #define BIT_10 (1L << 10)
56 #define BIT_9 (1L << 9)
57 #define BIT_8 (1L << 8)
58 #define BIT_7 (1L << 7)
59 #define BIT_6 (1L << 6)
60 #define BIT_5 (1L << 5)
61 #define BIT_4 (1L << 4)
62 #define BIT_3 (1L << 3)
63 #define BIT_2 (1L << 2)
64 #define BIT_1 (1L << 1)
67 #define BIT_15S (1U << 15)
68 #define BIT_14S (1 << 14)
69 #define BIT_13S (1 << 13)
70 #define BIT_12S (1 << 12)
71 #define BIT_11S (1 << 11)
72 #define BIT_10S (1 << 10)
73 #define BIT_9S (1 << 9)
74 #define BIT_8S (1 << 8)
75 #define BIT_7S (1 << 7)
76 #define BIT_6S (1 << 6)
77 #define BIT_5S (1 << 5)
78 #define BIT_4S (1 << 4)
79 #define BIT_3S (1 << 3)
80 #define BIT_2S (1 << 2)
81 #define BIT_1S (1 << 1)
84 #define SHIFT31(x) ((x) << 31)
85 #define SHIFT30(x) ((x) << 30)
86 #define SHIFT29(x) ((x) << 29)
87 #define SHIFT28(x) ((x) << 28)
88 #define SHIFT27(x) ((x) << 27)
89 #define SHIFT26(x) ((x) << 26)
90 #define SHIFT25(x) ((x) << 25)
91 #define SHIFT24(x) ((x) << 24)
92 #define SHIFT23(x) ((x) << 23)
93 #define SHIFT22(x) ((x) << 22)
94 #define SHIFT21(x) ((x) << 21)
95 #define SHIFT20(x) ((x) << 20)
96 #define SHIFT19(x) ((x) << 19)
97 #define SHIFT18(x) ((x) << 18)
98 #define SHIFT17(x) ((x) << 17)
99 #define SHIFT16(x) ((x) << 16)
100 #define SHIFT15(x) ((x) << 15)
101 #define SHIFT14(x) ((x) << 14)
102 #define SHIFT13(x) ((x) << 13)
103 #define SHIFT12(x) ((x) << 12)
104 #define SHIFT11(x) ((x) << 11)
105 #define SHIFT10(x) ((x) << 10)
106 #define SHIFT9(x) ((x) << 9)
107 #define SHIFT8(x) ((x) << 8)
108 #define SHIFT7(x) ((x) << 7)
109 #define SHIFT6(x) ((x) << 6)
110 #define SHIFT5(x) ((x) << 5)
111 #define SHIFT4(x) ((x) << 4)
112 #define SHIFT3(x) ((x) << 3)
113 #define SHIFT2(x) ((x) << 2)
114 #define SHIFT1(x) ((x) << 1)
115 #define SHIFT0(x) ((x) << 0)
118 * Configuration Space header
119 * Since this module is used for different OS', those may be
120 * duplicate on some of them (e.g. Linux). But to keep the
121 * common source, we have to live with this...
123 #define PCI_VENDOR_ID 0x00 /* 16 bit Vendor ID */
124 #define PCI_DEVICE_ID 0x02 /* 16 bit Device ID */
125 #define PCI_COMMAND 0x04 /* 16 bit Command */
126 #define PCI_STATUS 0x06 /* 16 bit Status */
127 #define PCI_REV_ID 0x08 /* 8 bit Revision ID */
128 #define PCI_CLASS_CODE 0x09 /* 24 bit Class Code */
129 #define PCI_CACHE_LSZ 0x0c /* 8 bit Cache Line Size */
130 #define PCI_LAT_TIM 0x0d /* 8 bit Latency Timer */
131 #define PCI_HEADER_T 0x0e /* 8 bit Header Type */
132 #define PCI_BIST 0x0f /* 8 bit Built-in selftest */
133 #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
134 #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
135 /* Byte 0x18..0x2b: reserved */
136 #define PCI_SUB_VID 0x2c /* 16 bit Subsystem Vendor ID */
137 #define PCI_SUB_ID 0x2e /* 16 bit Subsystem ID */
138 #define PCI_BASE_ROM 0x30 /* 32 bit Expansion ROM Base Address */
139 #define PCI_CAP_PTR 0x34 /* 8 bit Capabilities Ptr */
140 /* Byte 0x35..0x3b: reserved */
141 #define PCI_IRQ_LINE 0x3c /* 8 bit Interrupt Line */
142 #define PCI_IRQ_PIN 0x3d /* 8 bit Interrupt Pin */
143 #define PCI_MIN_GNT 0x3e /* 8 bit Min_Gnt */
144 #define PCI_MAX_LAT 0x3f /* 8 bit Max_Lat */
145 /* Device Dependent Region */
146 #define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */
147 #define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */
148 /* Power Management Region */
149 #define PCI_PM_CAP_ID 0x48 /* 8 bit Power Management Cap. ID */
150 #define PCI_PM_NITEM 0x49 /* 8 bit Next Item Ptr */
151 #define PCI_PM_CAP_REG 0x4a /* 16 bit Power Management Capabilities */
152 #define PCI_PM_CTL_STS 0x4c /* 16 bit Power Manag. Control/Status */
153 /* Byte 0x4e: reserved */
154 #define PCI_PM_DAT_REG 0x4f /* 8 bit Power Manag. Data Register */
156 #define PCI_VPD_CAP_ID 0x50 /* 8 bit VPD Cap. ID */
157 #define PCI_VPD_NITEM 0x51 /* 8 bit Next Item Ptr */
158 #define PCI_VPD_ADR_REG 0x52 /* 16 bit VPD Address Register */
159 #define PCI_VPD_DAT_REG 0x54 /* 32 bit VPD Data Register */
160 /* Byte 0x58..0x59: reserved */
161 #define PCI_SER_LD_CTRL 0x5a /* 16 bit SEEPROM Loader Ctrl (YUKON only) */
162 /* Byte 0x5c..0xff: reserved */
165 * I2C Address (PCI Config)
167 * Note: The temperature and voltage sensors are relocated on a different
170 #define I2C_ADDR_VPD 0xa0 /* I2C address for the VPD EEPROM */
173 * Define Bits and Values of the registers
175 /* PCI_COMMAND 16 bit Command */
176 /* Bit 15..11: reserved */
177 #define PCI_INT_DIS BIT_10S /* Interrupt INTx# disable (PCI 2.3) */
178 #define PCI_FBTEN BIT_9S /* Fast Back-To-Back enable */
179 #define PCI_SERREN BIT_8S /* SERR enable */
180 #define PCI_ADSTEP BIT_7S /* Address Stepping */
181 #define PCI_PERREN BIT_6S /* Parity Report Response enable */
182 #define PCI_VGA_SNOOP BIT_5S /* VGA palette snoop */
183 #define PCI_MWIEN BIT_4S /* Memory write an inv cycl ena */
184 #define PCI_SCYCEN BIT_3S /* Special Cycle enable */
185 #define PCI_BMEN BIT_2S /* Bus Master enable */
186 #define PCI_MEMEN BIT_1S /* Memory Space Access enable */
187 #define PCI_IOEN BIT_0S /* I/O Space Access enable */
189 #define PCI_COMMAND_VAL (PCI_FBTEN | PCI_SERREN | PCI_PERREN | PCI_MWIEN |\
190 PCI_BMEN | PCI_MEMEN | PCI_IOEN)
192 /* PCI_STATUS 16 bit Status */
193 #define PCI_PERR BIT_15S /* Parity Error */
194 #define PCI_SERR BIT_14S /* Signaled SERR */
195 #define PCI_RMABORT BIT_13S /* Received Master Abort */
196 #define PCI_RTABORT BIT_12S /* Received Target Abort */
197 /* Bit 11: reserved */
198 #define PCI_DEVSEL (3<<9) /* Bit 10.. 9: DEVSEL Timing */
199 #define PCI_DEV_FAST (0<<9) /* fast */
200 #define PCI_DEV_MEDIUM (1<<9) /* medium */
201 #define PCI_DEV_SLOW (2<<9) /* slow */
202 #define PCI_DATAPERR BIT_8S /* DATA Parity error detected */
203 #define PCI_FB2BCAP BIT_7S /* Fast Back-to-Back Capability */
204 #define PCI_UDF BIT_6S /* User Defined Features */
205 #define PCI_66MHZCAP BIT_5S /* 66 MHz PCI bus clock capable */
206 #define PCI_NEWCAP BIT_4S /* New cap. list implemented */
207 #define PCI_INT_STAT BIT_3S /* Interrupt INTx# Status (PCI 2.3) */
208 /* Bit 2.. 0: reserved */
210 #define PCI_ERRBITS (PCI_PERR | PCI_SERR | PCI_RMABORT | PCI_RTABORT |\
213 /* PCI_CLASS_CODE 24 bit Class Code */
214 /* Byte 2: Base Class (02) */
215 /* Byte 1: SubClass (00) */
216 /* Byte 0: Programming Interface (00) */
218 /* PCI_CACHE_LSZ 8 bit Cache Line Size */
219 /* Possible values: 0,2,4,8,16,32,64,128 */
221 /* PCI_HEADER_T 8 bit Header Type */
222 #define PCI_HD_MF_DEV BIT_7S /* 0= single, 1= multi-func dev */
223 #define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout 0= normal */
225 /* PCI_BIST 8 bit Built-in selftest */
226 /* Built-in Self test not supported (optional) */
228 /* PCI_BASE_1ST 32 bit 1st Base address */
229 #define PCI_MEMSIZE 0x4000L /* use 16 kB Memory Base */
230 #define PCI_MEMBASE_MSK 0xffffc000L /* Bit 31..14: Memory Base Address */
231 #define PCI_MEMSIZE_MSK 0x00003ff0L /* Bit 13.. 4: Memory Size Req. */
232 #define PCI_PREFEN BIT_3 /* Prefetchable */
233 #define PCI_MEM_TYP (3L<<2) /* Bit 2.. 1: Memory Type */
234 #define PCI_MEM32BIT (0L<<1) /* Base addr anywhere in 32 Bit range */
235 #define PCI_MEM1M (1L<<1) /* Base addr below 1 MegaByte */
236 #define PCI_MEM64BIT (2L<<1) /* Base addr anywhere in 64 Bit range */
237 #define PCI_MEMSPACE BIT_0 /* Memory Space Indicator */
239 /* PCI_BASE_2ND 32 bit 2nd Base address */
240 #define PCI_IOBASE 0xffffff00L /* Bit 31.. 8: I/O Base address */
241 #define PCI_IOSIZE 0x000000fcL /* Bit 7.. 2: I/O Size Requirements */
242 /* Bit 1: reserved */
243 #define PCI_IOSPACE BIT_0 /* I/O Space Indicator */
245 /* PCI_BASE_ROM 32 bit Expansion ROM Base Address */
246 #define PCI_ROMBASE_MSK 0xfffe0000L /* Bit 31..17: ROM Base address */
247 #define PCI_ROMBASE_SIZ (0x1cL<<14) /* Bit 16..14: Treat as Base or Size */
248 #define PCI_ROMSIZE (0x38L<<11) /* Bit 13..11: ROM Size Requirements */
249 /* Bit 10.. 1: reserved */
250 #define PCI_ROMEN BIT_0 /* Address Decode enable */
252 /* Device Dependent Region */
253 /* PCI_OUR_REG_1 32 bit Our Register 1 */
254 /* Bit 31..29: reserved */
255 #define PCI_PHY_COMA BIT_28 /* Set PHY to Coma Mode (YUKON only) */
256 #define PCI_TEST_CAL BIT_27 /* Test PCI buffer calib. (YUKON only) */
257 #define PCI_EN_CAL BIT_26 /* Enable PCI buffer calib. (YUKON only) */
258 #define PCI_VIO BIT_25 /* PCI I/O Voltage, 0 = 3.3V, 1 = 5V */
259 #define PCI_DIS_BOOT BIT_24 /* Disable BOOT via ROM */
260 #define PCI_EN_IO BIT_23 /* Mapping to I/O space */
261 #define PCI_EN_FPROM BIT_22 /* Enable FLASH mapping to memory */
262 /* 1 = Map Flash to memory */
263 /* 0 = Disable addr. dec */
264 #define PCI_PAGESIZE (3L<<20) /* Bit 21..20: FLASH Page Size */
265 #define PCI_PAGE_16 (0L<<20) /* 16 k pages */
266 #define PCI_PAGE_32K (1L<<20) /* 32 k pages */
267 #define PCI_PAGE_64K (2L<<20) /* 64 k pages */
268 #define PCI_PAGE_128K (3L<<20) /* 128 k pages */
269 /* Bit 19: reserved */
270 #define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */
271 #define PCI_NOTAR BIT_15 /* No turnaround cycle */
272 #define PCI_FORCE_BE BIT_14 /* Assert all BEs on MR */
273 #define PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */
274 #define PCI_DIS_MRM BIT_12 /* Disable Mem Read Multiple */
275 #define PCI_DIS_MWI BIT_11 /* Disable Mem Write & Invalidate */
276 #define PCI_DISC_CLS BIT_10 /* Disc: cacheLsz bound */
277 #define PCI_BURST_DIS BIT_9 /* Burst Disable */
278 #define PCI_DIS_PCI_CLK BIT_8 /* Disable PCI clock driving */
279 #define PCI_SKEW_DAS (0xfL<<4) /* Bit 7.. 4: Skew Ctrl, DAS Ext */
280 #define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */
283 /* PCI_OUR_REG_2 32 bit Our Register 2 */
284 #define PCI_VPD_WR_THR (0xffL<<24) /* Bit 31..24: VPD Write Threshold */
285 #define PCI_DEV_SEL (0x7fL<<17) /* Bit 23..17: EEPROM Device Select */
286 #define PCI_VPD_ROM_SZ (7L<<14) /* Bit 16..14: VPD ROM Size */
287 /* Bit 13..12: reserved */
288 #define PCI_PATCH_DIR (0xfL<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */
289 #define PCI_PATCH_DIR_3 BIT_11
290 #define PCI_PATCH_DIR_2 BIT_10
291 #define PCI_PATCH_DIR_1 BIT_9
292 #define PCI_PATCH_DIR_0 BIT_8
293 #define PCI_EXT_PATCHS (0xfL<<4) /* Bit 7.. 4: Extended Patches 3..0 */
294 #define PCI_EXT_PATCH_3 BIT_7
295 #define PCI_EXT_PATCH_2 BIT_6
296 #define PCI_EXT_PATCH_1 BIT_5
297 #define PCI_EXT_PATCH_0 BIT_4
298 #define PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */
299 #define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */
300 /* Bit 1: reserved */
301 #define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */
304 /* Power Management Region */
305 /* PCI_PM_CAP_REG 16 bit Power Management Capabilities */
306 #define PCI_PME_SUP_MSK (0x1f<<11) /* Bit 15..11: PM Event Support Mask */
307 #define PCI_PME_D3C_SUP BIT_15S /* PME from D3cold Support (if Vaux) */
308 #define PCI_PME_D3H_SUP BIT_14S /* PME from D3hot Support */
309 #define PCI_PME_D2_SUP BIT_13S /* PME from D2 Support */
310 #define PCI_PME_D1_SUP BIT_12S /* PME from D1 Support */
311 #define PCI_PME_D0_SUP BIT_11S /* PME from D0 Support */
312 #define PCI_PM_D2_SUP BIT_10S /* D2 Support in 33 MHz mode */
313 #define PCI_PM_D1_SUP BIT_9S /* D1 Support */
314 /* Bit 8.. 6: reserved */
315 #define PCI_PM_DSI BIT_5S /* Device Specific Initialization */
316 #define PCI_PM_APS BIT_4S /* Auxialiary Power Source */
317 #define PCI_PME_CLOCK BIT_3S /* PM Event Clock */
318 #define PCI_PM_VER_MSK 7 /* Bit 2.. 0: PM PCI Spec. version */
320 /* PCI_PM_CTL_STS 16 bit Power Management Control/Status */
321 #define PCI_PME_STATUS BIT_15S /* PME Status (YUKON only) */
322 #define PCI_PM_DAT_SCL (3<<13) /* Bit 14..13: Data Reg. scaling factor */
323 #define PCI_PM_DAT_SEL (0xf<<9) /* Bit 12.. 9: PM data selector field */
324 #define PCI_PME_EN BIT_8S /* Enable PME# generation (YUKON only) */
325 /* Bit 7.. 2: reserved */
326 #define PCI_PM_STATE_MSK 3 /* Bit 1.. 0: Power Management State */
328 #define PCI_PM_STATE_D0 0 /* D0: Operational (default) */
329 #define PCI_PM_STATE_D1 1 /* D1: (YUKON only) */
330 #define PCI_PM_STATE_D2 2 /* D2: (YUKON only) */
331 #define PCI_PM_STATE_D3 3 /* D3: HOT, Power Down and Reset */
334 /* PCI_VPD_ADR_REG 16 bit VPD Address Register */
335 #define PCI_VPD_FLAG BIT_15S /* starts VPD rd/wr cycle */
336 #define PCI_VPD_ADR_MSK 0x7fffL /* Bit 14.. 0: VPD address mask */
338 /* Control Register File (Address Map) */
343 #define B0_RAP 0x0000 /* 8 bit Register Address Port */
344 /* 0x0001 - 0x0003: reserved */
345 #define B0_CTST 0x0004 /* 16 bit Control/Status register */
346 #define B0_LED 0x0006 /* 8 Bit LED register */
347 #define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */
348 #define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */
349 #define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */
350 #define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */
351 #define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */
352 #define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg */
353 /* 0x001c: reserved */
355 /* B0 XMAC 1 registers (GENESIS only) */
356 #define B0_XM1_IMSK 0x0020 /* 16 bit r/w XMAC 1 Interrupt Mask Register*/
357 /* 0x0022 - 0x0027: reserved */
358 #define B0_XM1_ISRC 0x0028 /* 16 bit ro XMAC 1 Interrupt Status Reg */
359 /* 0x002a - 0x002f: reserved */
360 #define B0_XM1_PHY_ADDR 0x0030 /* 16 bit r/w XMAC 1 PHY Address Register */
361 /* 0x0032 - 0x0033: reserved */
362 #define B0_XM1_PHY_DATA 0x0034 /* 16 bit r/w XMAC 1 PHY Data Register */
363 /* 0x0036 - 0x003f: reserved */
365 /* B0 XMAC 2 registers (GENESIS only) */
366 #define B0_XM2_IMSK 0x0040 /* 16 bit r/w XMAC 2 Interrupt Mask Register*/
367 /* 0x0042 - 0x0047: reserved */
368 #define B0_XM2_ISRC 0x0048 /* 16 bit ro XMAC 2 Interrupt Status Reg */
369 /* 0x004a - 0x004f: reserved */
370 #define B0_XM2_PHY_ADDR 0x0050 /* 16 bit r/w XMAC 2 PHY Address Register */
371 /* 0x0052 - 0x0053: reserved */
372 #define B0_XM2_PHY_DATA 0x0054 /* 16 bit r/w XMAC 2 PHY Data Register */
373 /* 0x0056 - 0x005f: reserved */
375 /* BMU Control Status Registers */
376 #define B0_R1_CSR 0x0060 /* 32 bit BMU Ctrl/Stat Rx Queue 1 */
377 #define B0_R2_CSR 0x0064 /* 32 bit BMU Ctrl/Stat Rx Queue 2 */
378 #define B0_XS1_CSR 0x0068 /* 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
379 #define B0_XA1_CSR 0x006c /* 32 bit BMU Ctrl/Stat Async Tx Queue 1*/
380 #define B0_XS2_CSR 0x0070 /* 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
381 #define B0_XA2_CSR 0x0074 /* 32 bit BMU Ctrl/Stat Async Tx Queue 2*/
382 /* 0x0078 - 0x007f: reserved */
386 * - completely empty (this is the RAP Block window)
387 * Note: if RAP = 1 this page is reserved
393 /* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */
394 #define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */
395 /* 0x0106 - 0x0107: reserved */
396 #define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */
397 /* 0x010e - 0x010f: reserved */
398 #define B2_MAC_3 0x0110 /* NA reg MAC Address 3 */
399 /* 0x0116 - 0x0117: reserved */
400 #define B2_CONN_TYP 0x0118 /* 8 bit Connector type */
401 #define B2_PMD_TYP 0x0119 /* 8 bit PMD type */
402 #define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */
403 #define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */
404 /* Eprom registers are currently of no use */
405 #define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */
406 #define B2_E_1 0x011d /* 8 bit EPROM Byte 1 (PHY type) */
407 #define B2_E_2 0x011e /* 8 bit EPROM Byte 2 */
408 #define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */
409 #define B2_FAR 0x0120 /* 32 bit Flash-Prom Addr Reg/Cnt */
410 #define B2_FDP 0x0124 /* 8 bit Flash-Prom Data Port */
411 /* 0x0125 - 0x0127: reserved */
412 #define B2_LD_CTRL 0x0128 /* 8 bit EPROM loader control register */
413 #define B2_LD_TEST 0x0129 /* 8 bit EPROM loader test register */
414 /* 0x012a - 0x012f: reserved */
415 #define B2_TI_INI 0x0130 /* 32 bit Timer Init Value */
416 #define B2_TI_VAL 0x0134 /* 32 bit Timer Value */
417 #define B2_TI_CTRL 0x0138 /* 8 bit Timer Control */
418 #define B2_TI_TEST 0x0139 /* 8 Bit Timer Test */
419 /* 0x013a - 0x013f: reserved */
420 #define B2_IRQM_INI 0x0140 /* 32 bit IRQ Moderation Timer Init Reg.*/
421 #define B2_IRQM_VAL 0x0144 /* 32 bit IRQ Moderation Timer Value */
422 #define B2_IRQM_CTRL 0x0148 /* 8 bit IRQ Moderation Timer Control */
423 #define B2_IRQM_TEST 0x0149 /* 8 bit IRQ Moderation Timer Test */
424 #define B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */
425 #define B2_IRQM_HWE_MSK 0x0150 /* 32 bit IRQ Moderation HW Error Mask */
426 /* 0x0154 - 0x0157: reserved */
427 #define B2_TST_CTRL1 0x0158 /* 8 bit Test Control Register 1 */
428 #define B2_TST_CTRL2 0x0159 /* 8 bit Test Control Register 2 */
429 /* 0x015a - 0x015b: reserved */
430 #define B2_GP_IO 0x015c /* 32 bit General Purpose I/O Register */
431 #define B2_I2C_CTRL 0x0160 /* 32 bit I2C HW Control Register */
432 #define B2_I2C_DATA 0x0164 /* 32 bit I2C HW Data Register */
433 #define B2_I2C_IRQ 0x0168 /* 32 bit I2C HW IRQ Register */
434 #define B2_I2C_SW 0x016c /* 32 bit I2C SW Port Register */
436 /* Blink Source Counter (GENESIS only) */
437 #define B2_BSC_INI 0x0170 /* 32 bit Blink Source Counter Init Val */
438 #define B2_BSC_VAL 0x0174 /* 32 bit Blink Source Counter Value */
439 #define B2_BSC_CTRL 0x0178 /* 8 bit Blink Source Counter Control */
440 #define B2_BSC_STAT 0x0179 /* 8 bit Blink Source Counter Status */
441 #define B2_BSC_TST 0x017a /* 16 bit Blink Source Counter Test Reg */
442 /* 0x017c - 0x017f: reserved */
447 /* RAM Random Registers */
448 #define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */
449 #define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */
450 #define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */
451 /* 0x018c - 0x018f: reserved */
453 /* RAM Interface Registers */
455 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
456 * not usable in SW. Please notice these are NOT real timeouts, these are
457 * the number of qWords transferred continuously.
459 #define B3_RI_WTO_R1 0x0190 /* 8 bit WR Timeout Queue R1 (TO0) */
460 #define B3_RI_WTO_XA1 0x0191 /* 8 bit WR Timeout Queue XA1 (TO1) */
461 #define B3_RI_WTO_XS1 0x0192 /* 8 bit WR Timeout Queue XS1 (TO2) */
462 #define B3_RI_RTO_R1 0x0193 /* 8 bit RD Timeout Queue R1 (TO3) */
463 #define B3_RI_RTO_XA1 0x0194 /* 8 bit RD Timeout Queue XA1 (TO4) */
464 #define B3_RI_RTO_XS1 0x0195 /* 8 bit RD Timeout Queue XS1 (TO5) */
465 #define B3_RI_WTO_R2 0x0196 /* 8 bit WR Timeout Queue R2 (TO6) */
466 #define B3_RI_WTO_XA2 0x0197 /* 8 bit WR Timeout Queue XA2 (TO7) */
467 #define B3_RI_WTO_XS2 0x0198 /* 8 bit WR Timeout Queue XS2 (TO8) */
468 #define B3_RI_RTO_R2 0x0199 /* 8 bit RD Timeout Queue R2 (TO9) */
469 #define B3_RI_RTO_XA2 0x019a /* 8 bit RD Timeout Queue XA2 (TO10)*/
470 #define B3_RI_RTO_XS2 0x019b /* 8 bit RD Timeout Queue XS2 (TO11)*/
471 #define B3_RI_TO_VAL 0x019c /* 8 bit Current Timeout Count Val */
472 /* 0x019d - 0x019f: reserved */
473 #define B3_RI_CTRL 0x01a0 /* 16 bit RAM Interface Control Register */
474 #define B3_RI_TEST 0x01a2 /* 8 bit RAM Interface Test Register */
475 /* 0x01a3 - 0x01af: reserved */
477 /* MAC Arbiter Registers (GENESIS only) */
478 /* these are the no. of qWord transferred continuously and NOT real timeouts */
479 #define B3_MA_TOINI_RX1 0x01b0 /* 8 bit Timeout Init Val Rx Path MAC 1 */
480 #define B3_MA_TOINI_RX2 0x01b1 /* 8 bit Timeout Init Val Rx Path MAC 2 */
481 #define B3_MA_TOINI_TX1 0x01b2 /* 8 bit Timeout Init Val Tx Path MAC 1 */
482 #define B3_MA_TOINI_TX2 0x01b3 /* 8 bit Timeout Init Val Tx Path MAC 2 */
483 #define B3_MA_TOVAL_RX1 0x01b4 /* 8 bit Timeout Value Rx Path MAC 1 */
484 #define B3_MA_TOVAL_RX2 0x01b5 /* 8 bit Timeout Value Rx Path MAC 1 */
485 #define B3_MA_TOVAL_TX1 0x01b6 /* 8 bit Timeout Value Tx Path MAC 2 */
486 #define B3_MA_TOVAL_TX2 0x01b7 /* 8 bit Timeout Value Tx Path MAC 2 */
487 #define B3_MA_TO_CTRL 0x01b8 /* 16 bit MAC Arbiter Timeout Ctrl Reg */
488 #define B3_MA_TO_TEST 0x01ba /* 16 bit MAC Arbiter Timeout Test Reg */
489 /* 0x01bc - 0x01bf: reserved */
490 #define B3_MA_RCINI_RX1 0x01c0 /* 8 bit Recovery Init Val Rx Path MAC 1 */
491 #define B3_MA_RCINI_RX2 0x01c1 /* 8 bit Recovery Init Val Rx Path MAC 2 */
492 #define B3_MA_RCINI_TX1 0x01c2 /* 8 bit Recovery Init Val Tx Path MAC 1 */
493 #define B3_MA_RCINI_TX2 0x01c3 /* 8 bit Recovery Init Val Tx Path MAC 2 */
494 #define B3_MA_RCVAL_RX1 0x01c4 /* 8 bit Recovery Value Rx Path MAC 1 */
495 #define B3_MA_RCVAL_RX2 0x01c5 /* 8 bit Recovery Value Rx Path MAC 1 */
496 #define B3_MA_RCVAL_TX1 0x01c6 /* 8 bit Recovery Value Tx Path MAC 2 */
497 #define B3_MA_RCVAL_TX2 0x01c7 /* 8 bit Recovery Value Tx Path MAC 2 */
498 #define B3_MA_RC_CTRL 0x01c8 /* 16 bit MAC Arbiter Recovery Ctrl Reg */
499 #define B3_MA_RC_TEST 0x01ca /* 16 bit MAC Arbiter Recovery Test Reg */
500 /* 0x01cc - 0x01cf: reserved */
502 /* Packet Arbiter Registers (GENESIS only) */
503 /* these are real timeouts */
504 #define B3_PA_TOINI_RX1 0x01d0 /* 16 bit Timeout Init Val Rx Path MAC 1 */
505 /* 0x01d2 - 0x01d3: reserved */
506 #define B3_PA_TOINI_RX2 0x01d4 /* 16 bit Timeout Init Val Rx Path MAC 2 */
507 /* 0x01d6 - 0x01d7: reserved */
508 #define B3_PA_TOINI_TX1 0x01d8 /* 16 bit Timeout Init Val Tx Path MAC 1 */
509 /* 0x01da - 0x01db: reserved */
510 #define B3_PA_TOINI_TX2 0x01dc /* 16 bit Timeout Init Val Tx Path MAC 2 */
511 /* 0x01de - 0x01df: reserved */
512 #define B3_PA_TOVAL_RX1 0x01e0 /* 16 bit Timeout Val Rx Path MAC 1 */
513 /* 0x01e2 - 0x01e3: reserved */
514 #define B3_PA_TOVAL_RX2 0x01e4 /* 16 bit Timeout Val Rx Path MAC 2 */
515 /* 0x01e6 - 0x01e7: reserved */
516 #define B3_PA_TOVAL_TX1 0x01e8 /* 16 bit Timeout Val Tx Path MAC 1 */
517 /* 0x01ea - 0x01eb: reserved */
518 #define B3_PA_TOVAL_TX2 0x01ec /* 16 bit Timeout Val Tx Path MAC 2 */
519 /* 0x01ee - 0x01ef: reserved */
520 #define B3_PA_CTRL 0x01f0 /* 16 bit Packet Arbiter Ctrl Register */
521 #define B3_PA_TEST 0x01f2 /* 16 bit Packet Arbiter Test Register */
522 /* 0x01f4 - 0x01ff: reserved */
527 /* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
528 #define TXA_ITI_INI 0x0200 /* 32 bit Tx Arb Interval Timer Init Val*/
529 #define TXA_ITI_VAL 0x0204 /* 32 bit Tx Arb Interval Timer Value */
530 #define TXA_LIM_INI 0x0208 /* 32 bit Tx Arb Limit Counter Init Val */
531 #define TXA_LIM_VAL 0x020c /* 32 bit Tx Arb Limit Counter Value */
532 #define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */
533 #define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */
534 #define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */
535 /* 0x0213 - 0x027f: reserved */
536 /* 0x0280 - 0x0292: MAC 2 */
537 /* 0x0213 - 0x027f: reserved */
542 /* External registers (GENESIS only) */
543 #define B6_EXT_REG 0x0300
548 /* This is a copy of the Configuration register file (lower half) */
549 #define B7_CFG_SPC 0x0380
554 /* Receive and Transmit Queue Registers, use Q_ADDR() to access */
555 #define B8_Q_REGS 0x0400
557 /* Queue Register Offsets, use Q_ADDR() to access */
558 #define Q_D 0x00 /* 8*32 bit Current Descriptor */
559 #define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */
560 #define Q_DA_H 0x24 /* 32 bit Current Descriptor Address High dWord */
561 #define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */
562 #define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */
563 #define Q_BC 0x30 /* 32 bit Current Byte Counter */
564 #define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */
565 #define Q_F 0x38 /* 32 bit Flag Register */
566 #define Q_T1 0x3c /* 32 bit Test Register 1 */
567 #define Q_T1_TR 0x3c /* 8 bit Test Register 1 Transfer SM */
568 #define Q_T1_WR 0x3d /* 8 bit Test Register 1 Write Descriptor SM */
569 #define Q_T1_RD 0x3e /* 8 bit Test Register 1 Read Descriptor SM */
570 #define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */
571 #define Q_T2 0x40 /* 32 bit Test Register 2 */
572 #define Q_T3 0x44 /* 32 bit Test Register 3 */
573 /* 0x48 - 0x7f: reserved */
578 /* RAM Buffer Registers */
579 #define B16_RAM_REGS 0x0800
581 /* RAM Buffer Register Offsets, use RB_ADDR() to access */
582 #define RB_START 0x00 /* 32 bit RAM Buffer Start Address */
583 #define RB_END 0x04 /* 32 bit RAM Buffer End Address */
584 #define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */
585 #define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */
586 #define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Pack */
587 #define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Pack */
588 #define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */
589 #define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */
590 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
591 #define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */
592 #define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */
593 #define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */
594 #define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */
595 #define RB_TST2 0x2A /* 8 bit RAM Buffer Test Register 2 */
596 /* 0x2c - 0x7f: reserved */
602 * Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only)
603 * use MR_ADDR() to access
605 #define RX_MFF_EA 0x0c00 /* 32 bit Receive MAC FIFO End Address */
606 #define RX_MFF_WP 0x0c04 /* 32 bit Receive MAC FIFO Write Pointer */
607 /* 0x0c08 - 0x0c0b: reserved */
608 #define RX_MFF_RP 0x0c0c /* 32 bit Receive MAC FIFO Read Pointer */
609 #define RX_MFF_PC 0x0c10 /* 32 bit Receive MAC FIFO Packet Cnt */
610 #define RX_MFF_LEV 0x0c14 /* 32 bit Receive MAC FIFO Level */
611 #define RX_MFF_CTRL1 0x0c18 /* 16 bit Receive MAC FIFO Control Reg 1*/
612 #define RX_MFF_STAT_TO 0x0c1a /* 8 bit Receive MAC Status Timeout */
613 #define RX_MFF_TIST_TO 0x0c1b /* 8 bit Receive MAC Time Stamp Timeout */
614 #define RX_MFF_CTRL2 0x0c1c /* 8 bit Receive MAC FIFO Control Reg 2*/
615 #define RX_MFF_TST1 0x0c1d /* 8 bit Receive MAC FIFO Test Reg 1 */
616 #define RX_MFF_TST2 0x0c1e /* 8 bit Receive MAC FIFO Test Reg 2 */
617 /* 0x0c1f: reserved */
618 #define RX_LED_INI 0x0c20 /* 32 bit Receive LED Cnt Init Value */
619 #define RX_LED_VAL 0x0c24 /* 32 bit Receive LED Cnt Current Value */
620 #define RX_LED_CTRL 0x0c28 /* 8 bit Receive LED Cnt Control Reg */
621 #define RX_LED_TST 0x0c29 /* 8 bit Receive LED Cnt Test Register */
622 /* 0x0c2a - 0x0c2f: reserved */
623 #define LNK_SYNC_INI 0x0c30 /* 32 bit Link Sync Cnt Init Value */
624 #define LNK_SYNC_VAL 0x0c34 /* 32 bit Link Sync Cnt Current Value */
625 #define LNK_SYNC_CTRL 0x0c38 /* 8 bit Link Sync Cnt Control Register */
626 #define LNK_SYNC_TST 0x0c39 /* 8 bit Link Sync Cnt Test Register */
627 /* 0x0c3a - 0x0c3b: reserved */
628 #define LNK_LED_REG 0x0c3c /* 8 bit Link LED Register */
629 /* 0x0c3d - 0x0c3f: reserved */
631 /* Receive GMAC FIFO (YUKON only), use MR_ADDR() to access */
632 #define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */
633 #define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */
634 #define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */
635 #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */
636 #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */
637 /* 0x0c54 - 0x0c5f: reserved */
638 #define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */
639 /* 0x0c64 - 0x0c67: reserved */
640 #define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */
641 /* 0x0c6c - 0x0c6f: reserved */
642 #define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */
643 /* 0x0c74 - 0x0c77: reserved */
644 #define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */
645 /* 0x0c7c - 0x0c7f: reserved */
650 /* 0x0c80 - 0x0cbf: MAC 2 */
651 /* 0x0cc0 - 0x0cff: reserved */
657 * Transmit MAC FIFO and Transmit LED Registers (GENESIS only),
658 * use MR_ADDR() to access
660 #define TX_MFF_EA 0x0d00 /* 32 bit Transmit MAC FIFO End Address */
661 #define TX_MFF_WP 0x0d04 /* 32 bit Transmit MAC FIFO WR Pointer */
662 #define TX_MFF_WSP 0x0d08 /* 32 bit Transmit MAC FIFO WR Shadow Ptr */
663 #define TX_MFF_RP 0x0d0c /* 32 bit Transmit MAC FIFO RD Pointer */
664 #define TX_MFF_PC 0x0d10 /* 32 bit Transmit MAC FIFO Packet Cnt */
665 #define TX_MFF_LEV 0x0d14 /* 32 bit Transmit MAC FIFO Level */
666 #define TX_MFF_CTRL1 0x0d18 /* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
667 #define TX_MFF_WAF 0x0d1a /* 8 bit Transmit MAC Wait after flush */
668 /* 0x0c1b: reserved */
669 #define TX_MFF_CTRL2 0x0d1c /* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
670 #define TX_MFF_TST1 0x0d1d /* 8 bit Transmit MAC FIFO Test Reg 1 */
671 #define TX_MFF_TST2 0x0d1e /* 8 bit Transmit MAC FIFO Test Reg 2 */
672 /* 0x0d1f: reserved */
673 #define TX_LED_INI 0x0d20 /* 32 bit Transmit LED Cnt Init Value */
674 #define TX_LED_VAL 0x0d24 /* 32 bit Transmit LED Cnt Current Val */
675 #define TX_LED_CTRL 0x0d28 /* 8 bit Transmit LED Cnt Control Reg */
676 #define TX_LED_TST 0x0d29 /* 8 bit Transmit LED Cnt Test Reg */
677 /* 0x0d2a - 0x0d3f: reserved */
679 /* Transmit GMAC FIFO (YUKON only), use MR_ADDR() to access */
680 #define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */
681 #define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
682 #define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */
683 /* 0x0d4c - 0x0d5f: reserved */
684 #define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */
685 #define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
686 #define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */
687 /* 0x0d6c - 0x0d6f: reserved */
688 #define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */
689 #define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */
690 #define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */
691 /* 0x0d7c - 0x0d7f: reserved */
696 /* 0x0d80 - 0x0dbf: MAC 2 */
697 /* 0x0daa - 0x0dff: reserved */
702 /* Descriptor Poll Timer Registers */
703 #define B28_DPT_INI 0x0e00 /* 24 bit Descriptor Poll Timer Init Val */
704 #define B28_DPT_VAL 0x0e04 /* 24 bit Descriptor Poll Timer Curr Val */
705 #define B28_DPT_CTRL 0x0e08 /* 8 bit Descriptor Poll Timer Ctrl Reg */
706 /* 0x0e09: reserved */
707 #define B28_DPT_TST 0x0e0a /* 8 bit Descriptor Poll Timer Test Reg */
708 /* 0x0e0b: reserved */
710 /* Time Stamp Timer Registers (YUKON only) */
711 /* 0x0e10: reserved */
712 #define GMAC_TI_ST_VAL 0x0e14 /* 32 bit Time Stamp Timer Curr Val */
713 #define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */
714 /* 0x0e19: reserved */
715 #define GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */
716 /* 0x0e1b - 0x0e7f: reserved */
721 /* 0x0e80 - 0x0efc: reserved */
726 /* GMAC and GPHY Control Registers (YUKON only) */
727 #define GMAC_CTRL 0x0f00 /* 32 bit GMAC Control Reg */
728 #define GPHY_CTRL 0x0f04 /* 32 bit GPHY Control Reg */
729 #define GMAC_IRQ_SRC 0x0f08 /* 8 bit GMAC Interrupt Source Reg */
730 /* 0x0f09 - 0x0f0b: reserved */
731 #define GMAC_IRQ_MSK 0x0f0c /* 8 bit GMAC Interrupt Mask Reg */
732 /* 0x0f0d - 0x0f0f: reserved */
733 #define GMAC_LINK_CTRL 0x0f10 /* 16 bit Link Control Reg */
734 /* 0x0f14 - 0x0f1f: reserved */
736 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
738 #define WOL_REG_OFFS 0x20 /* HW-Bug: Address is + 0x20 against spec. */
740 #define WOL_CTRL_STAT 0x0f20 /* 16 bit WOL Control/Status Reg */
741 #define WOL_MATCH_CTL 0x0f22 /* 8 bit WOL Match Control Reg */
742 #define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */
743 #define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */
744 #define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */
745 #define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Ptr */
747 /* use this macro to access above registers */
748 #define WOL_REG(Reg) ((Reg) + (pAC->GIni.GIWolOffs))
751 /* WOL Pattern Length Registers (YUKON only) */
753 #define WOL_PATT_LEN_LO 0x0f30 /* 32 bit WOL Pattern Length 3..0 */
754 #define WOL_PATT_LEN_HI 0x0f34 /* 24 bit WOL Pattern Length 6..4 */
756 /* WOL Pattern Counter Registers (YUKON only) */
758 #define WOL_PATT_CNT_0 0x0f38 /* 32 bit WOL Pattern Counter 3..0 */
759 #define WOL_PATT_CNT_4 0x0f3c /* 24 bit WOL Pattern Counter 6..4 */
760 /* 0x0f40 - 0x0f7f: reserved */
765 /* 0x0f80 - 0x0fff: reserved */
770 #define WOL_PATT_RAM_1 0x1000 /* WOL Pattern RAM Link 1 */
775 /* 0x1100 - 0x1fff: reserved */
780 #define BASE_XMAC_1 0x2000 /* XMAC 1 registers */
786 #define BASE_GMAC_1 0x2800 /* GMAC 1 registers */
791 #define BASE_XMAC_2 0x3000 /* XMAC 2 registers */
796 #define BASE_GMAC_2 0x3800 /* GMAC 2 registers */
799 * Control Register Bit Definitions:
801 /* B0_RAP 8 bit Register Address Port */
802 /* Bit 7: reserved */
803 #define RAP_RAP 0x3f /* Bit 6..0: 0 = block 0,..,6f = block 6f */
805 /* B0_CTST 16 bit Control/Status register */
806 /* Bit 15..14: reserved */
807 #define CS_CLK_RUN_HOT BIT_13S /* CLK_RUN hot m. (YUKON-Lite only) */
808 #define CS_CLK_RUN_RST BIT_12S /* CLK_RUN reset (YUKON-Lite only) */
809 #define CS_CLK_RUN_ENA BIT_11S /* CLK_RUN enable (YUKON-Lite only) */
810 #define CS_VAUX_AVAIL BIT_10S /* VAUX available (YUKON only) */
811 #define CS_BUS_CLOCK BIT_9S /* Bus Clock 0/1 = 33/66 MHz */
812 #define CS_BUS_SLOT_SZ BIT_8S /* Slot Size 0/1 = 32/64 bit slot */
813 #define CS_ST_SW_IRQ BIT_7S /* Set IRQ SW Request */
814 #define CS_CL_SW_IRQ BIT_6S /* Clear IRQ SW Request */
815 #define CS_STOP_DONE BIT_5S /* Stop Master is finished */
816 #define CS_STOP_MAST BIT_4S /* Command Bit to stop the master */
817 #define CS_MRST_CLR BIT_3S /* Clear Master reset */
818 #define CS_MRST_SET BIT_2S /* Set Master reset */
819 #define CS_RST_CLR BIT_1S /* Clear Software reset */
820 #define CS_RST_SET BIT_0S /* Set Software reset */
822 /* B0_LED 8 Bit LED register */
823 /* Bit 7.. 2: reserved */
824 #define LED_STAT_ON BIT_1S /* Status LED on */
825 #define LED_STAT_OFF BIT_0S /* Status LED off */
827 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
828 #define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */
829 #define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */
830 #define PC_VCC_ENA BIT_5 /* Switch VCC Enable */
831 #define PC_VCC_DIS BIT_4 /* Switch VCC Disable */
832 #define PC_VAUX_ON BIT_3 /* Switch VAUX On */
833 #define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */
834 #define PC_VCC_ON BIT_1 /* Switch VCC On */
835 #define PC_VCC_OFF BIT_0 /* Switch VCC Off */
837 /* B0_ISRC 32 bit Interrupt Source Register */
838 /* B0_IMSK 32 bit Interrupt Mask Register */
839 /* B0_SP_ISRC 32 bit Special Interrupt Source Reg */
840 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
841 #define IS_ALL_MSK 0xbfffffffUL /* All Interrupt bits */
842 #define IS_HW_ERR BIT_31 /* Interrupt HW Error */
843 /* Bit 30: reserved */
844 #define IS_PA_TO_RX1 BIT_29 /* Packet Arb Timeout Rx1 */
845 #define IS_PA_TO_RX2 BIT_28 /* Packet Arb Timeout Rx2 */
846 #define IS_PA_TO_TX1 BIT_27 /* Packet Arb Timeout Tx1 */
847 #define IS_PA_TO_TX2 BIT_26 /* Packet Arb Timeout Tx2 */
848 #define IS_I2C_READY BIT_25 /* IRQ on end of I2C Tx */
849 #define IS_IRQ_SW BIT_24 /* SW forced IRQ */
850 #define IS_EXT_REG BIT_23 /* IRQ from LM80 or PHY (GENESIS only) */
851 /* IRQ from PHY (YUKON only) */
852 #define IS_TIMINT BIT_22 /* IRQ from Timer */
853 #define IS_MAC1 BIT_21 /* IRQ from MAC 1 */
854 #define IS_LNK_SYNC_M1 BIT_20 /* Link Sync Cnt wrap MAC 1 */
855 #define IS_MAC2 BIT_19 /* IRQ from MAC 2 */
856 #define IS_LNK_SYNC_M2 BIT_18 /* Link Sync Cnt wrap MAC 2 */
857 /* Receive Queue 1 */
858 #define IS_R1_B BIT_17 /* Q_R1 End of Buffer */
859 #define IS_R1_F BIT_16 /* Q_R1 End of Frame */
860 #define IS_R1_C BIT_15 /* Q_R1 Encoding Error */
861 /* Receive Queue 2 */
862 #define IS_R2_B BIT_14 /* Q_R2 End of Buffer */
863 #define IS_R2_F BIT_13 /* Q_R2 End of Frame */
864 #define IS_R2_C BIT_12 /* Q_R2 Encoding Error */
865 /* Synchronous Transmit Queue 1 */
866 #define IS_XS1_B BIT_11 /* Q_XS1 End of Buffer */
867 #define IS_XS1_F BIT_10 /* Q_XS1 End of Frame */
868 #define IS_XS1_C BIT_9 /* Q_XS1 Encoding Error */
869 /* Asynchronous Transmit Queue 1 */
870 #define IS_XA1_B BIT_8 /* Q_XA1 End of Buffer */
871 #define IS_XA1_F BIT_7 /* Q_XA1 End of Frame */
872 #define IS_XA1_C BIT_6 /* Q_XA1 Encoding Error */
873 /* Synchronous Transmit Queue 2 */
874 #define IS_XS2_B BIT_5 /* Q_XS2 End of Buffer */
875 #define IS_XS2_F BIT_4 /* Q_XS2 End of Frame */
876 #define IS_XS2_C BIT_3 /* Q_XS2 Encoding Error */
877 /* Asynchronous Transmit Queue 2 */
878 #define IS_XA2_B BIT_2 /* Q_XA2 End of Buffer */
879 #define IS_XA2_F BIT_1 /* Q_XA2 End of Frame */
880 #define IS_XA2_C BIT_0 /* Q_XA2 Encoding Error */
883 /* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */
884 /* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */
885 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
886 #define IS_ERR_MSK 0x00000fffL /* All Error bits */
887 /* Bit 31..14: reserved */
888 #define IS_IRQ_TIST_OV BIT_13 /* Time Stamp Timer Overflow (YUKON only) */
889 #define IS_IRQ_SENSOR BIT_12 /* IRQ from Sensor (YUKON only) */
890 #define IS_IRQ_MST_ERR BIT_11 /* IRQ master error detected */
891 #define IS_IRQ_STAT BIT_10 /* IRQ status exception */
892 #define IS_NO_STAT_M1 BIT_9 /* No Rx Status from MAC 1 */
893 #define IS_NO_STAT_M2 BIT_8 /* No Rx Status from MAC 2 */
894 #define IS_NO_TIST_M1 BIT_7 /* No Time Stamp from MAC 1 */
895 #define IS_NO_TIST_M2 BIT_6 /* No Time Stamp from MAC 2 */
896 #define IS_RAM_RD_PAR BIT_5 /* RAM Read Parity Error */
897 #define IS_RAM_WR_PAR BIT_4 /* RAM Write Parity Error */
898 #define IS_M1_PAR_ERR BIT_3 /* MAC 1 Parity Error */
899 #define IS_M2_PAR_ERR BIT_2 /* MAC 2 Parity Error */
900 #define IS_R1_PAR_ERR BIT_1 /* Queue R1 Parity Error */
901 #define IS_R2_PAR_ERR BIT_0 /* Queue R2 Parity Error */
903 /* B2_CONN_TYP 8 bit Connector type */
904 /* B2_PMD_TYP 8 bit PMD type */
905 /* Values of connector and PMD type comply to SysKonnect internal std */
907 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
908 #define CFG_CHIP_R_MSK (0xf<<4) /* Bit 7.. 4: Chip Revision */
909 /* Bit 3.. 2: reserved */
910 #define CFG_DIS_M2_CLK BIT_1S /* Disable Clock for 2nd MAC */
911 #define CFG_SNG_MAC BIT_0S /* MAC Config: 0=2 MACs / 1=1 MAC*/
913 /* B2_CHIP_ID 8 bit Chip Identification Number */
914 #define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */
915 #define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */
916 #define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */
917 #define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */
919 #define CHIP_REV_YU_LITE_A1 3 /* Chip Rev. for YUKON-Lite A1,A2 */
920 #define CHIP_REV_YU_LITE_A3 7 /* Chip Rev. for YUKON-Lite A3 */
922 /* B2_FAR 32 bit Flash-Prom Addr Reg/Cnt */
923 #define FAR_ADDR 0x1ffffL /* Bit 16.. 0: FPROM Address mask */
925 /* B2_LD_CTRL 8 bit EPROM loader control register */
926 /* Bits are currently reserved */
928 /* B2_LD_TEST 8 bit EPROM loader test register */
929 /* Bit 7.. 4: reserved */
930 #define LD_T_ON BIT_3S /* Loader Test mode on */
931 #define LD_T_OFF BIT_2S /* Loader Test mode off */
932 #define LD_T_STEP BIT_1S /* Decrement FPROM addr. Counter */
933 #define LD_START BIT_0S /* Start loading FPROM */
938 /* B2_TI_CTRL 8 bit Timer control */
939 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
940 /* Bit 7.. 3: reserved */
941 #define TIM_START BIT_2S /* Start Timer */
942 #define TIM_STOP BIT_1S /* Stop Timer */
943 #define TIM_CLR_IRQ BIT_0S /* Clear Timer IRQ (!IRQM) */
945 /* B2_TI_TEST 8 Bit Timer Test */
946 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
947 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
948 /* Bit 7.. 3: reserved */
949 #define TIM_T_ON BIT_2S /* Test mode on */
950 #define TIM_T_OFF BIT_1S /* Test mode off */
951 #define TIM_T_STEP BIT_0S /* Test step */
953 /* B28_DPT_INI 32 bit Descriptor Poll Timer Init Val */
954 /* B28_DPT_VAL 32 bit Descriptor Poll Timer Curr Val */
955 /* Bit 31..24: reserved */
956 #define DPT_MSK 0x00ffffffL /* Bit 23.. 0: Desc Poll Timer Bits */
958 /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
959 /* Bit 7.. 2: reserved */
960 #define DPT_START BIT_1S /* Start Descriptor Poll Timer */
961 #define DPT_STOP BIT_0S /* Stop Descriptor Poll Timer */
963 /* B2_E_3 8 bit lower 4 bits used for HW self test result */
964 #define B2_E3_RES_MASK 0x0f
966 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
967 #define TST_FRC_DPERR_MR BIT_7S /* force DATAPERR on MST RD */
968 #define TST_FRC_DPERR_MW BIT_6S /* force DATAPERR on MST WR */
969 #define TST_FRC_DPERR_TR BIT_5S /* force DATAPERR on TRG RD */
970 #define TST_FRC_DPERR_TW BIT_4S /* force DATAPERR on TRG WR */
971 #define TST_FRC_APERR_M BIT_3S /* force ADDRPERR on MST */
972 #define TST_FRC_APERR_T BIT_2S /* force ADDRPERR on TRG */
973 #define TST_CFG_WRITE_ON BIT_1S /* Enable Config Reg WR */
974 #define TST_CFG_WRITE_OFF BIT_0S /* Disable Config Reg WR */
976 /* B2_TST_CTRL2 8 bit Test Control Register 2 */
977 /* Bit 7.. 4: reserved */
978 /* force the following error on the next master read/write */
979 #define TST_FRC_DPERR_MR64 BIT_3S /* DataPERR RD 64 */
980 #define TST_FRC_DPERR_MW64 BIT_2S /* DataPERR WR 64 */
981 #define TST_FRC_APERR_1M64 BIT_1S /* AddrPERR on 1. phase */
982 #define TST_FRC_APERR_2M64 BIT_0S /* AddrPERR on 2. phase */
984 /* B2_GP_IO 32 bit General Purpose I/O Register */
985 /* Bit 31..26: reserved */
986 #define GP_DIR_9 BIT_25 /* IO_9 direct, 0=In/1=Out */
987 #define GP_DIR_8 BIT_24 /* IO_8 direct, 0=In/1=Out */
988 #define GP_DIR_7 BIT_23 /* IO_7 direct, 0=In/1=Out */
989 #define GP_DIR_6 BIT_22 /* IO_6 direct, 0=In/1=Out */
990 #define GP_DIR_5 BIT_21 /* IO_5 direct, 0=In/1=Out */
991 #define GP_DIR_4 BIT_20 /* IO_4 direct, 0=In/1=Out */
992 #define GP_DIR_3 BIT_19 /* IO_3 direct, 0=In/1=Out */
993 #define GP_DIR_2 BIT_18 /* IO_2 direct, 0=In/1=Out */
994 #define GP_DIR_1 BIT_17 /* IO_1 direct, 0=In/1=Out */
995 #define GP_DIR_0 BIT_16 /* IO_0 direct, 0=In/1=Out */
996 /* Bit 15..10: reserved */
997 #define GP_IO_9 BIT_9 /* IO_9 pin */
998 #define GP_IO_8 BIT_8 /* IO_8 pin */
999 #define GP_IO_7 BIT_7 /* IO_7 pin */
1000 #define GP_IO_6 BIT_6 /* IO_6 pin */
1001 #define GP_IO_5 BIT_5 /* IO_5 pin */
1002 #define GP_IO_4 BIT_4 /* IO_4 pin */
1003 #define GP_IO_3 BIT_3 /* IO_3 pin */
1004 #define GP_IO_2 BIT_2 /* IO_2 pin */
1005 #define GP_IO_1 BIT_1 /* IO_1 pin */
1006 #define GP_IO_0 BIT_0 /* IO_0 pin */
1008 /* B2_I2C_CTRL 32 bit I2C HW Control Register */
1009 #define I2C_FLAG BIT_31 /* Start read/write if WR */
1010 #define I2C_ADDR (0x7fffL<<16) /* Bit 30..16: Addr to be RD/WR */
1011 #define I2C_DEV_SEL (0x7fL<<9) /* Bit 15.. 9: I2C Device Select */
1012 /* Bit 8.. 5: reserved */
1013 #define I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */
1014 #define I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */
1015 #define I2C_025K_DEV (0<<1) /* 0: 256 Bytes or smal. */
1016 #define I2C_05K_DEV (1<<1) /* 1: 512 Bytes */
1017 #define I2C_1K_DEV (2<<1) /* 2: 1024 Bytes */
1018 #define I2C_2K_DEV (3<<1) /* 3: 2048 Bytes */
1019 #define I2C_4K_DEV (4<<1) /* 4: 4096 Bytes */
1020 #define I2C_8K_DEV (5<<1) /* 5: 8192 Bytes */
1021 #define I2C_16K_DEV (6<<1) /* 6: 16384 Bytes */
1022 #define I2C_32K_DEV (7<<1) /* 7: 32768 Bytes */
1023 #define I2C_STOP BIT_0 /* Interrupt I2C transfer */
1025 /* B2_I2C_IRQ 32 bit I2C HW IRQ Register */
1026 /* Bit 31.. 1 reserved */
1027 #define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */
1029 /* B2_I2C_SW 32 bit (8 bit access) I2C HW SW Port Register */
1030 /* Bit 7.. 3: reserved */
1031 #define I2C_DATA_DIR BIT_2S /* direction of I2C_DATA */
1032 #define I2C_DATA BIT_1S /* I2C Data Port */
1033 #define I2C_CLK BIT_0S /* I2C Clock Port */
1038 #define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address, (Volt and Temp)*/
1041 /* B2_BSC_CTRL 8 bit Blink Source Counter Control */
1042 /* Bit 7.. 2: reserved */
1043 #define BSC_START BIT_1S /* Start Blink Source Counter */
1044 #define BSC_STOP BIT_0S /* Stop Blink Source Counter */
1046 /* B2_BSC_STAT 8 bit Blink Source Counter Status */
1047 /* Bit 7.. 1: reserved */
1048 #define BSC_SRC BIT_0S /* Blink Source, 0=Off / 1=On */
1050 /* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
1051 #define BSC_T_ON BIT_2S /* Test mode on */
1052 #define BSC_T_OFF BIT_1S /* Test mode off */
1053 #define BSC_T_STEP BIT_0S /* Test step */
1056 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
1057 /* Bit 31..19: reserved */
1058 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
1060 /* RAM Interface Registers */
1061 /* B3_RI_CTRL 16 bit RAM Iface Control Register */
1062 /* Bit 15..10: reserved */
1063 #define RI_CLR_RD_PERR BIT_9S /* Clear IRQ RAM Read Parity Err */
1064 #define RI_CLR_WR_PERR BIT_8S /* Clear IRQ RAM Write Parity Err*/
1065 /* Bit 7.. 2: reserved */
1066 #define RI_RST_CLR BIT_1S /* Clear RAM Interface Reset */
1067 #define RI_RST_SET BIT_0S /* Set RAM Interface Reset */
1069 /* B3_RI_TEST 8 bit RAM Iface Test Register */
1070 /* Bit 15.. 4: reserved */
1071 #define RI_T_EV BIT_3S /* Timeout Event occured */
1072 #define RI_T_ON BIT_2S /* Timeout Timer Test On */
1073 #define RI_T_OFF BIT_1S /* Timeout Timer Test Off */
1074 #define RI_T_STEP BIT_0S /* Timeout Timer Step */
1076 /* MAC Arbiter Registers */
1077 /* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
1078 /* Bit 15.. 4: reserved */
1079 #define MA_FOE_ON BIT_3S /* XMAC Fast Output Enable ON */
1080 #define MA_FOE_OFF BIT_2S /* XMAC Fast Output Enable OFF */
1081 #define MA_RST_CLR BIT_1S /* Clear MAC Arbiter Reset */
1082 #define MA_RST_SET BIT_0S /* Set MAC Arbiter Reset */
1084 /* B3_MA_RC_CTRL 16 bit MAC Arbiter Recovery Ctrl Reg */
1085 /* Bit 15.. 8: reserved */
1086 #define MA_ENA_REC_TX2 BIT_7S /* Enable Recovery Timer TX2 */
1087 #define MA_DIS_REC_TX2 BIT_6S /* Disable Recovery Timer TX2 */
1088 #define MA_ENA_REC_TX1 BIT_5S /* Enable Recovery Timer TX1 */
1089 #define MA_DIS_REC_TX1 BIT_4S /* Disable Recovery Timer TX1 */
1090 #define MA_ENA_REC_RX2 BIT_3S /* Enable Recovery Timer RX2 */
1091 #define MA_DIS_REC_RX2 BIT_2S /* Disable Recovery Timer RX2 */
1092 #define MA_ENA_REC_RX1 BIT_1S /* Enable Recovery Timer RX1 */
1093 #define MA_DIS_REC_RX1 BIT_0S /* Disable Recovery Timer RX1 */
1095 /* Packet Arbiter Registers */
1096 /* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
1097 /* Bit 15..14: reserved */
1098 #define PA_CLR_TO_TX2 BIT_13S /* Clear IRQ Packet Timeout TX2 */
1099 #define PA_CLR_TO_TX1 BIT_12S /* Clear IRQ Packet Timeout TX1 */
1100 #define PA_CLR_TO_RX2 BIT_11S /* Clear IRQ Packet Timeout RX2 */
1101 #define PA_CLR_TO_RX1 BIT_10S /* Clear IRQ Packet Timeout RX1 */
1102 #define PA_ENA_TO_TX2 BIT_9S /* Enable Timeout Timer TX2 */
1103 #define PA_DIS_TO_TX2 BIT_8S /* Disable Timeout Timer TX2 */
1104 #define PA_ENA_TO_TX1 BIT_7S /* Enable Timeout Timer TX1 */
1105 #define PA_DIS_TO_TX1 BIT_6S /* Disable Timeout Timer TX1 */
1106 #define PA_ENA_TO_RX2 BIT_5S /* Enable Timeout Timer RX2 */
1107 #define PA_DIS_TO_RX2 BIT_4S /* Disable Timeout Timer RX2 */
1108 #define PA_ENA_TO_RX1 BIT_3S /* Enable Timeout Timer RX1 */
1109 #define PA_DIS_TO_RX1 BIT_2S /* Disable Timeout Timer RX1 */
1110 #define PA_RST_CLR BIT_1S /* Clear MAC Arbiter Reset */
1111 #define PA_RST_SET BIT_0S /* Set MAC Arbiter Reset */
1113 #define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
1114 PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
1116 /* Rx/Tx Path related Arbiter Test Registers */
1117 /* B3_MA_TO_TEST 16 bit MAC Arbiter Timeout Test Reg */
1118 /* B3_MA_RC_TEST 16 bit MAC Arbiter Recovery Test Reg */
1119 /* B3_PA_TEST 16 bit Packet Arbiter Test Register */
1120 /* Bit 15, 11, 7, and 3 are reserved in B3_PA_TEST */
1121 #define TX2_T_EV BIT_15S /* TX2 Timeout/Recv Event occured */
1122 #define TX2_T_ON BIT_14S /* TX2 Timeout/Recv Timer Test On */
1123 #define TX2_T_OFF BIT_13S /* TX2 Timeout/Recv Timer Tst Off */
1124 #define TX2_T_STEP BIT_12S /* TX2 Timeout/Recv Timer Step */
1125 #define TX1_T_EV BIT_11S /* TX1 Timeout/Recv Event occured */
1126 #define TX1_T_ON BIT_10S /* TX1 Timeout/Recv Timer Test On */
1127 #define TX1_T_OFF BIT_9S /* TX1 Timeout/Recv Timer Tst Off */
1128 #define TX1_T_STEP BIT_8S /* TX1 Timeout/Recv Timer Step */
1129 #define RX2_T_EV BIT_7S /* RX2 Timeout/Recv Event occured */
1130 #define RX2_T_ON BIT_6S /* RX2 Timeout/Recv Timer Test On */
1131 #define RX2_T_OFF BIT_5S /* RX2 Timeout/Recv Timer Tst Off */
1132 #define RX2_T_STEP BIT_4S /* RX2 Timeout/Recv Timer Step */
1133 #define RX1_T_EV BIT_3S /* RX1 Timeout/Recv Event occured */
1134 #define RX1_T_ON BIT_2S /* RX1 Timeout/Recv Timer Test On */
1135 #define RX1_T_OFF BIT_1S /* RX1 Timeout/Recv Timer Tst Off */
1136 #define RX1_T_STEP BIT_0S /* RX1 Timeout/Recv Timer Step */
1139 /* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
1140 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
1141 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
1142 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
1143 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
1144 /* Bit 31..24: reserved */
1145 #define TXA_MAX_VAL 0x00ffffffUL/* Bit 23.. 0: Max TXA Timer/Cnt Val */
1147 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
1148 #define TXA_ENA_FSYNC BIT_7S /* Enable force of sync Tx queue */
1149 #define TXA_DIS_FSYNC BIT_6S /* Disable force of sync Tx queue */
1150 #define TXA_ENA_ALLOC BIT_5S /* Enable alloc of free bandwidth */
1151 #define TXA_DIS_ALLOC BIT_4S /* Disable alloc of free bandwidth */
1152 #define TXA_START_RC BIT_3S /* Start sync Rate Control */
1153 #define TXA_STOP_RC BIT_2S /* Stop sync Rate Control */
1154 #define TXA_ENA_ARB BIT_1S /* Enable Tx Arbiter */
1155 #define TXA_DIS_ARB BIT_0S /* Disable Tx Arbiter */
1157 /* TXA_TEST 8 bit Tx Arbiter Test Register */
1158 /* Bit 7.. 6: reserved */
1159 #define TXA_INT_T_ON BIT_5S /* Tx Arb Interval Timer Test On */
1160 #define TXA_INT_T_OFF BIT_4S /* Tx Arb Interval Timer Test Off */
1161 #define TXA_INT_T_STEP BIT_3S /* Tx Arb Interval Timer Step */
1162 #define TXA_LIM_T_ON BIT_2S /* Tx Arb Limit Timer Test On */
1163 #define TXA_LIM_T_OFF BIT_1S /* Tx Arb Limit Timer Test Off */
1164 #define TXA_LIM_T_STEP BIT_0S /* Tx Arb Limit Timer Step */
1166 /* TXA_STAT 8 bit Tx Arbiter Status Register */
1167 /* Bit 7.. 1: reserved */
1168 #define TXA_PRIO_XS BIT_0S /* sync queue has prio to send */
1170 /* Q_BC 32 bit Current Byte Counter */
1171 /* Bit 31..16: reserved */
1172 #define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */
1174 /* BMU Control Status Registers */
1175 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
1176 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
1177 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
1178 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
1179 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
1180 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
1181 /* Q_CSR 32 bit BMU Control/Status Register */
1182 /* Bit 31..25: reserved */
1183 #define CSR_SV_IDLE BIT_24 /* BMU SM Idle */
1184 /* Bit 23..22: reserved */
1185 #define CSR_DESC_CLR BIT_21 /* Clear Reset for Descr */
1186 #define CSR_DESC_SET BIT_20 /* Set Reset for Descr */
1187 #define CSR_FIFO_CLR BIT_19 /* Clear Reset for FIFO */
1188 #define CSR_FIFO_SET BIT_18 /* Set Reset for FIFO */
1189 #define CSR_HPI_RUN BIT_17 /* Release HPI SM */
1190 #define CSR_HPI_RST BIT_16 /* Reset HPI SM to Idle */
1191 #define CSR_SV_RUN BIT_15 /* Release Supervisor SM */
1192 #define CSR_SV_RST BIT_14 /* Reset Supervisor SM */
1193 #define CSR_DREAD_RUN BIT_13 /* Release Descr Read SM */
1194 #define CSR_DREAD_RST BIT_12 /* Reset Descr Read SM */
1195 #define CSR_DWRITE_RUN BIT_11 /* Release Descr Write SM */
1196 #define CSR_DWRITE_RST BIT_10 /* Reset Descr Write SM */
1197 #define CSR_TRANS_RUN BIT_9 /* Release Transfer SM */
1198 #define CSR_TRANS_RST BIT_8 /* Reset Transfer SM */
1199 #define CSR_ENA_POL BIT_7 /* Enable Descr Polling */
1200 #define CSR_DIS_POL BIT_6 /* Disable Descr Polling */
1201 #define CSR_STOP BIT_5 /* Stop Rx/Tx Queue */
1202 #define CSR_START BIT_4 /* Start Rx/Tx Queue */
1203 #define CSR_IRQ_CL_P BIT_3 /* (Rx) Clear Parity IRQ */
1204 #define CSR_IRQ_CL_B BIT_2 /* Clear EOB IRQ */
1205 #define CSR_IRQ_CL_F BIT_1 /* Clear EOF IRQ */
1206 #define CSR_IRQ_CL_C BIT_0 /* Clear ERR IRQ */
1208 #define CSR_SET_RESET (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
1209 CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
1211 #define CSR_CLR_RESET (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
1212 CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
1215 /* Q_F 32 bit Flag Register */
1216 /* Bit 31..28: reserved */
1217 #define F_ALM_FULL BIT_27 /* Rx FIFO: almost full */
1218 #define F_EMPTY BIT_27 /* Tx FIFO: empty flag */
1219 #define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */
1220 #define F_WM_REACHED BIT_25 /* Watermark reached */
1222 #define F_FIFO_LEVEL (0x1fL<<16) /* Bit 23..16: # of Qwords in FIFO */
1223 /* Bit 15..11: reserved */
1224 #define F_WATER_MARK 0x0007ffL /* Bit 10.. 0: Watermark */
1226 /* Q_T1 32 bit Test Register 1 */
1227 /* Holds four State Machine control Bytes */
1228 #define SM_CTRL_SV_MSK (0xffL<<24) /* Bit 31..24: Control Supervisor SM */
1229 #define SM_CTRL_RD_MSK (0xffL<<16) /* Bit 23..16: Control Read Desc SM */
1230 #define SM_CTRL_WR_MSK (0xffL<<8) /* Bit 15.. 8: Control Write Desc SM */
1231 #define SM_CTRL_TR_MSK 0xffL /* Bit 7.. 0: Control Transfer SM */
1233 /* Q_T1_TR 8 bit Test Register 1 Transfer SM */
1234 /* Q_T1_WR 8 bit Test Register 1 Write Descriptor SM */
1235 /* Q_T1_RD 8 bit Test Register 1 Read Descriptor SM */
1236 /* Q_T1_SV 8 bit Test Register 1 Supervisor SM */
1238 /* The control status byte of each machine looks like ... */
1239 #define SM_STATE 0xf0 /* Bit 7.. 4: State which shall be loaded */
1240 #define SM_LOAD BIT_3S /* Load the SM with SM_STATE */
1241 #define SM_TEST_ON BIT_2S /* Switch on SM Test Mode */
1242 #define SM_TEST_OFF BIT_1S /* Go off the Test Mode */
1243 #define SM_STEP BIT_0S /* Step the State Machine */
1244 /* The encoding of the states is not supported by the Diagnostics Tool */
1246 /* Q_T2 32 bit Test Register 2 */
1247 /* Bit 31.. 8: reserved */
1248 #define T2_AC_T_ON BIT_7 /* Address Counter Test Mode on */
1249 #define T2_AC_T_OFF BIT_6 /* Address Counter Test Mode off */
1250 #define T2_BC_T_ON BIT_5 /* Byte Counter Test Mode on */
1251 #define T2_BC_T_OFF BIT_4 /* Byte Counter Test Mode off */
1252 #define T2_STEP04 BIT_3 /* Inc AC/Dec BC by 4 */
1253 #define T2_STEP03 BIT_2 /* Inc AC/Dec BC by 3 */
1254 #define T2_STEP02 BIT_1 /* Inc AC/Dec BC by 2 */
1255 #define T2_STEP01 BIT_0 /* Inc AC/Dec BC by 1 */
1257 /* Q_T3 32 bit Test Register 3 */
1258 /* Bit 31.. 7: reserved */
1259 #define T3_MUX_MSK (7<<4) /* Bit 6.. 4: Mux Position */
1260 /* Bit 3: reserved */
1261 #define T3_VRAM_MSK 7 /* Bit 2.. 0: Virtual RAM Buffer Address */
1263 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
1264 /* RB_START 32 bit RAM Buffer Start Address */
1265 /* RB_END 32 bit RAM Buffer End Address */
1266 /* RB_WP 32 bit RAM Buffer Write Pointer */
1267 /* RB_RP 32 bit RAM Buffer Read Pointer */
1268 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
1269 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
1270 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
1271 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
1272 /* RB_PC 32 bit RAM Buffer Packet Counter */
1273 /* RB_LEV 32 bit RAM Buffer Level Register */
1274 /* Bit 31..19: reserved */
1275 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
1277 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
1278 /* Bit 7.. 4: reserved */
1279 #define RB_PC_DEC BIT_3S /* Packet Counter Decrem */
1280 #define RB_PC_T_ON BIT_2S /* Packet Counter Test On */
1281 #define RB_PC_T_OFF BIT_1S /* Packet Counter Tst Off */
1282 #define RB_PC_INC BIT_0S /* Packet Counter Increm */
1284 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
1285 /* Bit 7: reserved */
1286 #define RB_WP_T_ON BIT_6S /* Write Pointer Test On */
1287 #define RB_WP_T_OFF BIT_5S /* Write Pointer Test Off */
1288 #define RB_WP_INC BIT_4S /* Write Pointer Increm */
1289 /* Bit 3: reserved */
1290 #define RB_RP_T_ON BIT_2S /* Read Pointer Test On */
1291 #define RB_RP_T_OFF BIT_1S /* Read Pointer Test Off */
1292 #define RB_RP_DEC BIT_0S /* Read Pointer Decrement */
1294 /* RB_CTRL 8 bit RAM Buffer Control Register */
1295 /* Bit 7.. 6: reserved */
1296 #define RB_ENA_STFWD BIT_5S /* Enable Store & Forward */
1297 #define RB_DIS_STFWD BIT_4S /* Disable Store & Forward */
1298 #define RB_ENA_OP_MD BIT_3S /* Enable Operation Mode */
1299 #define RB_DIS_OP_MD BIT_2S /* Disable Operation Mode */
1300 #define RB_RST_CLR BIT_1S /* Clear RAM Buf STM Reset */
1301 #define RB_RST_SET BIT_0S /* Set RAM Buf STM Reset */
1304 /* Receive and Transmit MAC FIFO Registers (GENESIS only) */
1306 /* RX_MFF_EA 32 bit Receive MAC FIFO End Address */
1307 /* RX_MFF_WP 32 bit Receive MAC FIFO Write Pointer */
1308 /* RX_MFF_RP 32 bit Receive MAC FIFO Read Pointer */
1309 /* RX_MFF_PC 32 bit Receive MAC FIFO Packet Counter */
1310 /* RX_MFF_LEV 32 bit Receive MAC FIFO Level */
1311 /* TX_MFF_EA 32 bit Transmit MAC FIFO End Address */
1312 /* TX_MFF_WP 32 bit Transmit MAC FIFO Write Pointer */
1313 /* TX_MFF_WSP 32 bit Transmit MAC FIFO WR Shadow Pointer */
1314 /* TX_MFF_RP 32 bit Transmit MAC FIFO Read Pointer */
1315 /* TX_MFF_PC 32 bit Transmit MAC FIFO Packet Cnt */
1316 /* TX_MFF_LEV 32 bit Transmit MAC FIFO Level */
1317 /* Bit 31.. 6: reserved */
1318 #define MFF_MSK 0x007fL /* Bit 5.. 0: MAC FIFO Address/Ptr Bits */
1320 /* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */
1321 /* Bit 15..14: reserved */
1322 #define MFF_ENA_RDY_PAT BIT_13S /* Enable Ready Patch */
1323 #define MFF_DIS_RDY_PAT BIT_12S /* Disable Ready Patch */
1324 #define MFF_ENA_TIM_PAT BIT_11S /* Enable Timing Patch */
1325 #define MFF_DIS_TIM_PAT BIT_10S /* Disable Timing Patch */
1326 #define MFF_ENA_ALM_FUL BIT_9S /* Enable AlmostFull Sign */
1327 #define MFF_DIS_ALM_FUL BIT_8S /* Disable AlmostFull Sign */
1328 #define MFF_ENA_PAUSE BIT_7S /* Enable Pause Signaling */
1329 #define MFF_DIS_PAUSE BIT_6S /* Disable Pause Signaling */
1330 #define MFF_ENA_FLUSH BIT_5S /* Enable Frame Flushing */
1331 #define MFF_DIS_FLUSH BIT_4S /* Disable Frame Flushing */
1332 #define MFF_ENA_TIST BIT_3S /* Enable Time Stamp Gener */
1333 #define MFF_DIS_TIST BIT_2S /* Disable Time Stamp Gener */
1334 #define MFF_CLR_INTIST BIT_1S /* Clear IRQ No Time Stamp */
1335 #define MFF_CLR_INSTAT BIT_0S /* Clear IRQ No Status */
1337 #define MFF_RX_CTRL_DEF MFF_ENA_TIM_PAT
1339 /* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
1340 #define MFF_CLR_PERR BIT_15S /* Clear Parity Error IRQ */
1341 /* Bit 14: reserved */
1342 #define MFF_ENA_PKT_REC BIT_13S /* Enable Packet Recovery */
1343 #define MFF_DIS_PKT_REC BIT_12S /* Disable Packet Recovery */
1344 /* MFF_ENA_TIM_PAT (see RX_MFF_CTRL1) Bit 11: Enable Timing Patch */
1345 /* MFF_DIS_TIM_PAT (see RX_MFF_CTRL1) Bit 10: Disable Timing Patch */
1346 /* MFF_ENA_ALM_FUL (see RX_MFF_CTRL1) Bit 9: Enable Almost Full Sign */
1347 /* MFF_DIS_ALM_FUL (see RX_MFF_CTRL1) Bit 8: Disable Almost Full Sign */
1348 #define MFF_ENA_W4E BIT_7S /* Enable Wait for Empty */
1349 #define MFF_DIS_W4E BIT_6S /* Disable Wait for Empty */
1350 /* MFF_ENA_FLUSH (see RX_MFF_CTRL1) Bit 5: Enable Frame Flushing */
1351 /* MFF_DIS_FLUSH (see RX_MFF_CTRL1) Bit 4: Disable Frame Flushing */
1352 #define MFF_ENA_LOOPB BIT_3S /* Enable Loopback */
1353 #define MFF_DIS_LOOPB BIT_2S /* Disable Loopback */
1354 #define MFF_CLR_MAC_RST BIT_1S /* Clear XMAC Reset */
1355 #define MFF_SET_MAC_RST BIT_0S /* Set XMAC Reset */
1357 #define MFF_TX_CTRL_DEF (MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH)
1359 /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
1360 /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
1361 /* Bit 7: reserved */
1362 #define MFF_WSP_T_ON BIT_6S /* Tx: Write Shadow Ptr TestOn */
1363 #define MFF_WSP_T_OFF BIT_5S /* Tx: Write Shadow Ptr TstOff */
1364 #define MFF_WSP_INC BIT_4S /* Tx: Write Shadow Ptr Increment */
1365 #define MFF_PC_DEC BIT_3S /* Packet Counter Decrement */
1366 #define MFF_PC_T_ON BIT_2S /* Packet Counter Test On */
1367 #define MFF_PC_T_OFF BIT_1S /* Packet Counter Test Off */
1368 #define MFF_PC_INC BIT_0S /* Packet Counter Increment */
1370 /* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */
1371 /* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */
1372 /* Bit 7: reserved */
1373 #define MFF_WP_T_ON BIT_6S /* Write Pointer Test On */
1374 #define MFF_WP_T_OFF BIT_5S /* Write Pointer Test Off */
1375 #define MFF_WP_INC BIT_4S /* Write Pointer Increm */
1376 /* Bit 3: reserved */
1377 #define MFF_RP_T_ON BIT_2S /* Read Pointer Test On */
1378 #define MFF_RP_T_OFF BIT_1S /* Read Pointer Test Off */
1379 #define MFF_RP_DEC BIT_0S /* Read Pointer Decrement */
1381 /* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */
1382 /* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */
1383 /* Bit 7..4: reserved */
1384 #define MFF_ENA_OP_MD BIT_3S /* Enable Operation Mode */
1385 #define MFF_DIS_OP_MD BIT_2S /* Disable Operation Mode */
1386 #define MFF_RST_CLR BIT_1S /* Clear MAC FIFO Reset */
1387 #define MFF_RST_SET BIT_0S /* Set MAC FIFO Reset */
1390 /* Link LED Counter Registers (GENESIS only) */
1392 /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
1393 /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
1394 /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
1395 /* Bit 7.. 3: reserved */
1396 #define LED_START BIT_2S /* Start Timer */
1397 #define LED_STOP BIT_1S /* Stop Timer */
1398 #define LED_STATE BIT_0S /* Rx/Tx: LED State, 1=LED on */
1399 #define LED_CLR_IRQ BIT_0S /* Lnk: Clear Link IRQ */
1401 /* RX_LED_TST 8 bit Receive LED Cnt Test Register */
1402 /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
1403 /* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */
1404 /* Bit 7.. 3: reserved */
1405 #define LED_T_ON BIT_2S /* LED Counter Test mode On */
1406 #define LED_T_OFF BIT_1S /* LED Counter Test mode Off */
1407 #define LED_T_STEP BIT_0S /* LED Counter Step */
1409 /* LNK_LED_REG 8 bit Link LED Register */
1410 /* Bit 7.. 6: reserved */
1411 #define LED_BLK_ON BIT_5S /* Link LED Blinking On */
1412 #define LED_BLK_OFF BIT_4S /* Link LED Blinking Off */
1413 #define LED_SYNC_ON BIT_3S /* Use Sync Wire to switch LED */
1414 #define LED_SYNC_OFF BIT_2S /* Disable Sync Wire Input */
1415 #define LED_ON BIT_1S /* switch LED on */
1416 #define LED_OFF BIT_0S /* switch LED off */
1418 /* Receive and Transmit GMAC FIFO Registers (YUKON only) */
1420 /* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */
1421 /* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */
1422 /* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */
1423 /* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */
1424 /* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */
1425 /* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */
1426 /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */
1427 /* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
1428 /* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */
1429 /* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Ptr. */
1430 /* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */
1431 /* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */
1432 /* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */
1433 /* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */
1435 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1436 /* Bits 31..15: reserved */
1437 #define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */
1438 #define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */
1439 #define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */
1440 /* Bit 11: reserved */
1441 #define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */
1442 #define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */
1443 #define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */
1444 #define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */
1445 #define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */
1446 #define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */
1447 #define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */
1448 #define GMF_OPER_ON BIT_3 /* Operational Mode On */
1449 #define GMF_OPER_OFF BIT_2 /* Operational Mode Off */
1450 #define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */
1451 #define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */
1453 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1454 /* Bits 31..19: reserved */
1455 #define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */
1456 #define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */
1457 #define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */
1458 /* Bits 15..7: same as for RX_GMF_CTRL_T */
1459 #define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */
1460 #define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */
1461 #define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */
1462 /* Bits 3..0: same as for RX_GMF_CTRL_T */
1464 #define GMF_RX_CTRL_DEF (GMF_OPER_ON | GMF_RX_F_FL_ON)
1465 #define GMF_TX_CTRL_DEF GMF_OPER_ON
1467 #define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */
1469 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1470 /* Bit 7.. 3: reserved */
1471 #define GMT_ST_START BIT_2S /* Start Time Stamp Timer */
1472 #define GMT_ST_STOP BIT_1S /* Stop Time Stamp Timer */
1473 #define GMT_ST_CLR_IRQ BIT_0S /* Clear Time Stamp Timer IRQ */
1475 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1476 /* Bits 31.. 8: reserved */
1477 #define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */
1478 #define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */
1479 #define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */
1480 #define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */
1481 #define GMC_PAUSE_ON BIT_3 /* Pause On */
1482 #define GMC_PAUSE_OFF BIT_2 /* Pause Off */
1483 #define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */
1484 #define GMC_RST_SET BIT_0 /* Set GMAC Reset */
1486 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1487 /* Bits 31..29: reserved */
1488 #define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */
1489 #define GPC_INT_POL_HI BIT_27 /* IRQ Polarity is Active HIGH */
1490 #define GPC_75_OHM BIT_26 /* Use 75 Ohm Termination instead of 50 */
1491 #define GPC_DIS_FC BIT_25 /* Disable Automatic Fiber/Copper Detection */
1492 #define GPC_DIS_SLEEP BIT_24 /* Disable Energy Detect */
1493 #define GPC_HWCFG_M_3 BIT_23 /* HWCFG_MODE[3] */
1494 #define GPC_HWCFG_M_2 BIT_22 /* HWCFG_MODE[2] */
1495 #define GPC_HWCFG_M_1 BIT_21 /* HWCFG_MODE[1] */
1496 #define GPC_HWCFG_M_0 BIT_20 /* HWCFG_MODE[0] */
1497 #define GPC_ANEG_0 BIT_19 /* ANEG[0] */
1498 #define GPC_ENA_XC BIT_18 /* Enable MDI crossover */
1499 #define GPC_DIS_125 BIT_17 /* Disable 125 MHz clock */
1500 #define GPC_ANEG_3 BIT_16 /* ANEG[3] */
1501 #define GPC_ANEG_2 BIT_15 /* ANEG[2] */
1502 #define GPC_ANEG_1 BIT_14 /* ANEG[1] */
1503 #define GPC_ENA_PAUSE BIT_13 /* Enable Pause (SYM_OR_REM) */
1504 #define GPC_PHYADDR_4 BIT_12 /* Bit 4 of Phy Addr */
1505 #define GPC_PHYADDR_3 BIT_11 /* Bit 3 of Phy Addr */
1506 #define GPC_PHYADDR_2 BIT_10 /* Bit 2 of Phy Addr */
1507 #define GPC_PHYADDR_1 BIT_9 /* Bit 1 of Phy Addr */
1508 #define GPC_PHYADDR_0 BIT_8 /* Bit 0 of Phy Addr */
1509 /* Bits 7..2: reserved */
1510 #define GPC_RST_CLR BIT_1 /* Clear GPHY Reset */
1511 #define GPC_RST_SET BIT_0 /* Set GPHY Reset */
1513 #define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | \
1514 GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
1516 #define GPC_HWCFG_GMII_FIB ( GPC_HWCFG_M_2 | \
1517 GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
1519 #define GPC_ANEG_ADV_ALL_M (GPC_ANEG_3 | GPC_ANEG_2 | \
1520 GPC_ANEG_1 | GPC_ANEG_0)
1522 /* forced speed and duplex mode (don't mix with other ANEG bits) */
1523 #define GPC_FRC10MBIT_HALF 0
1524 #define GPC_FRC10MBIT_FULL GPC_ANEG_0
1525 #define GPC_FRC100MBIT_HALF GPC_ANEG_1
1526 #define GPC_FRC100MBIT_FULL (GPC_ANEG_0 | GPC_ANEG_1)
1528 /* auto-negotiation with limited advertised speeds */
1529 /* mix only with master/slave settings (for copper) */
1530 #define GPC_ADV_1000_HALF GPC_ANEG_2
1531 #define GPC_ADV_1000_FULL GPC_ANEG_3
1532 #define GPC_ADV_ALL (GPC_ANEG_2 | GPC_ANEG_3)
1534 /* master/slave settings */
1535 /* only for copper with 1000 Mbps */
1536 #define GPC_FORCE_MASTER 0
1537 #define GPC_FORCE_SLAVE GPC_ANEG_0
1538 #define GPC_PREF_MASTER GPC_ANEG_1
1539 #define GPC_PREF_SLAVE (GPC_ANEG_1 | GPC_ANEG_0)
1541 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
1542 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
1543 #define GM_IS_TX_CO_OV BIT_5 /* Transmit Counter Overflow IRQ */
1544 #define GM_IS_RX_CO_OV BIT_4 /* Receive Counter Overflow IRQ */
1545 #define GM_IS_TX_FF_UR BIT_3 /* Transmit FIFO Underrun */
1546 #define GM_IS_TX_COMPL BIT_2 /* Frame Transmission Complete */
1547 #define GM_IS_RX_FF_OR BIT_1 /* Receive FIFO Overrun */
1548 #define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */
1550 #define GMAC_DEF_MSK (GM_IS_TX_CO_OV | GM_IS_RX_CO_OV | \
1553 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
1554 /* Bits 15.. 2: reserved */
1555 #define GMLC_RST_CLR BIT_1S /* Clear GMAC Link Reset */
1556 #define GMLC_RST_SET BIT_0S /* Set GMAC Link Reset */
1559 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
1560 #define WOL_CTL_LINK_CHG_OCC BIT_15S
1561 #define WOL_CTL_MAGIC_PKT_OCC BIT_14S
1562 #define WOL_CTL_PATTERN_OCC BIT_13S
1564 #define WOL_CTL_CLEAR_RESULT BIT_12S
1566 #define WOL_CTL_ENA_PME_ON_LINK_CHG BIT_11S
1567 #define WOL_CTL_DIS_PME_ON_LINK_CHG BIT_10S
1568 #define WOL_CTL_ENA_PME_ON_MAGIC_PKT BIT_9S
1569 #define WOL_CTL_DIS_PME_ON_MAGIC_PKT BIT_8S
1570 #define WOL_CTL_ENA_PME_ON_PATTERN BIT_7S
1571 #define WOL_CTL_DIS_PME_ON_PATTERN BIT_6S
1573 #define WOL_CTL_ENA_LINK_CHG_UNIT BIT_5S
1574 #define WOL_CTL_DIS_LINK_CHG_UNIT BIT_4S
1575 #define WOL_CTL_ENA_MAGIC_PKT_UNIT BIT_3S
1576 #define WOL_CTL_DIS_MAGIC_PKT_UNIT BIT_2S
1577 #define WOL_CTL_ENA_PATTERN_UNIT BIT_1S
1578 #define WOL_CTL_DIS_PATTERN_UNIT BIT_0S
1580 #define WOL_CTL_DEFAULT \
1581 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
1582 WOL_CTL_DIS_PME_ON_PATTERN | \
1583 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
1584 WOL_CTL_DIS_LINK_CHG_UNIT | \
1585 WOL_CTL_DIS_PATTERN_UNIT | \
1586 WOL_CTL_DIS_MAGIC_PKT_UNIT)
1588 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
1589 #define WOL_CTL_PATT_ENA(x) (BIT_0 << (x))
1591 #define SK_NUM_WOL_PATTERN 7
1592 #define SK_PATTERN_PER_WORD 4
1593 #define SK_BITMASK_PATTERN 7
1594 #define SK_POW_PATTERN_LENGTH 128
1596 #define WOL_LENGTH_MSK 0x7f
1597 #define WOL_LENGTH_SHIFT 8
1600 /* Receive and Transmit Descriptors ******************************************/
1602 /* Transmit Descriptor struct */
1603 typedef struct s_HwTxd {
1604 SK_U32 volatile TxCtrl; /* Transmit Buffer Control Field */
1605 SK_U32 TxNext; /* Physical Address Pointer to the next TxD */
1606 SK_U32 TxAdrLo; /* Physical Tx Buffer Address lower dword */
1607 SK_U32 TxAdrHi; /* Physical Tx Buffer Address upper dword */
1608 SK_U32 TxStat; /* Transmit Frame Status Word */
1609 #ifndef SK_USE_REV_DESC
1610 SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */
1611 SK_U16 TxRes1; /* 16 bit reserved field */
1612 SK_U16 TxTcpWp; /* TCP Checksum Write Position */
1613 SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
1614 #else /* SK_USE_REV_DESC */
1615 SK_U16 TxRes1; /* 16 bit reserved field */
1616 SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */
1617 SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
1618 SK_U16 TxTcpWp; /* TCP Checksum Write Position */
1619 #endif /* SK_USE_REV_DESC */
1620 SK_U32 TxRes2; /* 32 bit reserved field */
1623 /* Receive Descriptor struct */
1624 typedef struct s_HwRxd {
1625 SK_U32 volatile RxCtrl; /* Receive Buffer Control Field */
1626 SK_U32 RxNext; /* Physical Address Pointer to the next RxD */
1627 SK_U32 RxAdrLo; /* Physical Rx Buffer Address lower dword */
1628 SK_U32 RxAdrHi; /* Physical Rx Buffer Address upper dword */
1629 SK_U32 RxStat; /* Receive Frame Status Word */
1630 SK_U32 RxTiSt; /* Receive Time Stamp (from XMAC on GENESIS) */
1631 #ifndef SK_USE_REV_DESC
1632 SK_U16 RxTcpSum1; /* TCP Checksum 1 */
1633 SK_U16 RxTcpSum2; /* TCP Checksum 2 */
1634 SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
1635 SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
1636 #else /* SK_USE_REV_DESC */
1637 SK_U16 RxTcpSum2; /* TCP Checksum 2 */
1638 SK_U16 RxTcpSum1; /* TCP Checksum 1 */
1639 SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
1640 SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
1641 #endif /* SK_USE_REV_DESC */
1645 * Drivers which use the reverse descriptor feature (PCI_OUR_REG_2)
1646 * should set the define SK_USE_REV_DESC.
1647 * Structures are 'normaly' not endianess dependent. But in
1648 * this case the SK_U16 fields are bound to bit positions inside the
1649 * descriptor. RxTcpSum1 e.g. must start at bit 0 within the 6.th DWord.
1650 * The bit positions inside a DWord are of course endianess dependent and
1651 * swaps if the DWord is swapped by the hardware.
1655 /* Descriptor Bit Definition */
1656 /* TxCtrl Transmit Buffer Control Field */
1657 /* RxCtrl Receive Buffer Control Field */
1658 #define BMU_OWN BIT_31 /* OWN bit: 0=host/1=BMU */
1659 #define BMU_STF BIT_30 /* Start of Frame */
1660 #define BMU_EOF BIT_29 /* End of Frame */
1661 #define BMU_IRQ_EOB BIT_28 /* Req "End of Buffer" IRQ */
1662 #define BMU_IRQ_EOF BIT_27 /* Req "End of Frame" IRQ */
1663 /* TxCtrl specific bits */
1664 #define BMU_STFWD BIT_26 /* (Tx) Store & Forward Frame */
1665 #define BMU_NO_FCS BIT_25 /* (Tx) Disable MAC FCS (CRC) generation */
1666 #define BMU_SW BIT_24 /* (Tx) 1 bit res. for SW use */
1667 /* RxCtrl specific bits */
1668 #define BMU_DEV_0 BIT_26 /* (Rx) Transfer data to Dev0 */
1669 #define BMU_STAT_VAL BIT_25 /* (Rx) Rx Status Valid */
1670 #define BMU_TIST_VAL BIT_24 /* (Rx) Rx TimeStamp Valid */
1671 /* Bit 23..16: BMU Check Opcodes */
1672 #define BMU_CHECK (0x55L<<16) /* Default BMU check */
1673 #define BMU_TCP_CHECK (0x56L<<16) /* Descr with TCP ext */
1674 #define BMU_UDP_CHECK (0x57L<<16) /* Descr with UDP ext (YUKON only) */
1675 #define BMU_BBC 0xffffL /* Bit 15.. 0: Buffer Byte Counter */
1677 /* TxStat Transmit Frame Status Word */
1678 /* RxStat Receive Frame Status Word */
1680 *Note: TxStat is reserved for ASIC loopback mode only
1682 * The Bits of the Status words are defined in xmac_ii.h
1686 /* macros ********************************************************************/
1688 /* Receive and Transmit Queues */
1689 #define Q_R1 0x0000 /* Receive Queue 1 */
1690 #define Q_R2 0x0080 /* Receive Queue 2 */
1691 #define Q_XS1 0x0200 /* Synchronous Transmit Queue 1 */
1692 #define Q_XA1 0x0280 /* Asynchronous Transmit Queue 1 */
1693 #define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */
1694 #define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */
1699 * Use this macro to access the Receive and Transmit Queue Registers.
1702 * Queue Queue to access.
1703 * Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, and Q_XA2
1704 * Offs Queue register offset.
1705 * Values: Q_D, Q_DA_L ... Q_T2, Q_T3
1707 * usage SK_IN32(pAC, Q_ADDR(Q_R2, Q_BC), pVal)
1709 #define Q_ADDR(Queue, Offs) (B8_Q_REGS + (Queue) + (Offs))
1714 * Use this macro to access the RAM Buffer Registers.
1717 * Queue Queue to access.
1718 * Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, and Q_XA2
1719 * Offs Queue register offset.
1720 * Values: RB_START, RB_END ... RB_LEV, RB_CTRL
1722 * usage SK_IN32(pAC, RB_ADDR(Q_R2, RB_RP), pVal)
1724 #define RB_ADDR(Queue, Offs) (B16_RAM_REGS + (Queue) + (Offs))
1727 /* MAC Related Registers */
1728 #define MAC_1 0 /* belongs to the port near the slot */
1729 #define MAC_2 1 /* belongs to the port far away from the slot */
1734 * Use this macro to access a MAC Related Registers inside the ASIC.
1737 * Mac MAC to access.
1738 * Values: MAC_1, MAC_2
1739 * Offs MAC register offset.
1740 * Values: RX_MFF_EA, RX_MFF_WP ... LNK_LED_REG,
1741 * TX_MFF_EA, TX_MFF_WP ... TX_LED_TST
1743 * usage SK_IN32(pAC, MR_ADDR(MAC_1, TX_MFF_EA), pVal)
1745 #define MR_ADDR(Mac, Offs) (((Mac) << 7) + (Offs))
1747 #ifdef SK_LITTLE_ENDIAN
1748 #define XM_WORD_LO 0
1749 #define XM_WORD_HI 1
1750 #else /* !SK_LITTLE_ENDIAN */
1751 #define XM_WORD_LO 1
1752 #define XM_WORD_HI 0
1753 #endif /* !SK_LITTLE_ENDIAN */
1757 * macros to access the XMAC (GENESIS only)
1759 * XM_IN16(), to read a 16 bit register (e.g. XM_MMU_CMD)
1760 * XM_OUT16(), to write a 16 bit register (e.g. XM_MMU_CMD)
1761 * XM_IN32(), to read a 32 bit register (e.g. XM_TX_EV_CNT)
1762 * XM_OUT32(), to write a 32 bit register (e.g. XM_TX_EV_CNT)
1763 * XM_INADDR(), to read a network address register (e.g. XM_SRC_CHK)
1764 * XM_OUTADDR(), to write a network address register (e.g. XM_SRC_CHK)
1765 * XM_INHASH(), to read the XM_HSM_CHK register
1766 * XM_OUTHASH() to write the XM_HSM_CHK register
1769 * Mac XMAC to access values: MAC_1 or MAC_2
1770 * IoC I/O context needed for SK I/O macros
1771 * Reg XMAC Register to read or write
1772 * (p)Val Value or pointer to the value which should be read or written
1774 * usage: XM_OUT16(IoC, MAC_1, XM_MMU_CMD, Value);
1777 #define XMA(Mac, Reg) \
1778 ((BASE_XMAC_1 + (Mac) * (BASE_XMAC_2 - BASE_XMAC_1)) | ((Reg) << 1))
1780 #define XM_IN16(IoC, Mac, Reg, pVal) \
1781 SK_IN16((IoC), XMA((Mac), (Reg)), (pVal))
1783 #define XM_OUT16(IoC, Mac, Reg, Val) \
1784 SK_OUT16((IoC), XMA((Mac), (Reg)), (Val))
1786 #define XM_IN32(IoC, Mac, Reg, pVal) { \
1787 SK_IN16((IoC), XMA((Mac), (Reg)), \
1788 (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_LO]); \
1789 SK_IN16((IoC), XMA((Mac), (Reg+2)), \
1790 (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_HI]); \
1793 #define XM_OUT32(IoC, Mac, Reg, Val) { \
1794 SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16)((Val) & 0xffffL)); \
1795 SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16)(((Val) >> 16) & 0xffffL));\
1798 /* Remember: we are always writing to / reading from LITTLE ENDIAN memory */
1800 #define XM_INADDR(IoC, Mac, Reg, pVal) { \
1803 pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
1804 SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \
1805 pByte[0] = (SK_U8)(Word & 0x00ff); \
1806 pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
1807 SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \
1808 pByte[2] = (SK_U8)(Word & 0x00ff); \
1809 pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
1810 SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \
1811 pByte[4] = (SK_U8)(Word & 0x00ff); \
1812 pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
1815 #define XM_OUTADDR(IoC, Mac, Reg, pVal) { \
1816 SK_U8 SK_FAR *pByte; \
1817 pByte = (SK_U8 SK_FAR *)&((SK_U8 SK_FAR *)(pVal))[0]; \
1818 SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \
1819 (((SK_U16)(pByte[0]) & 0x00ff) | \
1820 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
1821 SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \
1822 (((SK_U16)(pByte[2]) & 0x00ff) | \
1823 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
1824 SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \
1825 (((SK_U16)(pByte[4]) & 0x00ff) | \
1826 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
1829 #define XM_INHASH(IoC, Mac, Reg, pVal) { \
1831 SK_U8 SK_FAR *pByte; \
1832 pByte = (SK_U8 SK_FAR *)&((SK_U8 SK_FAR *)(pVal))[0]; \
1833 SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \
1834 pByte[0] = (SK_U8)(Word & 0x00ff); \
1835 pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
1836 SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \
1837 pByte[2] = (SK_U8)(Word & 0x00ff); \
1838 pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
1839 SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \
1840 pByte[4] = (SK_U8)(Word & 0x00ff); \
1841 pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
1842 SK_IN16((IoC), XMA((Mac), (Reg+6)), &Word); \
1843 pByte[6] = (SK_U8)(Word & 0x00ff); \
1844 pByte[7] = (SK_U8)((Word >> 8) & 0x00ff); \
1847 #define XM_OUTHASH(IoC, Mac, Reg, pVal) { \
1848 SK_U8 SK_FAR *pByte; \
1849 pByte = (SK_U8 SK_FAR *)&((SK_U8 SK_FAR *)(pVal))[0]; \
1850 SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \
1851 (((SK_U16)(pByte[0]) & 0x00ff)| \
1852 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
1853 SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \
1854 (((SK_U16)(pByte[2]) & 0x00ff)| \
1855 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
1856 SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \
1857 (((SK_U16)(pByte[4]) & 0x00ff)| \
1858 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
1859 SK_OUT16((IoC), XMA((Mac), (Reg+6)), (SK_U16) \
1860 (((SK_U16)(pByte[6]) & 0x00ff)| \
1861 (((SK_U16)(pByte[7]) << 8) & 0xff00))); \
1865 * macros to access the GMAC (YUKON only)
1867 * GM_IN16(), to read a 16 bit register (e.g. GM_GP_STAT)
1868 * GM_OUT16(), to write a 16 bit register (e.g. GM_GP_CTRL)
1869 * GM_IN32(), to read a 32 bit register (e.g. GM_)
1870 * GM_OUT32(), to write a 32 bit register (e.g. GM_)
1871 * GM_INADDR(), to read a network address register (e.g. GM_SRC_ADDR_1L)
1872 * GM_OUTADDR(), to write a network address register (e.g. GM_SRC_ADDR_2L)
1873 * GM_INHASH(), to read the GM_MC_ADDR_H1 register
1874 * GM_OUTHASH() to write the GM_MC_ADDR_H1 register
1877 * Mac GMAC to access values: MAC_1 or MAC_2
1878 * IoC I/O context needed for SK I/O macros
1879 * Reg GMAC Register to read or write
1880 * (p)Val Value or pointer to the value which should be read or written
1882 * usage: GM_OUT16(IoC, MAC_1, GM_GP_CTRL, Value);
1885 #define GMA(Mac, Reg) \
1886 ((BASE_GMAC_1 + (Mac) * (BASE_GMAC_2 - BASE_GMAC_1)) | (Reg))
1888 #define GM_IN16(IoC, Mac, Reg, pVal) \
1889 SK_IN16((IoC), GMA((Mac), (Reg)), (pVal))
1891 #define GM_OUT16(IoC, Mac, Reg, Val) \
1892 SK_OUT16((IoC), GMA((Mac), (Reg)), (Val))
1894 #define GM_IN32(IoC, Mac, Reg, pVal) { \
1895 SK_IN16((IoC), GMA((Mac), (Reg)), \
1896 (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_LO]); \
1897 SK_IN16((IoC), GMA((Mac), (Reg+4)), \
1898 (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_HI]); \
1901 #define GM_OUT32(IoC, Mac, Reg, Val) { \
1902 SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16)((Val) & 0xffffL)); \
1903 SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16)(((Val) >> 16) & 0xffffL));\
1906 #define GM_INADDR(IoC, Mac, Reg, pVal) { \
1909 pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
1910 SK_IN16((IoC), GMA((Mac), (Reg)), &Word); \
1911 pByte[0] = (SK_U8)(Word & 0x00ff); \
1912 pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
1913 SK_IN16((IoC), GMA((Mac), (Reg+4)), &Word); \
1914 pByte[2] = (SK_U8)(Word & 0x00ff); \
1915 pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
1916 SK_IN16((IoC), GMA((Mac), (Reg+8)), &Word); \
1917 pByte[4] = (SK_U8)(Word & 0x00ff); \
1918 pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
1921 #define GM_OUTADDR(IoC, Mac, Reg, pVal) { \
1922 SK_U8 SK_FAR *pByte; \
1923 pByte = (SK_U8 SK_FAR *)&((SK_U8 SK_FAR *)(pVal))[0]; \
1924 SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16) \
1925 (((SK_U16)(pByte[0]) & 0x00ff) | \
1926 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
1927 SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16) \
1928 (((SK_U16)(pByte[2]) & 0x00ff) | \
1929 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
1930 SK_OUT16((IoC), GMA((Mac), (Reg+8)), (SK_U16) \
1931 (((SK_U16)(pByte[4]) & 0x00ff) | \
1932 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
1935 #define GM_INHASH(IoC, Mac, Reg, pVal) { \
1938 pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
1939 SK_IN16((IoC), GMA((Mac), (Reg)), &Word); \
1940 pByte[0] = (SK_U8)(Word & 0x00ff); \
1941 pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
1942 SK_IN16((IoC), GMA((Mac), (Reg+4)), &Word); \
1943 pByte[2] = (SK_U8)(Word & 0x00ff); \
1944 pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
1945 SK_IN16((IoC), GMA((Mac), (Reg+8)), &Word); \
1946 pByte[4] = (SK_U8)(Word & 0x00ff); \
1947 pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
1948 SK_IN16((IoC), GMA((Mac), (Reg+12)), &Word); \
1949 pByte[6] = (SK_U8)(Word & 0x00ff); \
1950 pByte[7] = (SK_U8)((Word >> 8) & 0x00ff); \
1953 #define GM_OUTHASH(IoC, Mac, Reg, pVal) { \
1955 pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
1956 SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16) \
1957 (((SK_U16)(pByte[0]) & 0x00ff)| \
1958 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
1959 SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16) \
1960 (((SK_U16)(pByte[2]) & 0x00ff)| \
1961 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
1962 SK_OUT16((IoC), GMA((Mac), (Reg+8)), (SK_U16) \
1963 (((SK_U16)(pByte[4]) & 0x00ff)| \
1964 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
1965 SK_OUT16((IoC), GMA((Mac), (Reg+12)), (SK_U16) \
1966 (((SK_U16)(pByte[6]) & 0x00ff)| \
1967 (((SK_U16)(pByte[7]) << 8) & 0xff00))); \
1971 * Different MAC Types
1973 #define SK_MAC_XMAC 0 /* Xaqti XMAC II */
1974 #define SK_MAC_GMAC 1 /* Marvell GMAC */
1977 * Different PHY Types
1979 #define SK_PHY_XMAC 0 /* integrated in XMAC II */
1980 #define SK_PHY_BCOM 1 /* Broadcom BCM5400 */
1981 #define SK_PHY_LONE 2 /* Level One LXT1000 */
1982 #define SK_PHY_NAT 3 /* National DP83891 */
1983 #define SK_PHY_MARV_COPPER 4 /* Marvell 88E1011S */
1984 #define SK_PHY_MARV_FIBER 5 /* Marvell 88E1011S working on fiber */
1987 * PHY addresses (bits 12..8 of PHY address reg)
1989 #define PHY_ADDR_XMAC (0<<8)
1990 #define PHY_ADDR_BCOM (1<<8)
1991 #define PHY_ADDR_LONE (3<<8)
1992 #define PHY_ADDR_NAT (0<<8)
1994 /* GPHY address (bits 15..11 of SMI control reg) */
1995 #define PHY_ADDR_MARV 0
1998 * macros to access the PHY
2000 * PHY_READ() read a 16 bit value from the PHY
2001 * PHY_WRITE() write a 16 bit value to the PHY
2004 * IoC I/O context needed for SK I/O macros
2005 * pPort Pointer to port struct for PhyAddr
2006 * Mac XMAC to access values: MAC_1 or MAC_2
2007 * PhyReg PHY Register to read or write
2008 * (p)Val Value or pointer to the value which should be read or
2011 * usage: PHY_READ(IoC, pPort, MAC_1, PHY_CTRL, Value);
2012 * Warning: a PHY_READ on an uninitialized PHY (PHY still in reset) never
2013 * comes back. This is checked in DEBUG mode.
2016 #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \
2019 XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \
2020 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
2021 if ((pPort)->PhyType != SK_PHY_XMAC) { \
2023 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
2024 } while ((Mmu & XM_MMU_PHY_RDY) == 0); \
2025 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
2029 #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \
2033 XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \
2034 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
2035 if ((pPort)->PhyType != SK_PHY_XMAC) { \
2037 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
2039 if (__i > 100000) { \
2040 SK_DBG_PRINTF("*****************************\n"); \
2041 SK_DBG_PRINTF("PHY_READ on uninitialized PHY\n"); \
2042 SK_DBG_PRINTF("*****************************\n"); \
2045 } while ((Mmu & XM_MMU_PHY_RDY) == 0); \
2046 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
2051 #define PHY_WRITE(IoC, pPort, Mac, PhyReg, Val) { \
2054 if ((pPort)->PhyType != SK_PHY_XMAC) { \
2056 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
2057 } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \
2059 XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \
2060 XM_OUT16((IoC), (Mac), XM_PHY_DATA, (Val)); \
2061 if ((pPort)->PhyType != SK_PHY_XMAC) { \
2063 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
2064 } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \
2071 * Use this macro to access PCI config register from the I/O space.
2074 * Addr PCI configuration register to access.
2075 * Values: PCI_VENDOR_ID ... PCI_VPD_ADR_REG,
2077 * usage SK_IN16(pAC, PCI_C(PCI_VENDOR_ID), pVal);
2079 #define PCI_C(Addr) (B7_CFG_SPC + (Addr)) /* PCI Config Space */
2082 * Macro SK_HW_ADDR(Base, Addr)
2084 * Calculates the effective HW address
2087 * Base I/O or memory base address
2088 * Addr Address offset
2090 * usage: May be used in SK_INxx and SK_OUTxx macros
2091 * #define SK_IN8(pAC, Addr, pVal) ...\
2092 * *pVal = (SK_U8)inp(SK_HW_ADDR(pAC->Hw.Iop, Addr)))
2094 #ifdef SK_MEM_MAPPED_IO
2095 #define SK_HW_ADDR(Base, Addr) ((Base) + (Addr))
2096 #else /* SK_MEM_MAPPED_IO */
2097 #define SK_HW_ADDR(Base, Addr) \
2098 ((Base) + (((Addr) & 0x7f) | (((Addr) >> 7 > 0) ? 0x80 : 0)))
2099 #endif /* SK_MEM_MAPPED_IO */
2101 #define SZ_LONG (sizeof(SK_U32))
2104 * Macro SK_HWAC_LINK_LED()
2106 * Use this macro to set the link LED mode.
2108 * pAC Pointer to adapter context struct
2109 * IoC I/O context needed for SK I/O macros
2111 * Mode Mode to set for this LED
2113 #define SK_HWAC_LINK_LED(pAC, IoC, Port, Mode) \
2114 SK_OUT8(IoC, MR_ADDR(Port, LNK_LED_REG), Mode);
2117 /* typedefs *******************************************************************/
2120 /* function prototypes ********************************************************/
2124 #endif /* __cplusplus */
2126 #endif /* __INC_SKGEHW_H */
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