2 Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>
4 National Semiconductor SCx200 ACCESS.bus support
5 Also supports the AMD CS5535 and AMD CS5536
7 Based on i2c-keywest.c which is:
8 Copyright (c) 2001 Benjamin Herrenschmidt <benh@kernel.crashing.org>
9 Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
11 This program is free software; you can redistribute it and/or
12 modify it under the terms of the GNU General Public License as
13 published by the Free Software Foundation; either version 2 of the
14 License, or (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/module.h>
27 #include <linux/errno.h>
28 #include <linux/kernel.h>
29 #include <linux/init.h>
30 #include <linux/i2c.h>
31 #include <linux/pci.h>
32 #include <linux/delay.h>
33 #include <linux/mutex.h>
36 #include <linux/scx200.h>
38 #define NAME "scx200_acb"
40 MODULE_AUTHOR("Christer Weinigel <wingel@nano-system.com>");
41 MODULE_DESCRIPTION("NatSemi SCx200 ACCESS.bus Driver");
42 MODULE_LICENSE("GPL");
45 static int base[MAX_DEVICES] = { 0x820, 0x840 };
46 module_param_array(base, int, NULL, 0);
47 MODULE_PARM_DESC(base, "Base addresses for the ACCESS.bus controllers");
49 #define POLL_TIMEOUT (HZ/5)
51 enum scx200_acb_state {
61 static const char *scx200_acb_state_name[] = {
71 /* Physical interface */
72 struct scx200_acb_iface {
73 struct scx200_acb_iface *next;
74 struct i2c_adapter adapter;
78 /* State machine data */
79 enum scx200_acb_state state;
92 /* Register Definitions */
93 #define ACBSDA (iface->base + 0)
94 #define ACBST (iface->base + 1)
95 #define ACBST_SDAST 0x40 /* SDA Status */
96 #define ACBST_BER 0x20
97 #define ACBST_NEGACK 0x10 /* Negative Acknowledge */
98 #define ACBST_STASTR 0x08 /* Stall After Start */
99 #define ACBST_MASTER 0x02
100 #define ACBCST (iface->base + 2)
101 #define ACBCST_BB 0x02
102 #define ACBCTL1 (iface->base + 3)
103 #define ACBCTL1_STASTRE 0x80
104 #define ACBCTL1_NMINTE 0x40
105 #define ACBCTL1_ACK 0x10
106 #define ACBCTL1_STOP 0x02
107 #define ACBCTL1_START 0x01
108 #define ACBADDR (iface->base + 4)
109 #define ACBCTL2 (iface->base + 5)
110 #define ACBCTL2_ENABLE 0x01
112 /************************************************************************/
114 static void scx200_acb_machine(struct scx200_acb_iface *iface, u8 status)
118 dev_dbg(&iface->adapter.dev, "state %s, status = 0x%02x\n",
119 scx200_acb_state_name[iface->state], status);
121 if (status & ACBST_BER) {
122 errmsg = "bus error";
125 if (!(status & ACBST_MASTER)) {
126 errmsg = "not master";
129 if (status & ACBST_NEGACK) {
130 dev_dbg(&iface->adapter.dev, "negative ack in state %s\n",
131 scx200_acb_state_name[iface->state]);
133 iface->state = state_idle;
134 iface->result = -ENXIO;
136 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
137 outb(ACBST_STASTR | ACBST_NEGACK, ACBST);
139 /* Reset the status register */
144 switch (iface->state) {
146 dev_warn(&iface->adapter.dev, "interrupt in idle state\n");
150 /* Do a pointer write first */
151 outb(iface->address_byte & ~1, ACBSDA);
153 iface->state = state_command;
157 outb(iface->command, ACBSDA);
159 if (iface->address_byte & 1)
160 iface->state = state_repeat_start;
162 iface->state = state_write;
165 case state_repeat_start:
166 outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1);
170 if (iface->address_byte & 1) {
172 outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1);
174 outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1);
175 outb(iface->address_byte, ACBSDA);
177 iface->state = state_read;
179 outb(iface->address_byte, ACBSDA);
181 iface->state = state_write;
186 /* Set ACK if _next_ byte will be the last one */
188 outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1);
190 outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1);
192 if (iface->len == 1) {
194 iface->state = state_idle;
195 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
198 *iface->ptr++ = inb(ACBSDA);
204 if (iface->len == 0) {
206 iface->state = state_idle;
207 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
211 outb(*iface->ptr++, ACBSDA);
220 dev_err(&iface->adapter.dev, "%s in state %s\n", errmsg,
221 scx200_acb_state_name[iface->state]);
223 iface->state = state_idle;
224 iface->result = -EIO;
225 iface->needs_reset = 1;
228 static void scx200_acb_poll(struct scx200_acb_iface *iface)
231 unsigned long timeout;
233 timeout = jiffies + POLL_TIMEOUT;
237 /* Reset the status register to avoid the hang */
240 if ((status & (ACBST_SDAST|ACBST_BER|ACBST_NEGACK)) != 0) {
241 scx200_acb_machine(iface, status);
244 if (time_after(jiffies, timeout))
250 dev_err(&iface->adapter.dev, "timeout in state %s\n",
251 scx200_acb_state_name[iface->state]);
253 iface->state = state_idle;
254 iface->result = -EIO;
255 iface->needs_reset = 1;
258 static void scx200_acb_reset(struct scx200_acb_iface *iface)
260 /* Disable the ACCESS.bus device and Configure the SCL
261 frequency: 16 clock cycles */
265 /* Disable slave address */
267 /* Enable the ACCESS.bus device */
268 outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2);
269 /* Free STALL after START */
270 outb(inb(ACBCTL1) & ~(ACBCTL1_STASTRE | ACBCTL1_NMINTE), ACBCTL1);
272 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
273 /* Clear BER, NEGACK and STASTR bits */
274 outb(ACBST_BER | ACBST_NEGACK | ACBST_STASTR, ACBST);
276 outb(inb(ACBCST) | ACBCST_BB, ACBCST);
279 static s32 scx200_acb_smbus_xfer(struct i2c_adapter *adapter,
280 u16 address, unsigned short flags,
281 char rw, u8 command, int size,
282 union i2c_smbus_data *data)
284 struct scx200_acb_iface *iface = i2c_get_adapdata(adapter);
291 case I2C_SMBUS_QUICK:
298 buffer = rw ? &data->byte : &command;
301 case I2C_SMBUS_BYTE_DATA:
303 buffer = &data->byte;
306 case I2C_SMBUS_WORD_DATA:
308 cur_word = cpu_to_le16(data->word);
309 buffer = (u8 *)&cur_word;
312 case I2C_SMBUS_I2C_BLOCK_DATA:
313 len = data->block[0];
314 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
316 buffer = &data->block[1];
323 dev_dbg(&adapter->dev,
324 "size=%d, address=0x%x, command=0x%x, len=%d, read=%d\n",
325 size, address, command, len, rw);
327 if (!len && rw == I2C_SMBUS_READ) {
328 dev_dbg(&adapter->dev, "zero length read\n");
332 mutex_lock(&iface->mutex);
334 iface->address_byte = (address << 1) | rw;
335 iface->command = command;
338 iface->result = -EINVAL;
339 iface->needs_reset = 0;
341 outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1);
343 if (size == I2C_SMBUS_QUICK || size == I2C_SMBUS_BYTE)
344 iface->state = state_quick;
346 iface->state = state_address;
348 while (iface->state != state_idle)
349 scx200_acb_poll(iface);
351 if (iface->needs_reset)
352 scx200_acb_reset(iface);
356 mutex_unlock(&iface->mutex);
358 if (rc == 0 && size == I2C_SMBUS_WORD_DATA && rw == I2C_SMBUS_READ)
359 data->word = le16_to_cpu(cur_word);
362 dev_dbg(&adapter->dev, "transfer done, result: %d", rc);
366 for (i = 0; i < len; ++i)
367 printk(" %02x", buffer[i]);
375 static u32 scx200_acb_func(struct i2c_adapter *adapter)
377 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
378 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
379 I2C_FUNC_SMBUS_I2C_BLOCK;
382 /* For now, we only handle combined mode (smbus) */
383 static const struct i2c_algorithm scx200_acb_algorithm = {
384 .smbus_xfer = scx200_acb_smbus_xfer,
385 .functionality = scx200_acb_func,
388 static struct scx200_acb_iface *scx200_acb_list;
389 static DEFINE_MUTEX(scx200_acb_list_mutex);
391 static __init int scx200_acb_probe(struct scx200_acb_iface *iface)
395 /* Disable the ACCESS.bus device and Configure the SCL
396 frequency: 16 clock cycles */
399 if (inb(ACBCTL2) != 0x70) {
400 pr_debug(NAME ": ACBCTL2 readback failed\n");
404 outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1);
408 pr_debug(NAME ": disabled, but ACBCTL1=0x%02x\n",
413 outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2);
415 outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1);
418 if ((val & ACBCTL1_NMINTE) != ACBCTL1_NMINTE) {
419 pr_debug(NAME ": enabled, but NMINTE won't be set, "
420 "ACBCTL1=0x%02x\n", val);
427 static __init struct scx200_acb_iface *scx200_create_iface(const char *text,
428 struct device *dev, int index)
430 struct scx200_acb_iface *iface;
431 struct i2c_adapter *adapter;
433 iface = kzalloc(sizeof(*iface), GFP_KERNEL);
435 printk(KERN_ERR NAME ": can't allocate memory\n");
439 adapter = &iface->adapter;
440 i2c_set_adapdata(adapter, iface);
441 snprintf(adapter->name, sizeof(adapter->name), "%s ACB%d", text, index);
442 adapter->owner = THIS_MODULE;
443 adapter->algo = &scx200_acb_algorithm;
444 adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
445 adapter->dev.parent = dev;
447 mutex_init(&iface->mutex);
452 static int __init scx200_acb_create(struct scx200_acb_iface *iface)
454 struct i2c_adapter *adapter;
457 adapter = &iface->adapter;
459 rc = scx200_acb_probe(iface);
461 printk(KERN_WARNING NAME ": probe failed\n");
465 scx200_acb_reset(iface);
467 if (i2c_add_adapter(adapter) < 0) {
468 printk(KERN_ERR NAME ": failed to register\n");
472 mutex_lock(&scx200_acb_list_mutex);
473 iface->next = scx200_acb_list;
474 scx200_acb_list = iface;
475 mutex_unlock(&scx200_acb_list_mutex);
480 static __init int scx200_create_pci(const char *text, struct pci_dev *pdev,
483 struct scx200_acb_iface *iface;
486 iface = scx200_create_iface(text, &pdev->dev, 0);
494 rc = pci_enable_device_io(iface->pdev);
498 rc = pci_request_region(iface->pdev, iface->bar, iface->adapter.name);
500 printk(KERN_ERR NAME ": can't allocate PCI BAR %d\n",
505 iface->base = pci_resource_start(iface->pdev, iface->bar);
506 rc = scx200_acb_create(iface);
511 pci_release_region(iface->pdev, iface->bar);
512 pci_dev_put(iface->pdev);
518 static int __init scx200_create_isa(const char *text, unsigned long base,
521 struct scx200_acb_iface *iface;
524 iface = scx200_create_iface(text, NULL, index);
529 if (!request_region(base, 8, iface->adapter.name)) {
530 printk(KERN_ERR NAME ": can't allocate io 0x%lx-0x%lx\n",
537 rc = scx200_acb_create(iface);
542 release_region(base, 8);
548 /* Driver data is an index into the scx200_data array that indicates
549 * the name and the BAR where the I/O address resource is located. ISA
550 * devices are flagged with a bar value of -1 */
552 static struct pci_device_id scx200_pci[] = {
553 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_BRIDGE),
555 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SC1100_BRIDGE),
557 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA),
559 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA),
572 static __init int scx200_scan_pci(void)
576 struct pci_dev *pdev;
578 for(dev = 0; dev < ARRAY_SIZE(scx200_pci); dev++) {
579 pdev = pci_get_device(scx200_pci[dev].vendor,
580 scx200_pci[dev].device, NULL);
585 data = scx200_pci[dev].driver_data;
587 /* if .bar is greater or equal to zero, this is a
588 * PCI device - otherwise, we assume
589 that the ports are ISA based
592 if (scx200_data[data].bar >= 0)
593 rc = scx200_create_pci(scx200_data[data].name, pdev,
594 scx200_data[data].bar);
599 for (i = 0; i < MAX_DEVICES; ++i) {
603 rc = scx200_create_isa(scx200_data[data].name,
615 static int __init scx200_acb_init(void)
619 pr_debug(NAME ": NatSemi SCx200 ACCESS.bus Driver\n");
621 rc = scx200_scan_pci();
623 /* If at least one bus was created, init must succeed */
629 static void __exit scx200_acb_cleanup(void)
631 struct scx200_acb_iface *iface;
633 mutex_lock(&scx200_acb_list_mutex);
634 while ((iface = scx200_acb_list) != NULL) {
635 scx200_acb_list = iface->next;
636 mutex_unlock(&scx200_acb_list_mutex);
638 i2c_del_adapter(&iface->adapter);
641 pci_release_region(iface->pdev, iface->bar);
642 pci_dev_put(iface->pdev);
645 release_region(iface->base, 8);
648 mutex_lock(&scx200_acb_list_mutex);
650 mutex_unlock(&scx200_acb_list_mutex);
653 module_init(scx200_acb_init);
654 module_exit(scx200_acb_cleanup);