Merge git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial
[linux-2.6] / arch / powerpc / platforms / powermac / smp.c
1 /*
2  * SMP support for power macintosh.
3  *
4  * We support both the old "powersurge" SMP architecture
5  * and the current Core99 (G4 PowerMac) machines.
6  *
7  * Note that we don't support the very first rev. of
8  * Apple/DayStar 2 CPUs board, the one with the funky
9  * watchdog. Hopefully, none of these should be there except
10  * maybe internally to Apple. I should probably still add some
11  * code to detect this card though and disable SMP. --BenH.
12  *
13  * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
14  * and Ben Herrenschmidt <benh@kernel.crashing.org>.
15  *
16  * Support for DayStar quad CPU cards
17  * Copyright (C) XLR8, Inc. 1994-2000
18  *
19  *  This program is free software; you can redistribute it and/or
20  *  modify it under the terms of the GNU General Public License
21  *  as published by the Free Software Foundation; either version
22  *  2 of the License, or (at your option) any later version.
23  */
24 #include <linux/config.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/smp.h>
28 #include <linux/smp_lock.h>
29 #include <linux/interrupt.h>
30 #include <linux/kernel_stat.h>
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/spinlock.h>
34 #include <linux/errno.h>
35 #include <linux/hardirq.h>
36 #include <linux/cpu.h>
37
38 #include <asm/ptrace.h>
39 #include <asm/atomic.h>
40 #include <asm/irq.h>
41 #include <asm/page.h>
42 #include <asm/pgtable.h>
43 #include <asm/sections.h>
44 #include <asm/io.h>
45 #include <asm/prom.h>
46 #include <asm/smp.h>
47 #include <asm/machdep.h>
48 #include <asm/pmac_feature.h>
49 #include <asm/time.h>
50 #include <asm/mpic.h>
51 #include <asm/cacheflush.h>
52 #include <asm/keylargo.h>
53 #include <asm/pmac_low_i2c.h>
54
55 #undef DEBUG
56
57 #ifdef DEBUG
58 #define DBG(fmt...) udbg_printf(fmt)
59 #else
60 #define DBG(fmt...)
61 #endif
62
63 extern void __secondary_start_pmac_0(void);
64
65 #ifdef CONFIG_PPC32
66
67 /* Sync flag for HW tb sync */
68 static volatile int sec_tb_reset = 0;
69
70 /*
71  * Powersurge (old powermac SMP) support.
72  */
73
74 /* Addresses for powersurge registers */
75 #define HAMMERHEAD_BASE         0xf8000000
76 #define HHEAD_CONFIG            0x90
77 #define HHEAD_SEC_INTR          0xc0
78
79 /* register for interrupting the primary processor on the powersurge */
80 /* N.B. this is actually the ethernet ROM! */
81 #define PSURGE_PRI_INTR         0xf3019000
82
83 /* register for storing the start address for the secondary processor */
84 /* N.B. this is the PCI config space address register for the 1st bridge */
85 #define PSURGE_START            0xf2800000
86
87 /* Daystar/XLR8 4-CPU card */
88 #define PSURGE_QUAD_REG_ADDR    0xf8800000
89
90 #define PSURGE_QUAD_IRQ_SET     0
91 #define PSURGE_QUAD_IRQ_CLR     1
92 #define PSURGE_QUAD_IRQ_PRIMARY 2
93 #define PSURGE_QUAD_CKSTOP_CTL  3
94 #define PSURGE_QUAD_PRIMARY_ARB 4
95 #define PSURGE_QUAD_BOARD_ID    6
96 #define PSURGE_QUAD_WHICH_CPU   7
97 #define PSURGE_QUAD_CKSTOP_RDBK 8
98 #define PSURGE_QUAD_RESET_CTL   11
99
100 #define PSURGE_QUAD_OUT(r, v)   (out_8(quad_base + ((r) << 4) + 4, (v)))
101 #define PSURGE_QUAD_IN(r)       (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
102 #define PSURGE_QUAD_BIS(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
103 #define PSURGE_QUAD_BIC(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
104
105 /* virtual addresses for the above */
106 static volatile u8 __iomem *hhead_base;
107 static volatile u8 __iomem *quad_base;
108 static volatile u32 __iomem *psurge_pri_intr;
109 static volatile u8 __iomem *psurge_sec_intr;
110 static volatile u32 __iomem *psurge_start;
111
112 /* values for psurge_type */
113 #define PSURGE_NONE             -1
114 #define PSURGE_DUAL             0
115 #define PSURGE_QUAD_OKEE        1
116 #define PSURGE_QUAD_COTTON      2
117 #define PSURGE_QUAD_ICEGRASS    3
118
119 /* what sort of powersurge board we have */
120 static int psurge_type = PSURGE_NONE;
121
122 /*
123  * Set and clear IPIs for powersurge.
124  */
125 static inline void psurge_set_ipi(int cpu)
126 {
127         if (psurge_type == PSURGE_NONE)
128                 return;
129         if (cpu == 0)
130                 in_be32(psurge_pri_intr);
131         else if (psurge_type == PSURGE_DUAL)
132                 out_8(psurge_sec_intr, 0);
133         else
134                 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
135 }
136
137 static inline void psurge_clr_ipi(int cpu)
138 {
139         if (cpu > 0) {
140                 switch(psurge_type) {
141                 case PSURGE_DUAL:
142                         out_8(psurge_sec_intr, ~0);
143                 case PSURGE_NONE:
144                         break;
145                 default:
146                         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
147                 }
148         }
149 }
150
151 /*
152  * On powersurge (old SMP powermac architecture) we don't have
153  * separate IPIs for separate messages like openpic does.  Instead
154  * we have a bitmap for each processor, where a 1 bit means that
155  * the corresponding message is pending for that processor.
156  * Ideally each cpu's entry would be in a different cache line.
157  *  -- paulus.
158  */
159 static unsigned long psurge_smp_message[NR_CPUS];
160
161 void psurge_smp_message_recv(struct pt_regs *regs)
162 {
163         int cpu = smp_processor_id();
164         int msg;
165
166         /* clear interrupt */
167         psurge_clr_ipi(cpu);
168
169         if (num_online_cpus() < 2)
170                 return;
171
172         /* make sure there is a message there */
173         for (msg = 0; msg < 4; msg++)
174                 if (test_and_clear_bit(msg, &psurge_smp_message[cpu]))
175                         smp_message_recv(msg, regs);
176 }
177
178 irqreturn_t psurge_primary_intr(int irq, void *d, struct pt_regs *regs)
179 {
180         psurge_smp_message_recv(regs);
181         return IRQ_HANDLED;
182 }
183
184 static void smp_psurge_message_pass(int target, int msg)
185 {
186         int i;
187
188         if (num_online_cpus() < 2)
189                 return;
190
191         for (i = 0; i < NR_CPUS; i++) {
192                 if (!cpu_online(i))
193                         continue;
194                 if (target == MSG_ALL
195                     || (target == MSG_ALL_BUT_SELF && i != smp_processor_id())
196                     || target == i) {
197                         set_bit(msg, &psurge_smp_message[i]);
198                         psurge_set_ipi(i);
199                 }
200         }
201 }
202
203 /*
204  * Determine a quad card presence. We read the board ID register, we
205  * force the data bus to change to something else, and we read it again.
206  * It it's stable, then the register probably exist (ugh !)
207  */
208 static int __init psurge_quad_probe(void)
209 {
210         int type;
211         unsigned int i;
212
213         type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
214         if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
215             || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
216                 return PSURGE_DUAL;
217
218         /* looks OK, try a slightly more rigorous test */
219         /* bogus is not necessarily cacheline-aligned,
220            though I don't suppose that really matters.  -- paulus */
221         for (i = 0; i < 100; i++) {
222                 volatile u32 bogus[8];
223                 bogus[(0+i)%8] = 0x00000000;
224                 bogus[(1+i)%8] = 0x55555555;
225                 bogus[(2+i)%8] = 0xFFFFFFFF;
226                 bogus[(3+i)%8] = 0xAAAAAAAA;
227                 bogus[(4+i)%8] = 0x33333333;
228                 bogus[(5+i)%8] = 0xCCCCCCCC;
229                 bogus[(6+i)%8] = 0xCCCCCCCC;
230                 bogus[(7+i)%8] = 0x33333333;
231                 wmb();
232                 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
233                 mb();
234                 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
235                         return PSURGE_DUAL;
236         }
237         return type;
238 }
239
240 static void __init psurge_quad_init(void)
241 {
242         int procbits;
243
244         if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
245         procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
246         if (psurge_type == PSURGE_QUAD_ICEGRASS)
247                 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
248         else
249                 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
250         mdelay(33);
251         out_8(psurge_sec_intr, ~0);
252         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
253         PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
254         if (psurge_type != PSURGE_QUAD_ICEGRASS)
255                 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
256         PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
257         mdelay(33);
258         PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
259         mdelay(33);
260         PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
261         mdelay(33);
262 }
263
264 static int __init smp_psurge_probe(void)
265 {
266         int i, ncpus;
267
268         /* We don't do SMP on the PPC601 -- paulus */
269         if (PVR_VER(mfspr(SPRN_PVR)) == 1)
270                 return 1;
271
272         /*
273          * The powersurge cpu board can be used in the generation
274          * of powermacs that have a socket for an upgradeable cpu card,
275          * including the 7500, 8500, 9500, 9600.
276          * The device tree doesn't tell you if you have 2 cpus because
277          * OF doesn't know anything about the 2nd processor.
278          * Instead we look for magic bits in magic registers,
279          * in the hammerhead memory controller in the case of the
280          * dual-cpu powersurge board.  -- paulus.
281          */
282         if (find_devices("hammerhead") == NULL)
283                 return 1;
284
285         hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
286         quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
287         psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
288
289         psurge_type = psurge_quad_probe();
290         if (psurge_type != PSURGE_DUAL) {
291                 psurge_quad_init();
292                 /* All released cards using this HW design have 4 CPUs */
293                 ncpus = 4;
294         } else {
295                 iounmap(quad_base);
296                 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
297                         /* not a dual-cpu card */
298                         iounmap(hhead_base);
299                         psurge_type = PSURGE_NONE;
300                         return 1;
301                 }
302                 ncpus = 2;
303         }
304
305         psurge_start = ioremap(PSURGE_START, 4);
306         psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
307
308         /*
309          * This is necessary because OF doesn't know about the
310          * secondary cpu(s), and thus there aren't nodes in the
311          * device tree for them, and smp_setup_cpu_maps hasn't
312          * set their bits in cpu_possible_map and cpu_present_map.
313          */
314         if (ncpus > NR_CPUS)
315                 ncpus = NR_CPUS;
316         for (i = 1; i < ncpus ; ++i) {
317                 cpu_set(i, cpu_present_map);
318                 cpu_set(i, cpu_possible_map);
319                 set_hard_smp_processor_id(i, i);
320         }
321
322         if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
323
324         return ncpus;
325 }
326
327 static void __init smp_psurge_kick_cpu(int nr)
328 {
329         unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8;
330         unsigned long a;
331
332         /* may need to flush here if secondary bats aren't setup */
333         for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
334                 asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
335         asm volatile("sync");
336
337         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
338
339         out_be32(psurge_start, start);
340         mb();
341
342         psurge_set_ipi(nr);
343         udelay(10);
344         psurge_clr_ipi(nr);
345
346         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
347 }
348
349 /*
350  * With the dual-cpu powersurge board, the decrementers and timebases
351  * of both cpus are frozen after the secondary cpu is started up,
352  * until we give the secondary cpu another interrupt.  This routine
353  * uses this to get the timebases synchronized.
354  *  -- paulus.
355  */
356 static void __init psurge_dual_sync_tb(int cpu_nr)
357 {
358         int t;
359
360         set_dec(tb_ticks_per_jiffy);
361         /* XXX fixme */
362         set_tb(0, 0);
363         last_jiffy_stamp(cpu_nr) = 0;
364
365         if (cpu_nr > 0) {
366                 mb();
367                 sec_tb_reset = 1;
368                 return;
369         }
370
371         /* wait for the secondary to have reset its TB before proceeding */
372         for (t = 10000000; t > 0 && !sec_tb_reset; --t)
373                 ;
374
375         /* now interrupt the secondary, starting both TBs */
376         psurge_set_ipi(1);
377 }
378
379 static struct irqaction psurge_irqaction = {
380         .handler = psurge_primary_intr,
381         .flags = SA_INTERRUPT,
382         .mask = CPU_MASK_NONE,
383         .name = "primary IPI",
384 };
385
386 static void __init smp_psurge_setup_cpu(int cpu_nr)
387 {
388
389         if (cpu_nr == 0) {
390                 /* If we failed to start the second CPU, we should still
391                  * send it an IPI to start the timebase & DEC or we might
392                  * have them stuck.
393                  */
394                 if (num_online_cpus() < 2) {
395                         if (psurge_type == PSURGE_DUAL)
396                                 psurge_set_ipi(1);
397                         return;
398                 }
399                 /* reset the entry point so if we get another intr we won't
400                  * try to startup again */
401                 out_be32(psurge_start, 0x100);
402                 if (setup_irq(30, &psurge_irqaction))
403                         printk(KERN_ERR "Couldn't get primary IPI interrupt");
404         }
405
406         if (psurge_type == PSURGE_DUAL)
407                 psurge_dual_sync_tb(cpu_nr);
408 }
409
410 void __init smp_psurge_take_timebase(void)
411 {
412         /* Dummy implementation */
413 }
414
415 void __init smp_psurge_give_timebase(void)
416 {
417         /* Dummy implementation */
418 }
419
420 /* PowerSurge-style Macs */
421 struct smp_ops_t psurge_smp_ops = {
422         .message_pass   = smp_psurge_message_pass,
423         .probe          = smp_psurge_probe,
424         .kick_cpu       = smp_psurge_kick_cpu,
425         .setup_cpu      = smp_psurge_setup_cpu,
426         .give_timebase  = smp_psurge_give_timebase,
427         .take_timebase  = smp_psurge_take_timebase,
428 };
429 #endif /* CONFIG_PPC32 - actually powersurge support */
430
431 #ifdef CONFIG_PPC64
432 /*
433  * G5s enable/disable the timebase via an i2c-connected clock chip.
434  */
435 static struct device_node *pmac_tb_clock_chip_host;
436 static u8 pmac_tb_pulsar_addr;
437 static void (*pmac_tb_freeze)(int freeze);
438 static DEFINE_SPINLOCK(timebase_lock);
439 static unsigned long timebase;
440
441 static void smp_core99_cypress_tb_freeze(int freeze)
442 {
443         u8 data;
444         int rc;
445
446         /* Strangely, the device-tree says address is 0xd2, but darwin
447          * accesses 0xd0 ...
448          */
449         pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_combined);
450         rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
451                                0xd0 | pmac_low_i2c_read,
452                                0x81, &data, 1);
453         if (rc != 0)
454                 goto bail;
455
456         data = (data & 0xf3) | (freeze ? 0x00 : 0x0c);
457
458         pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_stdsub);
459         rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
460                                0xd0 | pmac_low_i2c_write,
461                                0x81, &data, 1);
462
463  bail:
464         if (rc != 0) {
465                 printk("Cypress Timebase %s rc: %d\n",
466                        freeze ? "freeze" : "unfreeze", rc);
467                 panic("Timebase freeze failed !\n");
468         }
469 }
470
471
472 static void smp_core99_pulsar_tb_freeze(int freeze)
473 {
474         u8 data;
475         int rc;
476
477         pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_combined);
478         rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
479                                pmac_tb_pulsar_addr | pmac_low_i2c_read,
480                                0x2e, &data, 1);
481         if (rc != 0)
482                 goto bail;
483
484         data = (data & 0x88) | (freeze ? 0x11 : 0x22);
485
486         pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_stdsub);
487         rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
488                                pmac_tb_pulsar_addr | pmac_low_i2c_write,
489                                0x2e, &data, 1);
490  bail:
491         if (rc != 0) {
492                 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n",
493                        freeze ? "freeze" : "unfreeze", rc);
494                 panic("Timebase freeze failed !\n");
495         }
496 }
497
498
499 static void smp_core99_give_timebase(void)
500 {
501         /* Open i2c bus for synchronous access */
502         if (pmac_low_i2c_open(pmac_tb_clock_chip_host, 0))
503                 panic("Can't open i2c for TB sync !\n");
504
505         spin_lock(&timebase_lock);
506         (*pmac_tb_freeze)(1);
507         mb();
508         timebase = get_tb();
509         spin_unlock(&timebase_lock);
510
511         while (timebase)
512                 barrier();
513
514         spin_lock(&timebase_lock);
515         (*pmac_tb_freeze)(0);
516         spin_unlock(&timebase_lock);
517
518         /* Close i2c bus */
519         pmac_low_i2c_close(pmac_tb_clock_chip_host);
520 }
521
522
523 static void __devinit smp_core99_take_timebase(void)
524 {
525         while (!timebase)
526                 barrier();
527         spin_lock(&timebase_lock);
528         set_tb(timebase >> 32, timebase & 0xffffffff);
529         timebase = 0;
530         spin_unlock(&timebase_lock);
531 }
532
533 static void __init smp_core99_setup(int ncpus)
534 {
535         struct device_node *cc = NULL;  
536         struct device_node *p;
537         u32 *reg;
538         int ok;
539
540         /* HW sync only on these platforms */
541         if (!machine_is_compatible("PowerMac7,2") &&
542             !machine_is_compatible("PowerMac7,3") &&
543             !machine_is_compatible("RackMac3,1"))
544                 return;
545
546         /* Look for the clock chip */
547         while ((cc = of_find_node_by_name(cc, "i2c-hwclock")) != NULL) {
548                 p = of_get_parent(cc);
549                 ok = p && device_is_compatible(p, "uni-n-i2c");
550                 of_node_put(p);
551                 if (!ok)
552                         continue;
553
554                 reg = (u32 *)get_property(cc, "reg", NULL);
555                 if (reg == NULL)
556                         continue;
557
558                 switch (*reg) {
559                 case 0xd2:
560                         if (device_is_compatible(cc, "pulsar-legacy-slewing")) {
561                                 pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
562                                 pmac_tb_pulsar_addr = 0xd2;
563                                 printk(KERN_INFO "Timebase clock is Pulsar chip\n");
564                         } else if (device_is_compatible(cc, "cy28508")) {
565                                 pmac_tb_freeze = smp_core99_cypress_tb_freeze;
566                                 printk(KERN_INFO "Timebase clock is Cypress chip\n");
567                         }
568                         break;
569                 case 0xd4:
570                         pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
571                         pmac_tb_pulsar_addr = 0xd4;
572                         printk(KERN_INFO "Timebase clock is Pulsar chip\n");
573                         break;
574                 }
575                 if (pmac_tb_freeze != NULL) {
576                         pmac_tb_clock_chip_host = of_get_parent(cc);
577                         of_node_put(cc);
578                         break;
579                 }
580         }
581         if (pmac_tb_freeze == NULL) {
582                 smp_ops->give_timebase = smp_generic_give_timebase;
583                 smp_ops->take_timebase = smp_generic_take_timebase;
584         }
585 }
586
587 /* nothing to do here, caches are already set up by service processor */
588 static inline void __devinit core99_init_caches(int cpu)
589 {
590 }
591
592 #else /* CONFIG_PPC64 */
593
594 /*
595  * SMP G4 powermacs use a GPIO to enable/disable the timebase.
596  */
597
598 static unsigned int core99_tb_gpio;     /* Timebase freeze GPIO */
599
600 static unsigned int pri_tb_hi, pri_tb_lo;
601 static unsigned int pri_tb_stamp;
602
603 /* not __init, called in sleep/wakeup code */
604 void smp_core99_give_timebase(void)
605 {
606         unsigned long flags;
607         unsigned int t;
608
609         /* wait for the secondary to be in take_timebase */
610         for (t = 100000; t > 0 && !sec_tb_reset; --t)
611                 udelay(10);
612         if (!sec_tb_reset) {
613                 printk(KERN_WARNING "Timeout waiting sync on second CPU\n");
614                 return;
615         }
616
617         /* freeze the timebase and read it */
618         /* disable interrupts so the timebase is disabled for the
619            shortest possible time */
620         local_irq_save(flags);
621         pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4);
622         pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
623         mb();
624         pri_tb_hi = get_tbu();
625         pri_tb_lo = get_tbl();
626         pri_tb_stamp = last_jiffy_stamp(smp_processor_id());
627         mb();
628
629         /* tell the secondary we're ready */
630         sec_tb_reset = 2;
631         mb();
632
633         /* wait for the secondary to have taken it */
634         for (t = 100000; t > 0 && sec_tb_reset; --t)
635                 udelay(10);
636         if (sec_tb_reset)
637                 /* XXX BUG_ON here? */
638                 printk(KERN_WARNING "Timeout waiting sync(2) on second CPU\n");
639
640         /* Now, restart the timebase by leaving the GPIO to an open collector */
641         pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);
642         pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
643         local_irq_restore(flags);
644 }
645
646 /* not __init, called in sleep/wakeup code */
647 void smp_core99_take_timebase(void)
648 {
649         unsigned long flags;
650
651         /* tell the primary we're here */
652         sec_tb_reset = 1;
653         mb();
654
655         /* wait for the primary to set pri_tb_hi/lo */
656         while (sec_tb_reset < 2)
657                 mb();
658
659         /* set our stuff the same as the primary */
660         local_irq_save(flags);
661         set_dec(1);
662         set_tb(pri_tb_hi, pri_tb_lo);
663         last_jiffy_stamp(smp_processor_id()) = pri_tb_stamp;
664         mb();
665
666         /* tell the primary we're done */
667         sec_tb_reset = 0;
668         mb();
669         local_irq_restore(flags);
670 }
671
672 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
673 volatile static long int core99_l2_cache;
674 volatile static long int core99_l3_cache;
675
676 static void __devinit core99_init_caches(int cpu)
677 {
678         if (!cpu_has_feature(CPU_FTR_L2CR))
679                 return;
680
681         if (cpu == 0) {
682                 core99_l2_cache = _get_L2CR();
683                 printk("CPU0: L2CR is %lx\n", core99_l2_cache);
684         } else {
685                 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
686                 _set_L2CR(0);
687                 _set_L2CR(core99_l2_cache);
688                 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
689         }
690
691         if (!cpu_has_feature(CPU_FTR_L3CR))
692                 return;
693
694         if (cpu == 0){
695                 core99_l3_cache = _get_L3CR();
696                 printk("CPU0: L3CR is %lx\n", core99_l3_cache);
697         } else {
698                 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
699                 _set_L3CR(0);
700                 _set_L3CR(core99_l3_cache);
701                 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
702         }
703 }
704
705 static void __init smp_core99_setup(int ncpus)
706 {
707         struct device_node *cpu;
708         u32 *tbprop = NULL;
709         int i;
710
711         core99_tb_gpio = KL_GPIO_TB_ENABLE;     /* default value */
712         cpu = of_find_node_by_type(NULL, "cpu");
713         if (cpu != NULL) {
714                 tbprop = (u32 *)get_property(cpu, "timebase-enable", NULL);
715                 if (tbprop)
716                         core99_tb_gpio = *tbprop;
717                 of_node_put(cpu);
718         }
719
720         /* XXX should get this from reg properties */
721         for (i = 1; i < ncpus; ++i)
722                 smp_hw_index[i] = i;
723         powersave_nap = 0;
724 }
725 #endif
726
727 static int __init smp_core99_probe(void)
728 {
729         struct device_node *cpus;
730         int ncpus = 0;
731
732         if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
733
734         /* Count CPUs in the device-tree */
735         for (cpus = NULL; (cpus = of_find_node_by_type(cpus, "cpu")) != NULL;)
736                 ++ncpus;
737
738         printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus);
739
740         /* Nothing more to do if less than 2 of them */
741         if (ncpus <= 1)
742                 return 1;
743
744         smp_core99_setup(ncpus);
745         mpic_request_ipis();
746         core99_init_caches(0);
747
748         return ncpus;
749 }
750
751 static void __devinit smp_core99_kick_cpu(int nr)
752 {
753         unsigned int save_vector;
754         unsigned long new_vector;
755         unsigned long flags;
756         volatile unsigned int *vector
757                  = ((volatile unsigned int *)(KERNELBASE+0x100));
758
759         if (nr < 0 || nr > 3)
760                 return;
761         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu", 0x346);
762
763         local_irq_save(flags);
764         local_irq_disable();
765
766         /* Save reset vector */
767         save_vector = *vector;
768
769         /* Setup fake reset vector that does    
770          *   b __secondary_start_pmac_0 + nr*8 - KERNELBASE
771          */
772         new_vector = (unsigned long) __secondary_start_pmac_0 + nr * 8;
773         *vector = 0x48000002 + new_vector - KERNELBASE;
774
775         /* flush data cache and inval instruction cache */
776         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
777
778         /* Put some life in our friend */
779         pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
780
781         /* FIXME: We wait a bit for the CPU to take the exception, I should
782          * instead wait for the entry code to set something for me. Well,
783          * ideally, all that crap will be done in prom.c and the CPU left
784          * in a RAM-based wait loop like CHRP.
785          */
786         mdelay(1);
787
788         /* Restore our exception vector */
789         *vector = save_vector;
790         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
791
792         local_irq_restore(flags);
793         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
794 }
795
796 static void __devinit smp_core99_setup_cpu(int cpu_nr)
797 {
798         /* Setup L2/L3 */
799         if (cpu_nr != 0)
800                 core99_init_caches(cpu_nr);
801
802         /* Setup openpic */
803         mpic_setup_this_cpu();
804
805         if (cpu_nr == 0) {
806 #ifdef CONFIG_POWER4
807                 extern void g5_phy_disable_cpu1(void);
808
809                 /* If we didn't start the second CPU, we must take
810                  * it off the bus
811                  */
812                 if (machine_is_compatible("MacRISC4") &&
813                     num_online_cpus() < 2)              
814                         g5_phy_disable_cpu1();
815 #endif /* CONFIG_POWER4 */
816                 if (ppc_md.progress) ppc_md.progress("core99_setup_cpu 0 done", 0x349);
817         }
818 }
819
820
821 #if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32)
822
823 int smp_core99_cpu_disable(void)
824 {
825         cpu_clear(smp_processor_id(), cpu_online_map);
826
827         /* XXX reset cpu affinity here */
828         mpic_cpu_set_priority(0xf);
829         asm volatile("mtdec %0" : : "r" (0x7fffffff));
830         mb();
831         udelay(20);
832         asm volatile("mtdec %0" : : "r" (0x7fffffff));
833         return 0;
834 }
835
836 extern void low_cpu_die(void) __attribute__((noreturn)); /* in sleep.S */
837 static int cpu_dead[NR_CPUS];
838
839 void cpu_die(void)
840 {
841         local_irq_disable();
842         cpu_dead[smp_processor_id()] = 1;
843         mb();
844         low_cpu_die();
845 }
846
847 void smp_core99_cpu_die(unsigned int cpu)
848 {
849         int timeout;
850
851         timeout = 1000;
852         while (!cpu_dead[cpu]) {
853                 if (--timeout == 0) {
854                         printk("CPU %u refused to die!\n", cpu);
855                         break;
856                 }
857                 msleep(1);
858         }
859         cpu_dead[cpu] = 0;
860 }
861
862 #endif
863
864 /* Core99 Macs (dual G4s and G5s) */
865 struct smp_ops_t core99_smp_ops = {
866         .message_pass   = smp_mpic_message_pass,
867         .probe          = smp_core99_probe,
868         .kick_cpu       = smp_core99_kick_cpu,
869         .setup_cpu      = smp_core99_setup_cpu,
870         .give_timebase  = smp_core99_give_timebase,
871         .take_timebase  = smp_core99_take_timebase,
872 #if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32)
873         .cpu_disable    = smp_core99_cpu_disable,
874         .cpu_die        = smp_core99_cpu_die,
875 #endif
876 };