2 * linux/drivers/ide/pci/slc90e66.c Version 0.13 December 30, 2006
4 * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2006 MontaVista Software, Inc. <source@mvista.com>
7 * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
8 * but this keeps the ISA-Bridge and slots alive.
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/hdreg.h>
18 #include <linux/ide.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
24 static u8 slc90e66_ratemask (ide_drive_t *drive)
28 if (!eighty_ninty_three(drive))
29 mode = min_t(u8, mode, 1);
33 static u8 slc90e66_dma_2_pio (u8 xfer_rate) {
61 * Based on settings done by AMI BIOS
62 * (might be useful if drive is not registered in CMOS for any reason).
64 static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio)
66 ide_hwif_t *hwif = HWIF(drive);
67 struct pci_dev *dev = hwif->pci_dev;
68 int is_slave = drive->dn & 1;
69 int master_port = hwif->channel ? 0x42 : 0x40;
70 int slave_port = 0x44;
76 static const u8 timings[][2]= {
83 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
84 spin_lock_irqsave(&ide_lock, flags);
85 pci_read_config_word(dev, master_port, &master_data);
88 control |= 1; /* Programmable timing on */
89 if (drive->media == ide_disk)
90 control |= 4; /* Prefetch, post write */
92 control |= 2; /* IORDY */
94 master_data |= 0x4000;
95 master_data &= ~0x0070;
97 /* enable PPE, IE and TIME */
98 master_data = master_data | (control << 4);
100 pci_read_config_byte(dev, slave_port, &slave_data);
101 slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
102 slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
104 master_data &= ~0x3307;
106 /* enable PPE, IE and TIME */
107 master_data = master_data | control;
109 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
111 pci_write_config_word(dev, master_port, master_data);
113 pci_write_config_byte(dev, slave_port, slave_data);
114 spin_unlock_irqrestore(&ide_lock, flags);
117 static int slc90e66_tune_chipset (ide_drive_t *drive, u8 xferspeed)
119 ide_hwif_t *hwif = HWIF(drive);
120 struct pci_dev *dev = hwif->pci_dev;
121 u8 maslave = hwif->channel ? 0x42 : 0x40;
122 u8 speed = ide_rate_filter(slc90e66_ratemask(drive), xferspeed);
123 int sitre = 0, a_speed = 7 << (drive->dn * 4);
124 int u_speed = 0, u_flag = 1 << drive->dn;
125 u16 reg4042, reg44, reg48, reg4a;
127 pci_read_config_word(dev, maslave, ®4042);
128 sitre = (reg4042 & 0x4000) ? 1 : 0;
129 pci_read_config_word(dev, 0x44, ®44);
130 pci_read_config_word(dev, 0x48, ®48);
131 pci_read_config_word(dev, 0x4a, ®4a);
134 case XFER_UDMA_4: u_speed = 4 << (drive->dn * 4); break;
135 case XFER_UDMA_3: u_speed = 3 << (drive->dn * 4); break;
136 case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
137 case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
138 case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
141 case XFER_SW_DMA_2: break;
145 case XFER_PIO_0: break;
149 if (speed >= XFER_UDMA_0) {
150 if (!(reg48 & u_flag))
151 pci_write_config_word(dev, 0x48, reg48|u_flag);
152 /* FIXME: (reg4a & a_speed) ? */
153 if ((reg4a & u_speed) != u_speed) {
154 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
155 pci_read_config_word(dev, 0x4a, ®4a);
156 pci_write_config_word(dev, 0x4a, reg4a|u_speed);
160 pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
162 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
165 slc90e66_tune_drive(drive, slc90e66_dma_2_pio(speed));
166 return (ide_config_drive_speed(drive, speed));
169 static int slc90e66_config_drive_for_dma (ide_drive_t *drive)
171 u8 speed = ide_dma_speed(drive, slc90e66_ratemask(drive));
176 (void) slc90e66_tune_chipset(drive, speed);
177 return ide_dma_enable(drive);
180 static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive)
182 ide_hwif_t *hwif = HWIF(drive);
183 struct hd_driveid *id = drive->id;
185 drive->init_speed = 0;
187 if ((id->capability & 1) && drive->autodma) {
189 if (ide_use_dma(drive) && slc90e66_config_drive_for_dma(drive))
190 return hwif->ide_dma_on(drive);
194 } else if ((id->capability & 8) || (id->field_valid & 2)) {
196 (void) hwif->speedproc(drive, XFER_PIO_0 +
197 ide_get_best_pio_mode(drive, 255, 4, NULL));
198 return hwif->ide_dma_off_quietly(drive);
200 /* IORDY not supported */
204 static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
207 u8 mask = hwif->channel ? 0x01 : 0x02; /* bit0:Primary */
212 hwif->irq = hwif->channel ? 15 : 14;
214 hwif->speedproc = &slc90e66_tune_chipset;
215 hwif->tuneproc = &slc90e66_tune_drive;
217 pci_read_config_byte(hwif->pci_dev, 0x47, ®47);
219 if (!hwif->dma_base) {
220 hwif->drives[0].autotune = 1;
221 hwif->drives[1].autotune = 1;
226 hwif->ultra_mask = 0x1f;
227 hwif->mwdma_mask = 0x06;
228 hwif->swdma_mask = 0x04;
230 if (!hwif->udma_four) {
231 /* bit[0(1)]: 0:80, 1:40 */
232 hwif->udma_four = (reg47 & mask) ? 0 : 1;
235 hwif->ide_dma_check = &slc90e66_config_drive_xfer_rate;
239 hwif->drives[0].autodma = hwif->autodma;
240 hwif->drives[1].autodma = hwif->autodma;
243 static ide_pci_device_t slc90e66_chipset __devinitdata = {
245 .init_hwif = init_hwif_slc90e66,
248 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
249 .bootable = ON_BOARD,
252 static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
254 return ide_setup_pci_device(dev, &slc90e66_chipset);
257 static struct pci_device_id slc90e66_pci_tbl[] = {
258 { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0},
261 MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
263 static struct pci_driver driver = {
264 .name = "SLC90e66_IDE",
265 .id_table = slc90e66_pci_tbl,
266 .probe = slc90e66_init_one,
269 static int __init slc90e66_ide_init(void)
271 return ide_pci_register_driver(&driver);
274 module_init(slc90e66_ide_init);
276 MODULE_AUTHOR("Andre Hedrick");
277 MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
278 MODULE_LICENSE("GPL");