2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
36 #include "rt2x00pci.h"
37 #include "rt2400pci.h"
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
52 static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, ®);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
61 udelay(REGISTER_BUSY_DELAY);
67 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
68 const unsigned int word, const u8 value)
73 * Wait until the BBP becomes ready.
75 reg = rt2400pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
82 * Write the data into the BBP.
85 rt2x00_set_field32(®, BBPCSR_VALUE, value);
86 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1);
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
93 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
94 const unsigned int word, u8 *value)
99 * Wait until the BBP becomes ready.
101 reg = rt2400pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
108 * Write the request into the BBP.
111 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0);
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
118 * Wait until the BBP becomes ready.
120 reg = rt2400pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
130 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
131 const unsigned int word, const u32 value)
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, ®);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
143 udelay(REGISTER_BUSY_DELAY);
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
151 rt2x00_set_field32(®, RFCSR_VALUE, value);
152 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(®, RFCSR_BUSY, 1);
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
160 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
165 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
175 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
180 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
191 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
193 static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
194 const unsigned int word, u32 *data)
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
199 static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, u32 data)
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
205 static const struct rt2x00debug rt2400pci_rt2x00debug = {
206 .owner = THIS_MODULE,
208 .read = rt2400pci_read_csr,
209 .write = rt2400pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
220 .read = rt2400pci_bbp_read,
221 .write = rt2400pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
226 .read = rt2x00_rf_read,
227 .write = rt2400pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
234 #ifdef CONFIG_RT2400PCI_RFKILL
235 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
243 #define rt2400pci_rfkill_poll NULL
244 #endif /* CONFIG_RT2400PCI_RFKILL */
247 * Configuration handlers.
249 static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
252 rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
253 (2 * sizeof(__le32)));
256 static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev,
259 rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
260 (2 * sizeof(__le32)));
263 static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
268 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
271 * Enable beacon config
273 rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®);
274 rt2x00_set_field32(®, BCNCSR1_PRELOAD,
275 PREAMBLE + get_duration(IEEE80211_HEADER, 20));
276 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
279 * Enable synchronisation.
281 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
282 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
283 rt2x00_set_field32(®, CSR14_TBCN, 1);
284 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
285 rt2x00_set_field32(®, CSR14_TSF_SYNC, tsf_sync);
286 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
289 static void rt2400pci_config_preamble(struct rt2x00_dev *rt2x00dev,
290 const int short_preamble,
291 const int ack_timeout,
292 const int ack_consume_time)
298 * When short preamble is enabled, we should set bit 0x08
300 preamble_mask = short_preamble << 3;
302 rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
303 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, ack_timeout);
304 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
305 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
307 rt2x00pci_register_read(rt2x00dev, ARCSR2, ®);
308 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00 | preamble_mask);
309 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
310 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
311 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
313 rt2x00pci_register_read(rt2x00dev, ARCSR3, ®);
314 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask);
315 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
316 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
317 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
319 rt2x00pci_register_read(rt2x00dev, ARCSR4, ®);
320 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask);
321 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
322 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
323 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
325 rt2x00pci_register_read(rt2x00dev, ARCSR5, ®);
326 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask);
327 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
328 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
329 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
332 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
333 const int basic_rate_mask)
335 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
338 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
339 struct rf_channel *rf)
342 * Switch on tuning bits.
344 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
345 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
347 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
348 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
349 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
352 * RF2420 chipset don't need any additional actions.
354 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
358 * For the RT2421 chipsets we need to write an invalid
359 * reference clock rate to activate auto_tune.
360 * After that we set the value back to the correct channel.
362 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
363 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
364 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
368 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
369 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
370 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
375 * Switch off tuning bits.
377 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
378 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
380 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
381 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
384 * Clear false CRC during channel switch.
386 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
389 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
391 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
394 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
395 struct antenna_setup *ant)
400 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
401 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
404 * Configure the TX antenna.
407 case ANTENNA_HW_DIVERSITY:
408 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
411 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
413 case ANTENNA_SW_DIVERSITY:
415 * NOTE: We should never come here because rt2x00lib is
416 * supposed to catch this and send us the correct antenna
417 * explicitely. However we are nog going to bug about this.
418 * Instead, just default to antenna B.
421 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
426 * Configure the RX antenna.
429 case ANTENNA_HW_DIVERSITY:
430 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
433 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
435 case ANTENNA_SW_DIVERSITY:
437 * NOTE: We should never come here because rt2x00lib is
438 * supposed to catch this and send us the correct antenna
439 * explicitely. However we are nog going to bug about this.
440 * Instead, just default to antenna B.
443 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
447 rt2400pci_bbp_write(rt2x00dev, 4, r4);
448 rt2400pci_bbp_write(rt2x00dev, 1, r1);
451 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
452 struct rt2x00lib_conf *libconf)
456 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
457 rt2x00_set_field32(®, CSR11_SLOT_TIME, libconf->slot_time);
458 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
460 rt2x00pci_register_read(rt2x00dev, CSR18, ®);
461 rt2x00_set_field32(®, CSR18_SIFS, libconf->sifs);
462 rt2x00_set_field32(®, CSR18_PIFS, libconf->pifs);
463 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
465 rt2x00pci_register_read(rt2x00dev, CSR19, ®);
466 rt2x00_set_field32(®, CSR19_DIFS, libconf->difs);
467 rt2x00_set_field32(®, CSR19_EIFS, libconf->eifs);
468 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
470 rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
471 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
472 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1);
473 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
475 rt2x00pci_register_read(rt2x00dev, CSR12, ®);
476 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL,
477 libconf->conf->beacon_int * 16);
478 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION,
479 libconf->conf->beacon_int * 16);
480 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
483 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
484 const unsigned int flags,
485 struct rt2x00lib_conf *libconf)
487 if (flags & CONFIG_UPDATE_PHYMODE)
488 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
489 if (flags & CONFIG_UPDATE_CHANNEL)
490 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
491 if (flags & CONFIG_UPDATE_TXPOWER)
492 rt2400pci_config_txpower(rt2x00dev,
493 libconf->conf->power_level);
494 if (flags & CONFIG_UPDATE_ANTENNA)
495 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
496 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
497 rt2400pci_config_duration(rt2x00dev, libconf);
500 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
501 struct ieee80211_tx_queue_params *params)
505 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
506 rt2x00_set_field32(®, CSR11_CWMIN, params->cw_min);
507 rt2x00_set_field32(®, CSR11_CWMAX, params->cw_max);
508 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
514 static void rt2400pci_enable_led(struct rt2x00_dev *rt2x00dev)
518 rt2x00pci_register_read(rt2x00dev, LEDCSR, ®);
520 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, 70);
521 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, 30);
522 rt2x00_set_field32(®, LEDCSR_LINK,
523 (rt2x00dev->led_mode != LED_MODE_ASUS));
524 rt2x00_set_field32(®, LEDCSR_ACTIVITY,
525 (rt2x00dev->led_mode != LED_MODE_TXRX_ACTIVITY));
526 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
529 static void rt2400pci_disable_led(struct rt2x00_dev *rt2x00dev)
533 rt2x00pci_register_read(rt2x00dev, LEDCSR, ®);
534 rt2x00_set_field32(®, LEDCSR_LINK, 0);
535 rt2x00_set_field32(®, LEDCSR_ACTIVITY, 0);
536 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
542 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
543 struct link_qual *qual)
549 * Update FCS error count from register.
551 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
552 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
555 * Update False CCA count from register.
557 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
558 qual->false_cca = bbp;
561 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
563 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
564 rt2x00dev->link.vgc_level = 0x08;
567 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
572 * The link tuner should not run longer then 60 seconds,
573 * and should run once every 2 seconds.
575 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
579 * Base r13 link tuning on the false cca count.
581 rt2400pci_bbp_read(rt2x00dev, 13, ®);
583 if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
584 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
585 rt2x00dev->link.vgc_level = reg;
586 } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
587 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
588 rt2x00dev->link.vgc_level = reg;
593 * Initialization functions.
595 static void rt2400pci_init_rxring(struct rt2x00_dev *rt2x00dev)
597 struct data_ring *ring = rt2x00dev->rx;
602 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
604 for (i = 0; i < ring->stats.limit; i++) {
605 rxd = ring->entry[i].priv;
607 rt2x00_desc_read(rxd, 2, &word);
608 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
610 rt2x00_desc_write(rxd, 2, word);
612 rt2x00_desc_read(rxd, 1, &word);
613 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
614 ring->entry[i].data_dma);
615 rt2x00_desc_write(rxd, 1, word);
617 rt2x00_desc_read(rxd, 0, &word);
618 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
619 rt2x00_desc_write(rxd, 0, word);
622 rt2x00_ring_index_clear(rt2x00dev->rx);
625 static void rt2400pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
627 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
632 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
634 for (i = 0; i < ring->stats.limit; i++) {
635 txd = ring->entry[i].priv;
637 rt2x00_desc_read(txd, 1, &word);
638 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
639 ring->entry[i].data_dma);
640 rt2x00_desc_write(txd, 1, word);
642 rt2x00_desc_read(txd, 2, &word);
643 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
645 rt2x00_desc_write(txd, 2, word);
647 rt2x00_desc_read(txd, 0, &word);
648 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
649 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
650 rt2x00_desc_write(txd, 0, word);
653 rt2x00_ring_index_clear(ring);
656 static int rt2400pci_init_rings(struct rt2x00_dev *rt2x00dev)
663 rt2400pci_init_rxring(rt2x00dev);
664 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
665 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
666 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
667 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
670 * Initialize registers.
672 rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
673 rt2x00_set_field32(®, TXCSR2_TXD_SIZE,
674 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
675 rt2x00_set_field32(®, TXCSR2_NUM_TXD,
676 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
677 rt2x00_set_field32(®, TXCSR2_NUM_ATIM,
678 rt2x00dev->bcn[1].stats.limit);
679 rt2x00_set_field32(®, TXCSR2_NUM_PRIO,
680 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
681 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
683 rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
684 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
685 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
686 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
688 rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
689 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
690 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
691 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
693 rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
694 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
695 rt2x00dev->bcn[1].data_dma);
696 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
698 rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
699 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
700 rt2x00dev->bcn[0].data_dma);
701 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
703 rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
704 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
705 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
706 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
708 rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
709 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER,
710 rt2x00dev->rx->data_dma);
711 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
716 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
720 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
721 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
722 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
723 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
725 rt2x00pci_register_read(rt2x00dev, TIMECSR, ®);
726 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33);
727 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63);
728 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0);
729 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
731 rt2x00pci_register_read(rt2x00dev, CSR9, ®);
732 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT,
733 (rt2x00dev->rx->data_size / 128));
734 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
736 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
738 rt2x00pci_register_read(rt2x00dev, ARCSR0, ®);
739 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA0, 133);
740 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID0, 134);
741 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA1, 136);
742 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID1, 135);
743 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
745 rt2x00pci_register_read(rt2x00dev, RXCSR3, ®);
746 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 3); /* Tx power.*/
747 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1);
748 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 32); /* Signal */
749 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1);
750 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 36); /* Rssi */
751 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1);
752 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
754 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
756 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
759 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
760 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
762 rt2x00pci_register_read(rt2x00dev, MACCSR2, ®);
763 rt2x00_set_field32(®, MACCSR2_DELAY, 64);
764 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
766 rt2x00pci_register_read(rt2x00dev, RALINKCSR, ®);
767 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17);
768 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 154);
769 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0);
770 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 154);
771 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
773 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
774 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1);
775 rt2x00_set_field32(®, CSR1_BBP_RESET, 0);
776 rt2x00_set_field32(®, CSR1_HOST_READY, 0);
777 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
779 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
780 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0);
781 rt2x00_set_field32(®, CSR1_HOST_READY, 1);
782 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
785 * We must clear the FCS and FIFO error count.
786 * These registers are cleared on read,
787 * so we may pass a useless variable to store the value.
789 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
790 rt2x00pci_register_read(rt2x00dev, CNT4, ®);
795 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
802 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
803 rt2400pci_bbp_read(rt2x00dev, 0, &value);
804 if ((value != 0xff) && (value != 0x00))
805 goto continue_csr_init;
806 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
807 udelay(REGISTER_BUSY_DELAY);
810 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
814 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
815 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
816 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
817 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
818 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
819 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
820 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
821 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
822 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
823 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
824 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
825 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
826 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
827 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
829 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
830 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
831 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
833 if (eeprom != 0xffff && eeprom != 0x0000) {
834 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
835 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
836 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
838 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
841 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
847 * Device state switch handlers.
849 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
850 enum dev_state state)
854 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
855 rt2x00_set_field32(®, RXCSR0_DISABLE_RX,
856 state == STATE_RADIO_RX_OFF);
857 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
860 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
861 enum dev_state state)
863 int mask = (state == STATE_RADIO_IRQ_OFF);
867 * When interrupts are being enabled, the interrupt registers
868 * should clear the register to assure a clean state.
870 if (state == STATE_RADIO_IRQ_ON) {
871 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
872 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
876 * Only toggle the interrupts bits we are going to use.
877 * Non-checked interrupt bits are disabled by default.
879 rt2x00pci_register_read(rt2x00dev, CSR8, ®);
880 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask);
881 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask);
882 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask);
883 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask);
884 rt2x00_set_field32(®, CSR8_RXDONE, mask);
885 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
888 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
891 * Initialize all registers.
893 if (rt2400pci_init_rings(rt2x00dev) ||
894 rt2400pci_init_registers(rt2x00dev) ||
895 rt2400pci_init_bbp(rt2x00dev)) {
896 ERROR(rt2x00dev, "Register initialization failed.\n");
903 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
908 rt2400pci_enable_led(rt2x00dev);
913 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
920 rt2400pci_disable_led(rt2x00dev);
922 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
925 * Disable synchronisation.
927 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
932 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
933 rt2x00_set_field32(®, TXCSR0_ABORT, 1);
934 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
937 * Disable interrupts.
939 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
942 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
943 enum dev_state state)
951 put_to_sleep = (state != STATE_AWAKE);
953 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
954 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1);
955 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state);
956 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state);
957 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
958 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
961 * Device is not guaranteed to be in the requested state yet.
962 * We must wait until the register indicates that the
963 * device has entered the correct state.
965 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
966 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
967 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
968 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
969 if (bbp_state == state && rf_state == state)
974 NOTICE(rt2x00dev, "Device failed to enter state %d, "
975 "current device state: bbp %d and rf %d.\n",
976 state, bbp_state, rf_state);
981 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
982 enum dev_state state)
988 retval = rt2400pci_enable_radio(rt2x00dev);
990 case STATE_RADIO_OFF:
991 rt2400pci_disable_radio(rt2x00dev);
993 case STATE_RADIO_RX_ON:
994 case STATE_RADIO_RX_OFF:
995 rt2400pci_toggle_rx(rt2x00dev, state);
997 case STATE_DEEP_SLEEP:
1001 retval = rt2400pci_set_state(rt2x00dev, state);
1012 * TX descriptor initialization
1014 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1016 struct txdata_entry_desc *desc,
1017 struct ieee80211_hdr *ieee80211hdr,
1018 unsigned int length,
1019 struct ieee80211_tx_control *control)
1024 * Start writing the descriptor words.
1026 rt2x00_desc_read(txd, 2, &word);
1027 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, length);
1028 rt2x00_desc_write(txd, 2, word);
1030 rt2x00_desc_read(txd, 3, &word);
1031 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, desc->signal);
1032 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1033 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1034 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, desc->service);
1035 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1036 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1037 rt2x00_desc_write(txd, 3, word);
1039 rt2x00_desc_read(txd, 4, &word);
1040 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, desc->length_low);
1041 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1042 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1043 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, desc->length_high);
1044 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1045 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1046 rt2x00_desc_write(txd, 4, word);
1048 rt2x00_desc_read(txd, 0, &word);
1049 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1050 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1051 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1052 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1053 rt2x00_set_field32(&word, TXD_W0_ACK,
1054 test_bit(ENTRY_TXD_ACK, &desc->flags));
1055 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1056 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1057 rt2x00_set_field32(&word, TXD_W0_RTS,
1058 test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
1059 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1060 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1062 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1063 rt2x00_desc_write(txd, 0, word);
1067 * TX data initialization
1069 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1074 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1075 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
1076 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1077 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
1078 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1083 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
1084 rt2x00_set_field32(®, TXCSR0_KICK_PRIO,
1085 (queue == IEEE80211_TX_QUEUE_DATA0));
1086 rt2x00_set_field32(®, TXCSR0_KICK_TX,
1087 (queue == IEEE80211_TX_QUEUE_DATA1));
1088 rt2x00_set_field32(®, TXCSR0_KICK_ATIM,
1089 (queue == IEEE80211_TX_QUEUE_AFTER_BEACON));
1090 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1094 * RX control handlers
1096 static void rt2400pci_fill_rxdone(struct data_entry *entry,
1097 struct rxdata_entry_desc *desc)
1099 __le32 *rxd = entry->priv;
1103 rt2x00_desc_read(rxd, 0, &word0);
1104 rt2x00_desc_read(rxd, 2, &word2);
1107 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1108 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1109 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1110 desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1113 * Obtain the status about this packet.
1115 desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1116 desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1117 entry->ring->rt2x00dev->rssi_offset;
1119 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1123 * Interrupt functions.
1125 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1127 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1128 struct data_entry *entry;
1134 while (!rt2x00_ring_empty(ring)) {
1135 entry = rt2x00_get_data_entry_done(ring);
1137 rt2x00_desc_read(txd, 0, &word);
1139 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1140 !rt2x00_get_field32(word, TXD_W0_VALID))
1144 * Obtain the status about this packet.
1146 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1147 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1149 rt2x00pci_txdone(rt2x00dev, entry, tx_status, retry);
1153 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1155 struct rt2x00_dev *rt2x00dev = dev_instance;
1159 * Get the interrupt sources & saved to local variable.
1160 * Write register value back to clear pending interrupts.
1162 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
1163 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1168 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1172 * Handle interrupts, walk through all bits
1173 * and run the tasks, the bits are checked in order of
1178 * 1 - Beacon timer expired interrupt.
1180 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1181 rt2x00lib_beacondone(rt2x00dev);
1184 * 2 - Rx ring done interrupt.
1186 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1187 rt2x00pci_rxdone(rt2x00dev);
1190 * 3 - Atim ring transmit done interrupt.
1192 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1193 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1196 * 4 - Priority ring transmit done interrupt.
1198 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1199 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1202 * 5 - Tx ring transmit done interrupt.
1204 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1205 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1211 * Device probe functions.
1213 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1215 struct eeprom_93cx6 eeprom;
1220 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
1222 eeprom.data = rt2x00dev;
1223 eeprom.register_read = rt2400pci_eepromregister_read;
1224 eeprom.register_write = rt2400pci_eepromregister_write;
1225 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1226 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1227 eeprom.reg_data_in = 0;
1228 eeprom.reg_data_out = 0;
1229 eeprom.reg_data_clock = 0;
1230 eeprom.reg_chip_select = 0;
1232 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1233 EEPROM_SIZE / sizeof(u16));
1236 * Start validation of the data that has been read.
1238 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1239 if (!is_valid_ether_addr(mac)) {
1240 DECLARE_MAC_BUF(macbuf);
1242 random_ether_addr(mac);
1243 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1246 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1247 if (word == 0xffff) {
1248 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1255 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1262 * Read EEPROM word for configuration.
1264 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1267 * Identify RF chipset.
1269 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1270 rt2x00pci_register_read(rt2x00dev, CSR0, ®);
1271 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1273 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1274 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1275 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1280 * Identify default antenna configuration.
1282 rt2x00dev->default_ant.tx =
1283 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1284 rt2x00dev->default_ant.rx =
1285 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1288 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1289 * I am not 100% sure about this, but the legacy drivers do not
1290 * indicate antenna swapping in software is required when
1291 * diversity is enabled.
1293 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1294 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1295 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1296 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1299 * Store led mode, for correct led behaviour.
1301 rt2x00dev->led_mode =
1302 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1305 * Detect if this device has an hardware controlled radio.
1307 #ifdef CONFIG_RT2400PCI_RFKILL
1308 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1309 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1310 #endif /* CONFIG_RT2400PCI_RFKILL */
1313 * Check if the BBP tuning should be enabled.
1315 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1316 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1322 * RF value list for RF2420 & RF2421
1325 static const struct rf_channel rf_vals_bg[] = {
1326 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1327 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1328 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1329 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1330 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1331 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1332 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1333 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1334 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1335 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1336 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1337 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1338 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1339 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1342 static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1344 struct hw_mode_spec *spec = &rt2x00dev->spec;
1349 * Initialize all hw fields.
1351 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1352 rt2x00dev->hw->extra_tx_headroom = 0;
1353 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1354 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1355 rt2x00dev->hw->queues = 2;
1357 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1358 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1359 rt2x00_eeprom_addr(rt2x00dev,
1360 EEPROM_MAC_ADDR_0));
1363 * Convert tx_power array in eeprom.
1365 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1366 for (i = 0; i < 14; i++)
1367 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1370 * Initialize hw_mode information.
1372 spec->num_modes = 1;
1373 spec->num_rates = 4;
1374 spec->tx_power_a = NULL;
1375 spec->tx_power_bg = txpower;
1376 spec->tx_power_default = DEFAULT_TXPOWER;
1378 spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1379 spec->channels = rf_vals_bg;
1382 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1387 * Allocate eeprom data.
1389 retval = rt2400pci_validate_eeprom(rt2x00dev);
1393 retval = rt2400pci_init_eeprom(rt2x00dev);
1398 * Initialize hw specifications.
1400 rt2400pci_probe_hw_mode(rt2x00dev);
1403 * This device requires the beacon ring
1405 __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
1408 * Set the rssi offset.
1410 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1416 * IEEE80211 stack callback functions.
1418 static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
1419 unsigned int changed_flags,
1420 unsigned int *total_flags,
1422 struct dev_addr_list *mc_list)
1424 struct rt2x00_dev *rt2x00dev = hw->priv;
1425 struct interface *intf = &rt2x00dev->interface;
1429 * Mask off any flags we are going to ignore from
1430 * the total_flags field.
1441 * Apply some rules to the filters:
1442 * - Some filters imply different filters to be set.
1443 * - Some things we can't filter out at all.
1444 * - Some filters are set based on interface type.
1446 *total_flags |= FIF_ALLMULTI;
1447 if (*total_flags & FIF_OTHER_BSS ||
1448 *total_flags & FIF_PROMISC_IN_BSS)
1449 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1450 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
1451 *total_flags |= FIF_PROMISC_IN_BSS;
1454 * Check if there is any work left for us.
1456 if (intf->filter == *total_flags)
1458 intf->filter = *total_flags;
1461 * Start configuration steps.
1462 * Note that the version error will always be dropped
1463 * since there is no filter for it at this time.
1465 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
1466 rt2x00_set_field32(®, RXCSR0_DROP_CRC,
1467 !(*total_flags & FIF_FCSFAIL));
1468 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL,
1469 !(*total_flags & FIF_PLCPFAIL));
1470 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL,
1471 !(*total_flags & FIF_CONTROL));
1472 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME,
1473 !(*total_flags & FIF_PROMISC_IN_BSS));
1474 rt2x00_set_field32(®, RXCSR0_DROP_TODS,
1475 !(*total_flags & FIF_PROMISC_IN_BSS));
1476 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1);
1477 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1480 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1481 u32 short_retry, u32 long_retry)
1483 struct rt2x00_dev *rt2x00dev = hw->priv;
1486 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
1487 rt2x00_set_field32(®, CSR11_LONG_RETRY, long_retry);
1488 rt2x00_set_field32(®, CSR11_SHORT_RETRY, short_retry);
1489 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1494 static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1496 const struct ieee80211_tx_queue_params *params)
1498 struct rt2x00_dev *rt2x00dev = hw->priv;
1501 * We don't support variating cw_min and cw_max variables
1502 * per queue. So by default we only configure the TX queue,
1503 * and ignore all other configurations.
1505 if (queue != IEEE80211_TX_QUEUE_DATA0)
1508 if (rt2x00mac_conf_tx(hw, queue, params))
1512 * Write configuration to register.
1514 rt2400pci_config_cw(rt2x00dev, &rt2x00dev->tx->tx_params);
1519 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1521 struct rt2x00_dev *rt2x00dev = hw->priv;
1525 rt2x00pci_register_read(rt2x00dev, CSR17, ®);
1526 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1527 rt2x00pci_register_read(rt2x00dev, CSR16, ®);
1528 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1533 static void rt2400pci_reset_tsf(struct ieee80211_hw *hw)
1535 struct rt2x00_dev *rt2x00dev = hw->priv;
1537 rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1538 rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1541 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1543 struct rt2x00_dev *rt2x00dev = hw->priv;
1546 rt2x00pci_register_read(rt2x00dev, CSR15, ®);
1547 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1550 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1552 .start = rt2x00mac_start,
1553 .stop = rt2x00mac_stop,
1554 .add_interface = rt2x00mac_add_interface,
1555 .remove_interface = rt2x00mac_remove_interface,
1556 .config = rt2x00mac_config,
1557 .config_interface = rt2x00mac_config_interface,
1558 .configure_filter = rt2400pci_configure_filter,
1559 .get_stats = rt2x00mac_get_stats,
1560 .set_retry_limit = rt2400pci_set_retry_limit,
1561 .erp_ie_changed = rt2x00mac_erp_ie_changed,
1562 .conf_tx = rt2400pci_conf_tx,
1563 .get_tx_stats = rt2x00mac_get_tx_stats,
1564 .get_tsf = rt2400pci_get_tsf,
1565 .reset_tsf = rt2400pci_reset_tsf,
1566 .beacon_update = rt2x00pci_beacon_update,
1567 .tx_last_beacon = rt2400pci_tx_last_beacon,
1570 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1571 .irq_handler = rt2400pci_interrupt,
1572 .probe_hw = rt2400pci_probe_hw,
1573 .initialize = rt2x00pci_initialize,
1574 .uninitialize = rt2x00pci_uninitialize,
1575 .set_device_state = rt2400pci_set_device_state,
1576 .rfkill_poll = rt2400pci_rfkill_poll,
1577 .link_stats = rt2400pci_link_stats,
1578 .reset_tuner = rt2400pci_reset_tuner,
1579 .link_tuner = rt2400pci_link_tuner,
1580 .write_tx_desc = rt2400pci_write_tx_desc,
1581 .write_tx_data = rt2x00pci_write_tx_data,
1582 .kick_tx_queue = rt2400pci_kick_tx_queue,
1583 .fill_rxdone = rt2400pci_fill_rxdone,
1584 .config_mac_addr = rt2400pci_config_mac_addr,
1585 .config_bssid = rt2400pci_config_bssid,
1586 .config_type = rt2400pci_config_type,
1587 .config_preamble = rt2400pci_config_preamble,
1588 .config = rt2400pci_config,
1591 static const struct rt2x00_ops rt2400pci_ops = {
1592 .name = KBUILD_MODNAME,
1593 .rxd_size = RXD_DESC_SIZE,
1594 .txd_size = TXD_DESC_SIZE,
1595 .eeprom_size = EEPROM_SIZE,
1597 .lib = &rt2400pci_rt2x00_ops,
1598 .hw = &rt2400pci_mac80211_ops,
1599 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1600 .debugfs = &rt2400pci_rt2x00debug,
1601 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1605 * RT2400pci module information.
1607 static struct pci_device_id rt2400pci_device_table[] = {
1608 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1612 MODULE_AUTHOR(DRV_PROJECT);
1613 MODULE_VERSION(DRV_VERSION);
1614 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1615 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1616 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1617 MODULE_LICENSE("GPL");
1619 static struct pci_driver rt2400pci_driver = {
1620 .name = KBUILD_MODNAME,
1621 .id_table = rt2400pci_device_table,
1622 .probe = rt2x00pci_probe,
1623 .remove = __devexit_p(rt2x00pci_remove),
1624 .suspend = rt2x00pci_suspend,
1625 .resume = rt2x00pci_resume,
1628 static int __init rt2400pci_init(void)
1630 return pci_register_driver(&rt2400pci_driver);
1633 static void __exit rt2400pci_exit(void)
1635 pci_unregister_driver(&rt2400pci_driver);
1638 module_init(rt2400pci_init);
1639 module_exit(rt2400pci_exit);