2 * include/asm-sh/cpu-sh3/cacheflush.h
4 * Copyright (C) 1999 Niibe Yutaka
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #ifndef __ASM_CPU_SH3_CACHEFLUSH_H
11 #define __ASM_CPU_SH3_CACHEFLUSH_H
16 * - flush_cache_all() flushes entire cache
17 * - flush_cache_mm(mm) flushes the specified mm context's cache lines
18 * - flush_cache_page(mm, vmaddr, pfn) flushes a single page
19 * - flush_cache_range(vma, start, end) flushes a range of pages
21 * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
22 * - flush_icache_range(start, end) flushes(invalidates) a range for icache
23 * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
25 * Caches are indexed (effectively) by physical address on SH-3, so
29 #if defined(CONFIG_SH7705_CACHE_32KB)
31 /* SH7705 is an SH3 processor with 32KB cache. This has alias issues like the
32 * SH4. Unlike the SH4 this is a unified cache so we need to do some work
33 * in mmap when 'exec'ing a new binary
35 /* 32KB cache, 4kb PAGE sizes need to check bit 12 */
36 #define CACHE_ALIAS 0x00001000
40 struct vm_area_struct;
42 extern void flush_cache_all(void);
43 extern void flush_cache_mm(struct mm_struct *mm);
44 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
46 extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
47 extern void flush_dcache_page(struct page *pg);
48 extern void flush_icache_range(unsigned long start, unsigned long end);
49 extern void flush_icache_page(struct vm_area_struct *vma, struct page *page);
51 #define flush_dcache_mmap_lock(mapping) do { } while (0)
52 #define flush_dcache_mmap_unlock(mapping) do { } while (0)
54 /* SH3 has unified cache so no special action needed here */
55 #define flush_cache_sigtramp(vaddr) do { } while (0)
56 #define flush_page_to_ram(page) do { } while (0)
57 #define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
59 #define p3_cache_init() do { } while (0)
61 #define PG_mapped PG_arch_1
63 /* We provide our own get_unmapped_area to avoid cache alias issue */
64 #define HAVE_ARCH_UNMAPPED_AREA
68 #define flush_cache_all() do { } while (0)
69 #define flush_cache_mm(mm) do { } while (0)
70 #define flush_cache_range(vma, start, end) do { } while (0)
71 #define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
72 #define flush_dcache_page(page) do { } while (0)
73 #define flush_dcache_mmap_lock(mapping) do { } while (0)
74 #define flush_dcache_mmap_unlock(mapping) do { } while (0)
75 #define flush_icache_range(start, end) do { } while (0)
76 #define flush_icache_page(vma,pg) do { } while (0)
77 #define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
78 #define flush_cache_sigtramp(vaddr) do { } while (0)
80 #define p3_cache_init() do { } while (0)
82 #define HAVE_ARCH_UNMAPPED_AREA
86 #endif /* __ASM_CPU_SH3_CACHEFLUSH_H */