Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394...
[linux-2.6] / arch / arm / mach-integrator / integrator_cp.c
1 /*
2  *  linux/arch/arm/mach-integrator/integrator_cp.c
3  *
4  *  Copyright (C) 2003 Deep Blue Solutions Ltd
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License.
9  */
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/list.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/slab.h>
17 #include <linux/string.h>
18 #include <linux/sysdev.h>
19 #include <linux/amba/bus.h>
20 #include <linux/amba/kmi.h>
21 #include <linux/amba/clcd.h>
22 #include <linux/io.h>
23
24 #include <mach/hardware.h>
25 #include <asm/irq.h>
26 #include <asm/setup.h>
27 #include <asm/mach-types.h>
28 #include <asm/hardware/icst525.h>
29
30 #include <mach/cm.h>
31 #include <mach/lm.h>
32
33 #include <asm/mach/arch.h>
34 #include <asm/mach/flash.h>
35 #include <asm/mach/irq.h>
36 #include <asm/mach/mmc.h>
37 #include <asm/mach/map.h>
38 #include <asm/mach/time.h>
39
40 #include "common.h"
41 #include "clock.h"
42
43 #define INTCP_PA_MMC_BASE               0x1c000000
44 #define INTCP_PA_AACI_BASE              0x1d000000
45
46 #define INTCP_PA_FLASH_BASE             0x24000000
47 #define INTCP_FLASH_SIZE                SZ_32M
48
49 #define INTCP_PA_CLCD_BASE              0xc0000000
50
51 #define INTCP_VA_CIC_BASE               0xf1000040
52 #define INTCP_VA_PIC_BASE               0xf1400000
53 #define INTCP_VA_SIC_BASE               0xfca00000
54
55 #define INTCP_PA_ETH_BASE               0xc8000000
56 #define INTCP_ETH_SIZE                  0x10
57
58 #define INTCP_VA_CTRL_BASE              0xfcb00000
59 #define INTCP_FLASHPROG                 0x04
60 #define CINTEGRATOR_FLASHPROG_FLVPPEN   (1 << 0)
61 #define CINTEGRATOR_FLASHPROG_FLWREN    (1 << 1)
62
63 /*
64  * Logical      Physical
65  * f1000000     10000000        Core module registers
66  * f1100000     11000000        System controller registers
67  * f1200000     12000000        EBI registers
68  * f1300000     13000000        Counter/Timer
69  * f1400000     14000000        Interrupt controller
70  * f1600000     16000000        UART 0
71  * f1700000     17000000        UART 1
72  * f1a00000     1a000000        Debug LEDs
73  * f1b00000     1b000000        GPIO
74  */
75
76 static struct map_desc intcp_io_desc[] __initdata = {
77         {
78                 .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
79                 .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
80                 .length         = SZ_4K,
81                 .type           = MT_DEVICE
82         }, {
83                 .virtual        = IO_ADDRESS(INTEGRATOR_SC_BASE),
84                 .pfn            = __phys_to_pfn(INTEGRATOR_SC_BASE),
85                 .length         = SZ_4K,
86                 .type           = MT_DEVICE
87         }, {
88                 .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
89                 .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
90                 .length         = SZ_4K,
91                 .type           = MT_DEVICE
92         }, {
93                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
94                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
95                 .length         = SZ_4K,
96                 .type           = MT_DEVICE
97         }, {
98                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
99                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
100                 .length         = SZ_4K,
101                 .type           = MT_DEVICE
102         }, {
103                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
104                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
105                 .length         = SZ_4K,
106                 .type           = MT_DEVICE
107         }, {
108                 .virtual        = IO_ADDRESS(INTEGRATOR_UART1_BASE),
109                 .pfn            = __phys_to_pfn(INTEGRATOR_UART1_BASE),
110                 .length         = SZ_4K,
111                 .type           = MT_DEVICE
112         }, {
113                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
114                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
115                 .length         = SZ_4K,
116                 .type           = MT_DEVICE
117         }, {
118                 .virtual        = IO_ADDRESS(INTEGRATOR_GPIO_BASE),
119                 .pfn            = __phys_to_pfn(INTEGRATOR_GPIO_BASE),
120                 .length         = SZ_4K,
121                 .type           = MT_DEVICE
122         }, {
123                 .virtual        = 0xfca00000,
124                 .pfn            = __phys_to_pfn(0xca000000),
125                 .length         = SZ_4K,
126                 .type           = MT_DEVICE
127         }, {
128                 .virtual        = 0xfcb00000,
129                 .pfn            = __phys_to_pfn(0xcb000000),
130                 .length         = SZ_4K,
131                 .type           = MT_DEVICE
132         }
133 };
134
135 static void __init intcp_map_io(void)
136 {
137         iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
138 }
139
140 #define cic_writel      __raw_writel
141 #define cic_readl       __raw_readl
142 #define pic_writel      __raw_writel
143 #define pic_readl       __raw_readl
144 #define sic_writel      __raw_writel
145 #define sic_readl       __raw_readl
146
147 static void cic_mask_irq(unsigned int irq)
148 {
149         irq -= IRQ_CIC_START;
150         cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
151 }
152
153 static void cic_unmask_irq(unsigned int irq)
154 {
155         irq -= IRQ_CIC_START;
156         cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
157 }
158
159 static struct irq_chip cic_chip = {
160         .name   = "CIC",
161         .ack    = cic_mask_irq,
162         .mask   = cic_mask_irq,
163         .unmask = cic_unmask_irq,
164 };
165
166 static void pic_mask_irq(unsigned int irq)
167 {
168         irq -= IRQ_PIC_START;
169         pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
170 }
171
172 static void pic_unmask_irq(unsigned int irq)
173 {
174         irq -= IRQ_PIC_START;
175         pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
176 }
177
178 static struct irq_chip pic_chip = {
179         .name   = "PIC",
180         .ack    = pic_mask_irq,
181         .mask   = pic_mask_irq,
182         .unmask = pic_unmask_irq,
183 };
184
185 static void sic_mask_irq(unsigned int irq)
186 {
187         irq -= IRQ_SIC_START;
188         sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
189 }
190
191 static void sic_unmask_irq(unsigned int irq)
192 {
193         irq -= IRQ_SIC_START;
194         sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
195 }
196
197 static struct irq_chip sic_chip = {
198         .name   = "SIC",
199         .ack    = sic_mask_irq,
200         .mask   = sic_mask_irq,
201         .unmask = sic_unmask_irq,
202 };
203
204 static void
205 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
206 {
207         unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
208
209         if (status == 0) {
210                 do_bad_IRQ(irq, desc);
211                 return;
212         }
213
214         do {
215                 irq = ffs(status) - 1;
216                 status &= ~(1 << irq);
217
218                 irq += IRQ_SIC_START;
219
220                 generic_handle_irq(irq);
221         } while (status);
222 }
223
224 static void __init intcp_init_irq(void)
225 {
226         unsigned int i;
227
228         /*
229          * Disable all interrupt sources
230          */
231         pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
232         pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
233
234         for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
235                 if (i == 11)
236                         i = 22;
237                 if (i == 29)
238                         break;
239                 set_irq_chip(i, &pic_chip);
240                 set_irq_handler(i, handle_level_irq);
241                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
242         }
243
244         cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
245         cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
246
247         for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
248                 set_irq_chip(i, &cic_chip);
249                 set_irq_handler(i, handle_level_irq);
250                 set_irq_flags(i, IRQF_VALID);
251         }
252
253         sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
254         sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
255
256         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
257                 set_irq_chip(i, &sic_chip);
258                 set_irq_handler(i, handle_level_irq);
259                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
260         }
261
262         set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
263 }
264
265 /*
266  * Clock handling
267  */
268 #define CM_LOCK (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
269 #define CM_AUXOSC (IO_ADDRESS(INTEGRATOR_HDR_BASE)+0x1c)
270
271 static const struct icst525_params cp_auxvco_params = {
272         .ref            = 24000,
273         .vco_max        = 320000,
274         .vd_min         = 8,
275         .vd_max         = 263,
276         .rd_min         = 3,
277         .rd_max         = 65,
278 };
279
280 static void cp_auxvco_set(struct clk *clk, struct icst525_vco vco)
281 {
282         u32 val;
283
284         val = readl(CM_AUXOSC) & ~0x7ffff;
285         val |= vco.v | (vco.r << 9) | (vco.s << 16);
286
287         writel(0xa05f, CM_LOCK);
288         writel(val, CM_AUXOSC);
289         writel(0, CM_LOCK);
290 }
291
292 static struct clk cp_clcd_clk = {
293         .name   = "CLCDCLK",
294         .params = &cp_auxvco_params,
295         .setvco = cp_auxvco_set,
296 };
297
298 static struct clk cp_mmci_clk = {
299         .name   = "MCLK",
300         .rate   = 14745600,
301 };
302
303 /*
304  * Flash handling.
305  */
306 static int intcp_flash_init(void)
307 {
308         u32 val;
309
310         val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
311         val |= CINTEGRATOR_FLASHPROG_FLWREN;
312         writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
313
314         return 0;
315 }
316
317 static void intcp_flash_exit(void)
318 {
319         u32 val;
320
321         val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
322         val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
323         writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
324 }
325
326 static void intcp_flash_set_vpp(int on)
327 {
328         u32 val;
329
330         val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
331         if (on)
332                 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
333         else
334                 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
335         writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
336 }
337
338 static struct flash_platform_data intcp_flash_data = {
339         .map_name       = "cfi_probe",
340         .width          = 4,
341         .init           = intcp_flash_init,
342         .exit           = intcp_flash_exit,
343         .set_vpp        = intcp_flash_set_vpp,
344 };
345
346 static struct resource intcp_flash_resource = {
347         .start          = INTCP_PA_FLASH_BASE,
348         .end            = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
349         .flags          = IORESOURCE_MEM,
350 };
351
352 static struct platform_device intcp_flash_device = {
353         .name           = "armflash",
354         .id             = 0,
355         .dev            = {
356                 .platform_data  = &intcp_flash_data,
357         },
358         .num_resources  = 1,
359         .resource       = &intcp_flash_resource,
360 };
361
362 static struct resource smc91x_resources[] = {
363         [0] = {
364                 .start  = INTCP_PA_ETH_BASE,
365                 .end    = INTCP_PA_ETH_BASE + INTCP_ETH_SIZE - 1,
366                 .flags  = IORESOURCE_MEM,
367         },
368         [1] = {
369                 .start  = IRQ_CP_ETHINT,
370                 .end    = IRQ_CP_ETHINT,
371                 .flags  = IORESOURCE_IRQ,
372         },
373 };
374
375 static struct platform_device smc91x_device = {
376         .name           = "smc91x",
377         .id             = 0,
378         .num_resources  = ARRAY_SIZE(smc91x_resources),
379         .resource       = smc91x_resources,
380 };
381
382 static struct platform_device *intcp_devs[] __initdata = {
383         &intcp_flash_device,
384         &smc91x_device,
385 };
386
387 /*
388  * It seems that the card insertion interrupt remains active after
389  * we've acknowledged it.  We therefore ignore the interrupt, and
390  * rely on reading it from the SIC.  This also means that we must
391  * clear the latched interrupt.
392  */
393 static unsigned int mmc_status(struct device *dev)
394 {
395         unsigned int status = readl(0xfca00004);
396         writel(8, 0xfcb00008);
397
398         return status & 8;
399 }
400
401 static struct mmc_platform_data mmc_data = {
402         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
403         .status         = mmc_status,
404 };
405
406 static struct amba_device mmc_device = {
407         .dev            = {
408                 .bus_id = "mb:1c",
409                 .platform_data = &mmc_data,
410         },
411         .res            = {
412                 .start  = INTCP_PA_MMC_BASE,
413                 .end    = INTCP_PA_MMC_BASE + SZ_4K - 1,
414                 .flags  = IORESOURCE_MEM,
415         },
416         .irq            = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
417         .periphid       = 0,
418 };
419
420 static struct amba_device aaci_device = {
421         .dev            = {
422                 .bus_id = "mb:1d",
423         },
424         .res            = {
425                 .start  = INTCP_PA_AACI_BASE,
426                 .end    = INTCP_PA_AACI_BASE + SZ_4K - 1,
427                 .flags  = IORESOURCE_MEM,
428         },
429         .irq            = { IRQ_CP_AACIINT, NO_IRQ },
430         .periphid       = 0,
431 };
432
433
434 /*
435  * CLCD support
436  */
437 static struct clcd_panel vga = {
438         .mode           = {
439                 .name           = "VGA",
440                 .refresh        = 60,
441                 .xres           = 640,
442                 .yres           = 480,
443                 .pixclock       = 39721,
444                 .left_margin    = 40,
445                 .right_margin   = 24,
446                 .upper_margin   = 32,
447                 .lower_margin   = 11,
448                 .hsync_len      = 96,
449                 .vsync_len      = 2,
450                 .sync           = 0,
451                 .vmode          = FB_VMODE_NONINTERLACED,
452         },
453         .width          = -1,
454         .height         = -1,
455         .tim2           = TIM2_BCD | TIM2_IPC,
456         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
457         .bpp            = 16,
458         .grayscale      = 0,
459 };
460
461 /*
462  * Ensure VGA is selected.
463  */
464 static void cp_clcd_enable(struct clcd_fb *fb)
465 {
466         u32 val;
467
468         if (fb->fb.var.bits_per_pixel <= 8)
469                 val = CM_CTRL_LCDMUXSEL_VGA_8421BPP;
470         else if (fb->fb.var.bits_per_pixel <= 16)
471                 val = CM_CTRL_LCDMUXSEL_VGA_16BPP
472                         | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1
473                         | CM_CTRL_STATIC1 | CM_CTRL_STATIC2;
474         else
475                 val = 0; /* no idea for this, don't trust the docs */
476
477         cm_control(CM_CTRL_LCDMUXSEL_MASK|
478                    CM_CTRL_LCDEN0|
479                    CM_CTRL_LCDEN1|
480                    CM_CTRL_STATIC1|
481                    CM_CTRL_STATIC2|
482                    CM_CTRL_STATIC|
483                    CM_CTRL_n24BITEN, val);
484 }
485
486 static unsigned long framesize = SZ_1M;
487
488 static int cp_clcd_setup(struct clcd_fb *fb)
489 {
490         dma_addr_t dma;
491
492         fb->panel = &vga;
493
494         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
495                                                     &dma, GFP_KERNEL);
496         if (!fb->fb.screen_base) {
497                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
498                 return -ENOMEM;
499         }
500
501         fb->fb.fix.smem_start   = dma;
502         fb->fb.fix.smem_len     = framesize;
503
504         return 0;
505 }
506
507 static int cp_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
508 {
509         return dma_mmap_writecombine(&fb->dev->dev, vma,
510                                      fb->fb.screen_base,
511                                      fb->fb.fix.smem_start,
512                                      fb->fb.fix.smem_len);
513 }
514
515 static void cp_clcd_remove(struct clcd_fb *fb)
516 {
517         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
518                               fb->fb.screen_base, fb->fb.fix.smem_start);
519 }
520
521 static struct clcd_board clcd_data = {
522         .name           = "Integrator/CP",
523         .check          = clcdfb_check,
524         .decode         = clcdfb_decode,
525         .enable         = cp_clcd_enable,
526         .setup          = cp_clcd_setup,
527         .mmap           = cp_clcd_mmap,
528         .remove         = cp_clcd_remove,
529 };
530
531 static struct amba_device clcd_device = {
532         .dev            = {
533                 .bus_id = "mb:c0",
534                 .coherent_dma_mask = ~0,
535                 .platform_data = &clcd_data,
536         },
537         .res            = {
538                 .start  = INTCP_PA_CLCD_BASE,
539                 .end    = INTCP_PA_CLCD_BASE + SZ_4K - 1,
540                 .flags  = IORESOURCE_MEM,
541         },
542         .dma_mask       = ~0,
543         .irq            = { IRQ_CP_CLCDCINT, NO_IRQ },
544         .periphid       = 0,
545 };
546
547 static struct amba_device *amba_devs[] __initdata = {
548         &mmc_device,
549         &aaci_device,
550         &clcd_device,
551 };
552
553 static void __init intcp_init(void)
554 {
555         int i;
556
557         clk_register(&cp_clcd_clk);
558         clk_register(&cp_mmci_clk);
559
560         platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
561
562         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
563                 struct amba_device *d = amba_devs[i];
564                 amba_device_register(d, &iomem_resource);
565         }
566 }
567
568 #define TIMER_CTRL_IE   (1 << 5)                        /* Interrupt Enable */
569
570 static void __init intcp_timer_init(void)
571 {
572         integrator_time_init(1000000 / HZ, TIMER_CTRL_IE);
573 }
574
575 static struct sys_timer cp_timer = {
576         .init           = intcp_timer_init,
577         .offset         = integrator_gettimeoffset,
578 };
579
580 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
581         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
582         .phys_io        = 0x16000000,
583         .io_pg_offst    = ((0xf1600000) >> 18) & 0xfffc,
584         .boot_params    = 0x00000100,
585         .map_io         = intcp_map_io,
586         .init_irq       = intcp_init_irq,
587         .timer          = &cp_timer,
588         .init_machine   = intcp_init,
589 MACHINE_END