git.oblomov.eu Git - linux-2.6/blob - sound/pci/rme96.c

   1 /*
   2  *   ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
   3  *   interfaces
   4  *
   5  *      Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
   6  *
   7  *      Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
   8  *      code.
   9  *
  10  *   This program is free software; you can redistribute it and/or modify
  11  *   it under the terms of the GNU General Public License as published by
  12  *   the Free Software Foundation; either version 2 of the License, or
  13  *   (at your option) any later version.
  14  *
  15  *   This program is distributed in the hope that it will be useful,
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *   GNU General Public License for more details.
  19  *
  20  *   You should have received a copy of the GNU General Public License
  21  *   along with this program; if not, write to the Free Software
  22  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  *
  24  */
  25
  26 #include <linux/delay.h>
  27 #include <linux/init.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/slab.h>
  31 #include <linux/moduleparam.h>
  32
  33 #include <sound/core.h>
  34 #include <sound/info.h>
  35 #include <sound/control.h>
  36 #include <sound/pcm.h>
  37 #include <sound/pcm_params.h>
  38 #include <sound/asoundef.h>
  39 #include <sound/initval.h>
  40
  41 #include <asm/io.h>
  42
  43 /* note, two last pcis should be equal, it is not a bug */
  44
  45 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
  46 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
  47                    "Digi96/8 PAD");
  48 MODULE_LICENSE("GPL");
  49 MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
  50                 "{RME,Digi96/8},"
  51                 "{RME,Digi96/8 PRO},"
  52                 "{RME,Digi96/8 PST},"
  53                 "{RME,Digi96/8 PAD}}");
  54
  55 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  56 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  57 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
  58
  59 module_param_array(index, int, NULL, 0444);
  60 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
  61 module_param_array(id, charp, NULL, 0444);
  62 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
  63 module_param_array(enable, bool, NULL, 0444);
  64 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
  65
  66 /*
  67  * Defines for RME Digi96 series, from internal RME reference documents
  68  * dated 12.01.00
  69  */
  70
  71 #define RME96_SPDIF_NCHANNELS 2
  72
  73 /* Playback and capture buffer size */
  74 #define RME96_BUFFER_SIZE 0x10000
  75
  76 /* IO area size */
  77 #define RME96_IO_SIZE 0x60000
  78
  79 /* IO area offsets */
  80 #define RME96_IO_PLAY_BUFFER      0x0
  81 #define RME96_IO_REC_BUFFER       0x10000
  82 #define RME96_IO_CONTROL_REGISTER 0x20000
  83 #define RME96_IO_ADDITIONAL_REG   0x20004
  84 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
  85 #define RME96_IO_CONFIRM_REC_IRQ  0x2000C
  86 #define RME96_IO_SET_PLAY_POS     0x40000
  87 #define RME96_IO_RESET_PLAY_POS   0x4FFFC
  88 #define RME96_IO_SET_REC_POS      0x50000
  89 #define RME96_IO_RESET_REC_POS    0x5FFFC
  90 #define RME96_IO_GET_PLAY_POS     0x20000
  91 #define RME96_IO_GET_REC_POS      0x30000
  92
  93 /* Write control register bits */
  94 #define RME96_WCR_START     (1 << 0)
  95 #define RME96_WCR_START_2   (1 << 1)
  96 #define RME96_WCR_GAIN_0    (1 << 2)
  97 #define RME96_WCR_GAIN_1    (1 << 3)
  98 #define RME96_WCR_MODE24    (1 << 4)
  99 #define RME96_WCR_MODE24_2  (1 << 5)
 100 #define RME96_WCR_BM        (1 << 6)
 101 #define RME96_WCR_BM_2      (1 << 7)
 102 #define RME96_WCR_ADAT      (1 << 8)
 103 #define RME96_WCR_FREQ_0    (1 << 9)
 104 #define RME96_WCR_FREQ_1    (1 << 10)
 105 #define RME96_WCR_DS        (1 << 11)
 106 #define RME96_WCR_PRO       (1 << 12)
 107 #define RME96_WCR_EMP       (1 << 13)
 108 #define RME96_WCR_SEL       (1 << 14)
 109 #define RME96_WCR_MASTER    (1 << 15)
 110 #define RME96_WCR_PD        (1 << 16)
 111 #define RME96_WCR_INP_0     (1 << 17)
 112 #define RME96_WCR_INP_1     (1 << 18)
 113 #define RME96_WCR_THRU_0    (1 << 19)
 114 #define RME96_WCR_THRU_1    (1 << 20)
 115 #define RME96_WCR_THRU_2    (1 << 21)
 116 #define RME96_WCR_THRU_3    (1 << 22)
 117 #define RME96_WCR_THRU_4    (1 << 23)
 118 #define RME96_WCR_THRU_5    (1 << 24)
 119 #define RME96_WCR_THRU_6    (1 << 25)
 120 #define RME96_WCR_THRU_7    (1 << 26)
 121 #define RME96_WCR_DOLBY     (1 << 27)
 122 #define RME96_WCR_MONITOR_0 (1 << 28)
 123 #define RME96_WCR_MONITOR_1 (1 << 29)
 124 #define RME96_WCR_ISEL      (1 << 30)
 125 #define RME96_WCR_IDIS      (1 << 31)
 126
 127 #define RME96_WCR_BITPOS_GAIN_0 2
 128 #define RME96_WCR_BITPOS_GAIN_1 3
 129 #define RME96_WCR_BITPOS_FREQ_0 9
 130 #define RME96_WCR_BITPOS_FREQ_1 10
 131 #define RME96_WCR_BITPOS_INP_0 17
 132 #define RME96_WCR_BITPOS_INP_1 18
 133 #define RME96_WCR_BITPOS_MONITOR_0 28
 134 #define RME96_WCR_BITPOS_MONITOR_1 29
 135
 136 /* Read control register bits */
 137 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
 138 #define RME96_RCR_IRQ_2     (1 << 16)
 139 #define RME96_RCR_T_OUT     (1 << 17)
 140 #define RME96_RCR_DEV_ID_0  (1 << 21)
 141 #define RME96_RCR_DEV_ID_1  (1 << 22)
 142 #define RME96_RCR_LOCK      (1 << 23)
 143 #define RME96_RCR_VERF      (1 << 26)
 144 #define RME96_RCR_F0        (1 << 27)
 145 #define RME96_RCR_F1        (1 << 28)
 146 #define RME96_RCR_F2        (1 << 29)
 147 #define RME96_RCR_AUTOSYNC  (1 << 30)
 148 #define RME96_RCR_IRQ       (1 << 31)
 149
 150 #define RME96_RCR_BITPOS_F0 27
 151 #define RME96_RCR_BITPOS_F1 28
 152 #define RME96_RCR_BITPOS_F2 29
 153
 154 /* Additonal register bits */
 155 #define RME96_AR_WSEL       (1 << 0)
 156 #define RME96_AR_ANALOG     (1 << 1)
 157 #define RME96_AR_FREQPAD_0  (1 << 2)
 158 #define RME96_AR_FREQPAD_1  (1 << 3)
 159 #define RME96_AR_FREQPAD_2  (1 << 4)
 160 #define RME96_AR_PD2        (1 << 5)
 161 #define RME96_AR_DAC_EN     (1 << 6)
 162 #define RME96_AR_CLATCH     (1 << 7)
 163 #define RME96_AR_CCLK       (1 << 8)
 164 #define RME96_AR_CDATA      (1 << 9)
 165
 166 #define RME96_AR_BITPOS_F0 2
 167 #define RME96_AR_BITPOS_F1 3
 168 #define RME96_AR_BITPOS_F2 4
 169
 170 /* Monitor tracks */
 171 #define RME96_MONITOR_TRACKS_1_2 0
 172 #define RME96_MONITOR_TRACKS_3_4 1
 173 #define RME96_MONITOR_TRACKS_5_6 2
 174 #define RME96_MONITOR_TRACKS_7_8 3
 175
 176 /* Attenuation */
 177 #define RME96_ATTENUATION_0 0
 178 #define RME96_ATTENUATION_6 1
 179 #define RME96_ATTENUATION_12 2
 180 #define RME96_ATTENUATION_18 3
 181
 182 /* Input types */
 183 #define RME96_INPUT_OPTICAL 0
 184 #define RME96_INPUT_COAXIAL 1
 185 #define RME96_INPUT_INTERNAL 2
 186 #define RME96_INPUT_XLR 3
 187 #define RME96_INPUT_ANALOG 4
 188
 189 /* Clock modes */
 190 #define RME96_CLOCKMODE_SLAVE 0
 191 #define RME96_CLOCKMODE_MASTER 1
 192 #define RME96_CLOCKMODE_WORDCLOCK 2
 193
 194 /* Block sizes in bytes */
 195 #define RME96_SMALL_BLOCK_SIZE 2048
 196 #define RME96_LARGE_BLOCK_SIZE 8192
 197
 198 /* Volume control */
 199 #define RME96_AD1852_VOL_BITS 14
 200 #define RME96_AD1855_VOL_BITS 10
 201
 202
 203 struct rme96 {
 204         spinlock_t    lock;
 205         int irq;
 206         unsigned long port;
 207         void __iomem *iobase;
 208
 209         u32 wcreg;    /* cached write control register value */
 210         u32 wcreg_spdif;                /* S/PDIF setup */
 211         u32 wcreg_spdif_stream;         /* S/PDIF setup (temporary) */
 212         u32 rcreg;    /* cached read control register value */
 213         u32 areg;     /* cached additional register value */
 214         u16 vol[2]; /* cached volume of analog output */
 215
 216         u8 rev; /* card revision number */
 217
 218         struct snd_pcm_substream *playback_substream;
 219         struct snd_pcm_substream *capture_substream;
 220
 221         int playback_frlog; /* log2 of framesize */
 222         int capture_frlog;
 223
 224         size_t playback_periodsize; /* in bytes, zero if not used */
 225         size_t capture_periodsize; /* in bytes, zero if not used */
 226
 227         struct snd_card *card;
 228         struct snd_pcm *spdif_pcm;
 229         struct snd_pcm *adat_pcm;
 230         struct pci_dev     *pci;
 231         struct snd_kcontrol   *spdif_ctl;
 232 };
 233
 234 static struct pci_device_id snd_rme96_ids[] = {
 235         { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_RME_DIGI96,
 236           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
 237         { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_RME_DIGI96_8,
 238           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
 239         { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO,
 240           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
 241         { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST,
 242           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
 243         { 0, }
 244 };
 245
 246 MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
 247
 248 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
 249 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
 250 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
 251 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
 252                                      (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
 253 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
 254 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
 255                                   ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
 256 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
 257
 258 static int
 259 snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
 260
 261 static int
 262 snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
 263
 264 static int
 265 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
 266                            int cmd);
 267
 268 static int
 269 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
 270                           int cmd);
 271
 272 static snd_pcm_uframes_t
 273 snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
 274
 275 static snd_pcm_uframes_t
 276 snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
 277
 278 static void __devinit
 279 snd_rme96_proc_init(struct rme96 *rme96);
 280
 281 static int
 282 snd_rme96_create_switches(struct snd_card *card,
 283                           struct rme96 *rme96);
 284
 285 static int
 286 snd_rme96_getinputtype(struct rme96 *rme96);
 287
 288 static inline unsigned int
 289 snd_rme96_playback_ptr(struct rme96 *rme96)
 290 {
 291         return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
 292                 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
 293 }
 294
 295 static inline unsigned int
 296 snd_rme96_capture_ptr(struct rme96 *rme96)
 297 {
 298         return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
 299                 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
 300 }
 301
 302 static int
 303 snd_rme96_playback_silence(struct snd_pcm_substream *substream,
 304                            int channel, /* not used (interleaved data) */
 305                            snd_pcm_uframes_t pos,
 306                            snd_pcm_uframes_t count)
 307 {
 308         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 309         count <<= rme96->playback_frlog;
 310         pos <<= rme96->playback_frlog;
 311         memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
 312                   0, count);
 313         return 0;
 314 }
 315
 316 static int
 317 snd_rme96_playback_copy(struct snd_pcm_substream *substream,
 318                         int channel, /* not used (interleaved data) */
 319                         snd_pcm_uframes_t pos,
 320                         void __user *src,
 321                         snd_pcm_uframes_t count)
 322 {
 323         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 324         count <<= rme96->playback_frlog;
 325         pos <<= rme96->playback_frlog;
 326         copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
 327                             count);
 328         return 0;
 329 }
 330
 331 static int
 332 snd_rme96_capture_copy(struct snd_pcm_substream *substream,
 333                        int channel, /* not used (interleaved data) */
 334                        snd_pcm_uframes_t pos,
 335                        void __user *dst,
 336                        snd_pcm_uframes_t count)
 337 {
 338         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 339         count <<= rme96->capture_frlog;
 340         pos <<= rme96->capture_frlog;
 341         copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
 342                             count);
 343         return 0;
 344 }
 345
 346 /*
 347  * Digital output capabilities (S/PDIF)
 348  */
 349 static struct snd_pcm_hardware snd_rme96_playback_spdif_info =
 350 {
 351         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 352                               SNDRV_PCM_INFO_MMAP_VALID |
 353                               SNDRV_PCM_INFO_INTERLEAVED |
 354                               SNDRV_PCM_INFO_PAUSE),
 355         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 356                               SNDRV_PCM_FMTBIT_S32_LE),
 357         .rates =             (SNDRV_PCM_RATE_32000 |
 358                               SNDRV_PCM_RATE_44100 |
 359                               SNDRV_PCM_RATE_48000 |
 360                               SNDRV_PCM_RATE_64000 |
 361                               SNDRV_PCM_RATE_88200 |
 362                               SNDRV_PCM_RATE_96000),
 363         .rate_min =          32000,
 364         .rate_max =          96000,
 365         .channels_min =      2,
 366         .channels_max =      2,
 367         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 368         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 369         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 370         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 371         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 372         .fifo_size =         0,
 373 };
 374
 375 /*
 376  * Digital input capabilities (S/PDIF)
 377  */
 378 static struct snd_pcm_hardware snd_rme96_capture_spdif_info =
 379 {
 380         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 381                               SNDRV_PCM_INFO_MMAP_VALID |
 382                               SNDRV_PCM_INFO_INTERLEAVED |
 383                               SNDRV_PCM_INFO_PAUSE),
 384         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 385                               SNDRV_PCM_FMTBIT_S32_LE),
 386         .rates =             (SNDRV_PCM_RATE_32000 |
 387                               SNDRV_PCM_RATE_44100 |
 388                               SNDRV_PCM_RATE_48000 |
 389                               SNDRV_PCM_RATE_64000 |
 390                               SNDRV_PCM_RATE_88200 |
 391                               SNDRV_PCM_RATE_96000),
 392         .rate_min =          32000,
 393         .rate_max =          96000,
 394         .channels_min =      2,
 395         .channels_max =      2,
 396         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 397         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 398         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 399         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 400         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 401         .fifo_size =         0,
 402 };
 403
 404 /*
 405  * Digital output capabilities (ADAT)
 406  */
 407 static struct snd_pcm_hardware snd_rme96_playback_adat_info =
 408 {
 409         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 410                               SNDRV_PCM_INFO_MMAP_VALID |
 411                               SNDRV_PCM_INFO_INTERLEAVED |
 412                               SNDRV_PCM_INFO_PAUSE),
 413         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 414                               SNDRV_PCM_FMTBIT_S32_LE),
 415         .rates =             (SNDRV_PCM_RATE_44100 |
 416                               SNDRV_PCM_RATE_48000),
 417         .rate_min =          44100,
 418         .rate_max =          48000,
 419         .channels_min =      8,
 420         .channels_max =      8,
 421         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 422         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 423         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 424         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 425         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 426         .fifo_size =         0,
 427 };
 428
 429 /*
 430  * Digital input capabilities (ADAT)
 431  */
 432 static struct snd_pcm_hardware snd_rme96_capture_adat_info =
 433 {
 434         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 435                               SNDRV_PCM_INFO_MMAP_VALID |
 436                               SNDRV_PCM_INFO_INTERLEAVED |
 437                               SNDRV_PCM_INFO_PAUSE),
 438         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 439                               SNDRV_PCM_FMTBIT_S32_LE),
 440         .rates =             (SNDRV_PCM_RATE_44100 |
 441                               SNDRV_PCM_RATE_48000),
 442         .rate_min =          44100,
 443         .rate_max =          48000,
 444         .channels_min =      8,
 445         .channels_max =      8,
 446         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 447         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 448         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 449         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 450         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 451         .fifo_size =         0,
 452 };
 453
 454 /*
 455  * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
 456  * of the AD1852 or AD1852 D/A converter on the board.  CDATA must be set up
 457  * on the falling edge of CCLK and be stable on the rising edge.  The rising
 458  * edge of CLATCH after the last data bit clocks in the whole data word.
 459  * A fast processor could probably drive the SPI interface faster than the
 460  * DAC can handle (3MHz for the 1855, unknown for the 1852).  The udelay(1)
 461  * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
 462  *
 463  * NOTE: increased delay from 1 to 10, since there where problems setting
 464  * the volume.
 465  */
 466 static void
 467 snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
 468 {
 469         int i;
 470
 471         for (i = 0; i < 16; i++) {
 472                 if (val & 0x8000) {
 473                         rme96->areg |= RME96_AR_CDATA;
 474                 } else {
 475                         rme96->areg &= ~RME96_AR_CDATA;
 476                 }
 477                 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
 478                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 479                 udelay(10);
 480                 rme96->areg |= RME96_AR_CCLK;
 481                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 482                 udelay(10);
 483                 val <<= 1;
 484         }
 485         rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
 486         rme96->areg |= RME96_AR_CLATCH;
 487         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 488         udelay(10);
 489         rme96->areg &= ~RME96_AR_CLATCH;
 490         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 491 }
 492
 493 static void
 494 snd_rme96_apply_dac_volume(struct rme96 *rme96)
 495 {
 496         if (RME96_DAC_IS_1852(rme96)) {
 497                 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
 498                 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
 499         } else if (RME96_DAC_IS_1855(rme96)) {
 500                 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
 501                 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
 502         }
 503 }
 504
 505 static void
 506 snd_rme96_reset_dac(struct rme96 *rme96)
 507 {
 508         writel(rme96->wcreg | RME96_WCR_PD,
 509                rme96->iobase + RME96_IO_CONTROL_REGISTER);
 510         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 511 }
 512
 513 static int
 514 snd_rme96_getmontracks(struct rme96 *rme96)
 515 {
 516         return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
 517                 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
 518 }
 519
 520 static int
 521 snd_rme96_setmontracks(struct rme96 *rme96,
 522                        int montracks)
 523 {
 524         if (montracks & 1) {
 525                 rme96->wcreg |= RME96_WCR_MONITOR_0;
 526         } else {
 527                 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
 528         }
 529         if (montracks & 2) {
 530                 rme96->wcreg |= RME96_WCR_MONITOR_1;
 531         } else {
 532                 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
 533         }
 534         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 535         return 0;
 536 }
 537
 538 static int
 539 snd_rme96_getattenuation(struct rme96 *rme96)
 540 {
 541         return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
 542                 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
 543 }
 544
 545 static int
 546 snd_rme96_setattenuation(struct rme96 *rme96,
 547                          int attenuation)
 548 {
 549         switch (attenuation) {
 550         case 0:
 551                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
 552                         ~RME96_WCR_GAIN_1;
 553                 break;
 554         case 1:
 555                 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
 556                         ~RME96_WCR_GAIN_1;
 557                 break;
 558         case 2:
 559                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
 560                         RME96_WCR_GAIN_1;
 561                 break;
 562         case 3:
 563                 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
 564                         RME96_WCR_GAIN_1;
 565                 break;
 566         default:
 567                 return -EINVAL;
 568         }
 569         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 570         return 0;
 571 }
 572
 573 static int
 574 snd_rme96_capture_getrate(struct rme96 *rme96,
 575                           int *is_adat)
 576 {
 577         int n, rate;
 578
 579         *is_adat = 0;
 580         if (rme96->areg & RME96_AR_ANALOG) {
 581                 /* Analog input, overrides S/PDIF setting */
 582                 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
 583                         (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
 584                 switch (n) {
 585                 case 1:
 586                         rate = 32000;
 587                         break;
 588                 case 2:
 589                         rate = 44100;
 590                         break;
 591                 case 3:
 592                         rate = 48000;
 593                         break;
 594                 default:
 595                         return -1;
 596                 }
 597                 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
 598         }
 599
 600         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
 601         if (rme96->rcreg & RME96_RCR_LOCK) {
 602                 /* ADAT rate */
 603                 *is_adat = 1;
 604                 if (rme96->rcreg & RME96_RCR_T_OUT) {
 605                         return 48000;
 606                 }
 607                 return 44100;
 608         }
 609
 610         if (rme96->rcreg & RME96_RCR_VERF) {
 611                 return -1;
 612         }
 613
 614         /* S/PDIF rate */
 615         n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
 616                 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
 617                 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
 618
 619         switch (n) {
 620         case 0:
 621                 if (rme96->rcreg & RME96_RCR_T_OUT) {
 622                         return 64000;
 623                 }
 624                 return -1;
 625         case 3: return 96000;
 626         case 4: return 88200;
 627         case 5: return 48000;
 628         case 6: return 44100;
 629         case 7: return 32000;
 630         default:
 631                 break;
 632         }
 633         return -1;
 634 }
 635
 636 static int
 637 snd_rme96_playback_getrate(struct rme96 *rme96)
 638 {
 639         int rate, dummy;
 640
 641         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
 642             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
 643             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
 644         {
 645                 /* slave clock */
 646                 return rate;
 647         }
 648         rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
 649                 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
 650         switch (rate) {
 651         case 1:
 652                 rate = 32000;
 653                 break;
 654         case 2:
 655                 rate = 44100;
 656                 break;
 657         case 3:
 658                 rate = 48000;
 659                 break;
 660         default:
 661                 return -1;
 662         }
 663         return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
 664 }
 665
 666 static int
 667 snd_rme96_playback_setrate(struct rme96 *rme96,
 668                            int rate)
 669 {
 670         int ds;
 671
 672         ds = rme96->wcreg & RME96_WCR_DS;
 673         switch (rate) {
 674         case 32000:
 675                 rme96->wcreg &= ~RME96_WCR_DS;
 676                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
 677                         ~RME96_WCR_FREQ_1;
 678                 break;
 679         case 44100:
 680                 rme96->wcreg &= ~RME96_WCR_DS;
 681                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
 682                         ~RME96_WCR_FREQ_0;
 683                 break;
 684         case 48000:
 685                 rme96->wcreg &= ~RME96_WCR_DS;
 686                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
 687                         RME96_WCR_FREQ_1;
 688                 break;
 689         case 64000:
 690                 rme96->wcreg |= RME96_WCR_DS;
 691                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
 692                         ~RME96_WCR_FREQ_1;
 693                 break;
 694         case 88200:
 695                 rme96->wcreg |= RME96_WCR_DS;
 696                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
 697                         ~RME96_WCR_FREQ_0;
 698                 break;
 699         case 96000:
 700                 rme96->wcreg |= RME96_WCR_DS;
 701                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
 702                         RME96_WCR_FREQ_1;
 703                 break;
 704         default:
 705                 return -EINVAL;
 706         }
 707         if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
 708             (ds && !(rme96->wcreg & RME96_WCR_DS)))
 709         {
 710                 /* change to/from double-speed: reset the DAC (if available) */
 711                 snd_rme96_reset_dac(rme96);
 712         } else {
 713                 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 714         }
 715         return 0;
 716 }
 717
 718 static int
 719 snd_rme96_capture_analog_setrate(struct rme96 *rme96,
 720                                  int rate)
 721 {
 722         switch (rate) {
 723         case 32000:
 724                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
 725                                ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
 726                 break;
 727         case 44100:
 728                 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
 729                                RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
 730                 break;
 731         case 48000:
 732                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
 733                                RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
 734                 break;
 735         case 64000:
 736                 if (rme96->rev < 4) {
 737                         return -EINVAL;
 738                 }
 739                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
 740                                ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
 741                 break;
 742         case 88200:
 743                 if (rme96->rev < 4) {
 744                         return -EINVAL;
 745                 }
 746                 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
 747                                RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
 748                 break;
 749         case 96000:
 750                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
 751                                RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
 752                 break;
 753         default:
 754                 return -EINVAL;
 755         }
 756         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 757         return 0;
 758 }
 759
 760 static int
 761 snd_rme96_setclockmode(struct rme96 *rme96,
 762                        int mode)
 763 {
 764         switch (mode) {
 765         case RME96_CLOCKMODE_SLAVE:
 766                 /* AutoSync */
 767                 rme96->wcreg &= ~RME96_WCR_MASTER;
 768                 rme96->areg &= ~RME96_AR_WSEL;
 769                 break;
 770         case RME96_CLOCKMODE_MASTER:
 771                 /* Internal */
 772                 rme96->wcreg |= RME96_WCR_MASTER;
 773                 rme96->areg &= ~RME96_AR_WSEL;
 774                 break;
 775         case RME96_CLOCKMODE_WORDCLOCK:
 776                 /* Word clock is a master mode */
 777                 rme96->wcreg |= RME96_WCR_MASTER;
 778                 rme96->areg |= RME96_AR_WSEL;
 779                 break;
 780         default:
 781                 return -EINVAL;
 782         }
 783         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 784         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 785         return 0;
 786 }
 787
 788 static int
 789 snd_rme96_getclockmode(struct rme96 *rme96)
 790 {
 791         if (rme96->areg & RME96_AR_WSEL) {
 792                 return RME96_CLOCKMODE_WORDCLOCK;
 793         }
 794         return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
 795                 RME96_CLOCKMODE_SLAVE;
 796 }
 797
 798 static int
 799 snd_rme96_setinputtype(struct rme96 *rme96,
 800                        int type)
 801 {
 802         int n;
 803
 804         switch (type) {
 805         case RME96_INPUT_OPTICAL:
 806                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
 807                         ~RME96_WCR_INP_1;
 808                 break;
 809         case RME96_INPUT_COAXIAL:
 810                 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
 811                         ~RME96_WCR_INP_1;
 812                 break;
 813         case RME96_INPUT_INTERNAL:
 814                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
 815                         RME96_WCR_INP_1;
 816                 break;
 817         case RME96_INPUT_XLR:
 818                 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
 819                      rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
 820                     (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
 821                      rme96->rev > 4))
 822                 {
 823                         /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
 824                         return -EINVAL;
 825                 }
 826                 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
 827                         RME96_WCR_INP_1;
 828                 break;
 829         case RME96_INPUT_ANALOG:
 830                 if (!RME96_HAS_ANALOG_IN(rme96)) {
 831                         return -EINVAL;
 832                 }
 833                 rme96->areg |= RME96_AR_ANALOG;
 834                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 835                 if (rme96->rev < 4) {
 836                         /*
 837                          * Revision less than 004 does not support 64 and
 838                          * 88.2 kHz
 839                          */
 840                         if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
 841                                 snd_rme96_capture_analog_setrate(rme96, 44100);
 842                         }
 843                         if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
 844                                 snd_rme96_capture_analog_setrate(rme96, 32000);
 845                         }
 846                 }
 847                 return 0;
 848         default:
 849                 return -EINVAL;
 850         }
 851         if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
 852                 rme96->areg &= ~RME96_AR_ANALOG;
 853                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 854         }
 855         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 856         return 0;
 857 }
 858
 859 static int
 860 snd_rme96_getinputtype(struct rme96 *rme96)
 861 {
 862         if (rme96->areg & RME96_AR_ANALOG) {
 863                 return RME96_INPUT_ANALOG;
 864         }
 865         return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
 866                 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
 867 }
 868
 869 static void
 870 snd_rme96_setframelog(struct rme96 *rme96,
 871                       int n_channels,
 872                       int is_playback)
 873 {
 874         int frlog;
 875
 876         if (n_channels == 2) {
 877                 frlog = 1;
 878         } else {
 879                 /* assume 8 channels */
 880                 frlog = 3;
 881         }
 882         if (is_playback) {
 883                 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
 884                 rme96->playback_frlog = frlog;
 885         } else {
 886                 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
 887                 rme96->capture_frlog = frlog;
 888         }
 889 }
 890
 891 static int
 892 snd_rme96_playback_setformat(struct rme96 *rme96,
 893                              int format)
 894 {
 895         switch (format) {
 896         case SNDRV_PCM_FORMAT_S16_LE:
 897                 rme96->wcreg &= ~RME96_WCR_MODE24;
 898                 break;
 899         case SNDRV_PCM_FORMAT_S32_LE:
 900                 rme96->wcreg |= RME96_WCR_MODE24;
 901                 break;
 902         default:
 903                 return -EINVAL;
 904         }
 905         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 906         return 0;
 907 }
 908
 909 static int
 910 snd_rme96_capture_setformat(struct rme96 *rme96,
 911                             int format)
 912 {
 913         switch (format) {
 914         case SNDRV_PCM_FORMAT_S16_LE:
 915                 rme96->wcreg &= ~RME96_WCR_MODE24_2;
 916                 break;
 917         case SNDRV_PCM_FORMAT_S32_LE:
 918                 rme96->wcreg |= RME96_WCR_MODE24_2;
 919                 break;
 920         default:
 921                 return -EINVAL;
 922         }
 923         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 924         return 0;
 925 }
 926
 927 static void
 928 snd_rme96_set_period_properties(struct rme96 *rme96,
 929                                 size_t period_bytes)
 930 {
 931         switch (period_bytes) {
 932         case RME96_LARGE_BLOCK_SIZE:
 933                 rme96->wcreg &= ~RME96_WCR_ISEL;
 934                 break;
 935         case RME96_SMALL_BLOCK_SIZE:
 936                 rme96->wcreg |= RME96_WCR_ISEL;
 937                 break;
 938         default:
 939                 snd_BUG();
 940                 break;
 941         }
 942         rme96->wcreg &= ~RME96_WCR_IDIS;
 943         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 944 }
 945
 946 static int
 947 snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
 948                              struct snd_pcm_hw_params *params)
 949 {
 950         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 951         struct snd_pcm_runtime *runtime = substream->runtime;
 952         int err, rate, dummy;
 953
 954         runtime->dma_area = (void __force *)(rme96->iobase +
 955                                              RME96_IO_PLAY_BUFFER);
 956         runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
 957         runtime->dma_bytes = RME96_BUFFER_SIZE;
 958
 959         spin_lock_irq(&rme96->lock);
 960         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
 961             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
 962             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
 963         {
 964                 /* slave clock */
 965                 if ((int)params_rate(params) != rate) {
 966                         spin_unlock_irq(&rme96->lock);
 967                         return -EIO;
 968                 }
 969         } else if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) {
 970                 spin_unlock_irq(&rme96->lock);
 971                 return err;
 972         }
 973         if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) {
 974                 spin_unlock_irq(&rme96->lock);
 975                 return err;
 976         }
 977         snd_rme96_setframelog(rme96, params_channels(params), 1);
 978         if (rme96->capture_periodsize != 0) {
 979                 if (params_period_size(params) << rme96->playback_frlog !=
 980                     rme96->capture_periodsize)
 981                 {
 982                         spin_unlock_irq(&rme96->lock);
 983                         return -EBUSY;
 984                 }
 985         }
 986         rme96->playback_periodsize =
 987                 params_period_size(params) << rme96->playback_frlog;
 988         snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
 989         /* S/PDIF setup */
 990         if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
 991                 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
 992                 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 993         }
 994         spin_unlock_irq(&rme96->lock);
 995
 996         return 0;
 997 }
 998
 999 static int
1000 snd_rme96_capture_hw_params(struct snd_pcm_substream *substream,
1001                             struct snd_pcm_hw_params *params)
1002 {
1003         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1004         struct snd_pcm_runtime *runtime = substream->runtime;
1005         int err, isadat, rate;
1006
1007         runtime->dma_area = (void __force *)(rme96->iobase +
1008                                              RME96_IO_REC_BUFFER);
1009         runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1010         runtime->dma_bytes = RME96_BUFFER_SIZE;
1011
1012         spin_lock_irq(&rme96->lock);
1013         if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1014                 spin_unlock_irq(&rme96->lock);
1015                 return err;
1016         }
1017         if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1018                 if ((err = snd_rme96_capture_analog_setrate(rme96,
1019                                                             params_rate(params))) < 0)
1020                 {
1021                         spin_unlock_irq(&rme96->lock);
1022                         return err;
1023                 }
1024         } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1025                 if ((int)params_rate(params) != rate) {
1026                         spin_unlock_irq(&rme96->lock);
1027                         return -EIO;
1028                 }
1029                 if ((isadat && runtime->hw.channels_min == 2) ||
1030                     (!isadat && runtime->hw.channels_min == 8))
1031                 {
1032                         spin_unlock_irq(&rme96->lock);
1033                         return -EIO;
1034                 }
1035         }
1036         snd_rme96_setframelog(rme96, params_channels(params), 0);
1037         if (rme96->playback_periodsize != 0) {
1038                 if (params_period_size(params) << rme96->capture_frlog !=
1039                     rme96->playback_periodsize)
1040                 {
1041                         spin_unlock_irq(&rme96->lock);
1042                         return -EBUSY;
1043                 }
1044         }
1045         rme96->capture_periodsize =
1046                 params_period_size(params) << rme96->capture_frlog;
1047         snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1048         spin_unlock_irq(&rme96->lock);
1049
1050         return 0;
1051 }
1052
1053 static void
1054 snd_rme96_playback_start(struct rme96 *rme96,
1055                          int from_pause)
1056 {
1057         if (!from_pause) {
1058                 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1059         }
1060
1061         rme96->wcreg |= RME96_WCR_START;
1062         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1063 }
1064
1065 static void
1066 snd_rme96_capture_start(struct rme96 *rme96,
1067                         int from_pause)
1068 {
1069         if (!from_pause) {
1070                 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1071         }
1072
1073         rme96->wcreg |= RME96_WCR_START_2;
1074         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1075 }
1076
1077 static void
1078 snd_rme96_playback_stop(struct rme96 *rme96)
1079 {
1080         /*
1081          * Check if there is an unconfirmed IRQ, if so confirm it, or else
1082          * the hardware will not stop generating interrupts
1083          */
1084         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1085         if (rme96->rcreg & RME96_RCR_IRQ) {
1086                 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1087         }
1088         rme96->wcreg &= ~RME96_WCR_START;
1089         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1090 }
1091
1092 static void
1093 snd_rme96_capture_stop(struct rme96 *rme96)
1094 {
1095         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1096         if (rme96->rcreg & RME96_RCR_IRQ_2) {
1097                 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1098         }
1099         rme96->wcreg &= ~RME96_WCR_START_2;
1100         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1101 }
1102
1103 static irqreturn_t
1104 snd_rme96_interrupt(int irq,
1105                     void *dev_id)
1106 {
1107         struct rme96 *rme96 = (struct rme96 *)dev_id;
1108
1109         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1110         /* fastpath out, to ease interrupt sharing */
1111         if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1112               (rme96->rcreg & RME96_RCR_IRQ_2)))
1113         {
1114                 return IRQ_NONE;
1115         }
1116
1117         if (rme96->rcreg & RME96_RCR_IRQ) {
1118                 /* playback */
1119                 snd_pcm_period_elapsed(rme96->playback_substream);
1120                 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1121         }
1122         if (rme96->rcreg & RME96_RCR_IRQ_2) {
1123                 /* capture */
1124                 snd_pcm_period_elapsed(rme96->capture_substream);
1125                 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1126         }
1127         return IRQ_HANDLED;
1128 }
1129
1130 static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1131
1132 static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
1133         .count = ARRAY_SIZE(period_bytes),
1134         .list = period_bytes,
1135         .mask = 0
1136 };
1137
1138 static void
1139 rme96_set_buffer_size_constraint(struct rme96 *rme96,
1140                                  struct snd_pcm_runtime *runtime)
1141 {
1142         unsigned int size;
1143
1144         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1145                                      RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1146         if ((size = rme96->playback_periodsize) != 0 ||
1147             (size = rme96->capture_periodsize) != 0)
1148                 snd_pcm_hw_constraint_minmax(runtime,
1149                                              SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1150                                              size, size);
1151         else
1152                 snd_pcm_hw_constraint_list(runtime, 0,
1153                                            SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1154                                            &hw_constraints_period_bytes);
1155 }
1156
1157 static int
1158 snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream)
1159 {
1160         int rate, dummy;
1161         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1162         struct snd_pcm_runtime *runtime = substream->runtime;
1163
1164         spin_lock_irq(&rme96->lock);
1165         if (rme96->playback_substream != NULL) {
1166                 spin_unlock_irq(&rme96->lock);
1167                 return -EBUSY;
1168         }
1169         rme96->wcreg &= ~RME96_WCR_ADAT;
1170         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1171         rme96->playback_substream = substream;
1172         spin_unlock_irq(&rme96->lock);
1173
1174         runtime->hw = snd_rme96_playback_spdif_info;
1175         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1176             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1177             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1178         {
1179                 /* slave clock */
1180                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1181                 runtime->hw.rate_min = rate;
1182                 runtime->hw.rate_max = rate;
1183         }
1184         rme96_set_buffer_size_constraint(rme96, runtime);
1185
1186         rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1187         rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1188         snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1189                        SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1190         return 0;
1191 }
1192
1193 static int
1194 snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream)
1195 {
1196         int isadat, rate;
1197         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1198         struct snd_pcm_runtime *runtime = substream->runtime;
1199
1200         runtime->hw = snd_rme96_capture_spdif_info;
1201         if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1202             (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1203         {
1204                 if (isadat) {
1205                         return -EIO;
1206                 }
1207                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1208                 runtime->hw.rate_min = rate;
1209                 runtime->hw.rate_max = rate;
1210         }
1211
1212         spin_lock_irq(&rme96->lock);
1213         if (rme96->capture_substream != NULL) {
1214                 spin_unlock_irq(&rme96->lock);
1215                 return -EBUSY;
1216         }
1217         rme96->capture_substream = substream;
1218         spin_unlock_irq(&rme96->lock);
1219
1220         rme96_set_buffer_size_constraint(rme96, runtime);
1221         return 0;
1222 }
1223
1224 static int
1225 snd_rme96_playback_adat_open(struct snd_pcm_substream *substream)
1226 {
1227         int rate, dummy;
1228         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1229         struct snd_pcm_runtime *runtime = substream->runtime;
1230
1231         spin_lock_irq(&rme96->lock);
1232         if (rme96->playback_substream != NULL) {
1233                 spin_unlock_irq(&rme96->lock);
1234                 return -EBUSY;
1235         }
1236         rme96->wcreg |= RME96_WCR_ADAT;
1237         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1238         rme96->playback_substream = substream;
1239         spin_unlock_irq(&rme96->lock);
1240
1241         runtime->hw = snd_rme96_playback_adat_info;
1242         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1243             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1244             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1245         {
1246                 /* slave clock */
1247                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1248                 runtime->hw.rate_min = rate;
1249                 runtime->hw.rate_max = rate;
1250         }
1251         rme96_set_buffer_size_constraint(rme96, runtime);
1252         return 0;
1253 }
1254
1255 static int
1256 snd_rme96_capture_adat_open(struct snd_pcm_substream *substream)
1257 {
1258         int isadat, rate;
1259         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1260         struct snd_pcm_runtime *runtime = substream->runtime;
1261
1262         runtime->hw = snd_rme96_capture_adat_info;
1263         if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1264                 /* makes no sense to use analog input. Note that analog
1265                    expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1266                 return -EIO;
1267         }
1268         if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1269                 if (!isadat) {
1270                         return -EIO;
1271                 }
1272                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1273                 runtime->hw.rate_min = rate;
1274                 runtime->hw.rate_max = rate;
1275         }
1276
1277         spin_lock_irq(&rme96->lock);
1278         if (rme96->capture_substream != NULL) {
1279                 spin_unlock_irq(&rme96->lock);
1280                 return -EBUSY;
1281         }
1282         rme96->capture_substream = substream;
1283         spin_unlock_irq(&rme96->lock);
1284
1285         rme96_set_buffer_size_constraint(rme96, runtime);
1286         return 0;
1287 }
1288
1289 static int
1290 snd_rme96_playback_close(struct snd_pcm_substream *substream)
1291 {
1292         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1293         int spdif = 0;
1294
1295         spin_lock_irq(&rme96->lock);
1296         if (RME96_ISPLAYING(rme96)) {
1297                 snd_rme96_playback_stop(rme96);
1298         }
1299         rme96->playback_substream = NULL;
1300         rme96->playback_periodsize = 0;
1301         spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1302         spin_unlock_irq(&rme96->lock);
1303         if (spdif) {
1304                 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1305                 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1306                                SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1307         }
1308         return 0;
1309 }
1310
1311 static int
1312 snd_rme96_capture_close(struct snd_pcm_substream *substream)
1313 {
1314         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1315
1316         spin_lock_irq(&rme96->lock);
1317         if (RME96_ISRECORDING(rme96)) {
1318                 snd_rme96_capture_stop(rme96);
1319         }
1320         rme96->capture_substream = NULL;
1321         rme96->capture_periodsize = 0;
1322         spin_unlock_irq(&rme96->lock);
1323         return 0;
1324 }
1325
1326 static int
1327 snd_rme96_playback_prepare(struct snd_pcm_substream *substream)
1328 {
1329         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1330
1331         spin_lock_irq(&rme96->lock);
1332         if (RME96_ISPLAYING(rme96)) {
1333                 snd_rme96_playback_stop(rme96);
1334         }
1335         writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1336         spin_unlock_irq(&rme96->lock);
1337         return 0;
1338 }
1339
1340 static int
1341 snd_rme96_capture_prepare(struct snd_pcm_substream *substream)
1342 {
1343         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1344
1345         spin_lock_irq(&rme96->lock);
1346         if (RME96_ISRECORDING(rme96)) {
1347                 snd_rme96_capture_stop(rme96);
1348         }
1349         writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1350         spin_unlock_irq(&rme96->lock);
1351         return 0;
1352 }
1353
1354 static int
1355 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1356                            int cmd)
1357 {
1358         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1359
1360         switch (cmd) {
1361         case SNDRV_PCM_TRIGGER_START:
1362                 if (!RME96_ISPLAYING(rme96)) {
1363                         if (substream != rme96->playback_substream) {
1364                                 return -EBUSY;
1365                         }
1366                         snd_rme96_playback_start(rme96, 0);
1367                 }
1368                 break;
1369
1370         case SNDRV_PCM_TRIGGER_STOP:
1371                 if (RME96_ISPLAYING(rme96)) {
1372                         if (substream != rme96->playback_substream) {
1373                                 return -EBUSY;
1374                         }
1375                         snd_rme96_playback_stop(rme96);
1376                 }
1377                 break;
1378
1379         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1380                 if (RME96_ISPLAYING(rme96)) {
1381                         snd_rme96_playback_stop(rme96);
1382                 }
1383                 break;
1384
1385         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1386                 if (!RME96_ISPLAYING(rme96)) {
1387                         snd_rme96_playback_start(rme96, 1);
1388                 }
1389                 break;
1390
1391         default:
1392                 return -EINVAL;
1393         }
1394         return 0;
1395 }
1396
1397 static int
1398 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1399                           int cmd)
1400 {
1401         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1402
1403         switch (cmd) {
1404         case SNDRV_PCM_TRIGGER_START:
1405                 if (!RME96_ISRECORDING(rme96)) {
1406                         if (substream != rme96->capture_substream) {
1407                                 return -EBUSY;
1408                         }
1409                         snd_rme96_capture_start(rme96, 0);
1410                 }
1411                 break;
1412
1413         case SNDRV_PCM_TRIGGER_STOP:
1414                 if (RME96_ISRECORDING(rme96)) {
1415                         if (substream != rme96->capture_substream) {
1416                                 return -EBUSY;
1417                         }
1418                         snd_rme96_capture_stop(rme96);
1419                 }
1420                 break;
1421
1422         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1423                 if (RME96_ISRECORDING(rme96)) {
1424                         snd_rme96_capture_stop(rme96);
1425                 }
1426                 break;
1427
1428         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1429                 if (!RME96_ISRECORDING(rme96)) {
1430                         snd_rme96_capture_start(rme96, 1);
1431                 }
1432                 break;
1433
1434         default:
1435                 return -EINVAL;
1436         }
1437
1438         return 0;
1439 }
1440
1441 static snd_pcm_uframes_t
1442 snd_rme96_playback_pointer(struct snd_pcm_substream *substream)
1443 {
1444         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1445         return snd_rme96_playback_ptr(rme96);
1446 }
1447
1448 static snd_pcm_uframes_t
1449 snd_rme96_capture_pointer(struct snd_pcm_substream *substream)
1450 {
1451         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1452         return snd_rme96_capture_ptr(rme96);
1453 }
1454
1455 static struct snd_pcm_ops snd_rme96_playback_spdif_ops = {
1456         .open =         snd_rme96_playback_spdif_open,
1457         .close =        snd_rme96_playback_close,
1458         .ioctl =        snd_pcm_lib_ioctl,
1459         .hw_params =    snd_rme96_playback_hw_params,
1460         .prepare =      snd_rme96_playback_prepare,
1461         .trigger =      snd_rme96_playback_trigger,
1462         .pointer =      snd_rme96_playback_pointer,
1463         .copy =         snd_rme96_playback_copy,
1464         .silence =      snd_rme96_playback_silence,
1465         .mmap =         snd_pcm_lib_mmap_iomem,
1466 };
1467
1468 static struct snd_pcm_ops snd_rme96_capture_spdif_ops = {
1469         .open =         snd_rme96_capture_spdif_open,
1470         .close =        snd_rme96_capture_close,
1471         .ioctl =        snd_pcm_lib_ioctl,
1472         .hw_params =    snd_rme96_capture_hw_params,
1473         .prepare =      snd_rme96_capture_prepare,
1474         .trigger =      snd_rme96_capture_trigger,
1475         .pointer =      snd_rme96_capture_pointer,
1476         .copy =         snd_rme96_capture_copy,
1477         .mmap =         snd_pcm_lib_mmap_iomem,
1478 };
1479
1480 static struct snd_pcm_ops snd_rme96_playback_adat_ops = {
1481         .open =         snd_rme96_playback_adat_open,
1482         .close =        snd_rme96_playback_close,
1483         .ioctl =        snd_pcm_lib_ioctl,
1484         .hw_params =    snd_rme96_playback_hw_params,
1485         .prepare =      snd_rme96_playback_prepare,
1486         .trigger =      snd_rme96_playback_trigger,
1487         .pointer =      snd_rme96_playback_pointer,
1488         .copy =         snd_rme96_playback_copy,
1489         .silence =      snd_rme96_playback_silence,
1490         .mmap =         snd_pcm_lib_mmap_iomem,
1491 };
1492
1493 static struct snd_pcm_ops snd_rme96_capture_adat_ops = {
1494         .open =         snd_rme96_capture_adat_open,
1495         .close =        snd_rme96_capture_close,
1496         .ioctl =        snd_pcm_lib_ioctl,
1497         .hw_params =    snd_rme96_capture_hw_params,
1498         .prepare =      snd_rme96_capture_prepare,
1499         .trigger =      snd_rme96_capture_trigger,
1500         .pointer =      snd_rme96_capture_pointer,
1501         .copy =         snd_rme96_capture_copy,
1502         .mmap =         snd_pcm_lib_mmap_iomem,
1503 };
1504
1505 static void
1506 snd_rme96_free(void *private_data)
1507 {
1508         struct rme96 *rme96 = (struct rme96 *)private_data;
1509
1510         if (rme96 == NULL) {
1511                 return;
1512         }
1513         if (rme96->irq >= 0) {
1514                 snd_rme96_playback_stop(rme96);
1515                 snd_rme96_capture_stop(rme96);
1516                 rme96->areg &= ~RME96_AR_DAC_EN;
1517                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1518                 free_irq(rme96->irq, (void *)rme96);
1519                 rme96->irq = -1;
1520         }
1521         if (rme96->iobase) {
1522                 iounmap(rme96->iobase);
1523                 rme96->iobase = NULL;
1524         }
1525         if (rme96->port) {
1526                 pci_release_regions(rme96->pci);
1527                 rme96->port = 0;
1528         }
1529         pci_disable_device(rme96->pci);
1530 }
1531
1532 static void
1533 snd_rme96_free_spdif_pcm(struct snd_pcm *pcm)
1534 {
1535         struct rme96 *rme96 = (struct rme96 *) pcm->private_data;
1536         rme96->spdif_pcm = NULL;
1537 }
1538
1539 static void
1540 snd_rme96_free_adat_pcm(struct snd_pcm *pcm)
1541 {
1542         struct rme96 *rme96 = (struct rme96 *) pcm->private_data;
1543         rme96->adat_pcm = NULL;
1544 }
1545
1546 static int __devinit
1547 snd_rme96_create(struct rme96 *rme96)
1548 {
1549         struct pci_dev *pci = rme96->pci;
1550         int err;
1551
1552         rme96->irq = -1;
1553         spin_lock_init(&rme96->lock);
1554
1555         if ((err = pci_enable_device(pci)) < 0)
1556                 return err;
1557
1558         if ((err = pci_request_regions(pci, "RME96")) < 0)
1559                 return err;
1560         rme96->port = pci_resource_start(rme96->pci, 0);
1561
1562         if ((rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE)) == 0) {
1563                 snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
1564                 return -ENOMEM;
1565         }
1566
1567         if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED,
1568                         "RME96", rme96)) {
1569                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1570                 return -EBUSY;
1571         }
1572         rme96->irq = pci->irq;
1573
1574         /* read the card's revision number */
1575         pci_read_config_byte(pci, 8, &rme96->rev);
1576
1577         /* set up ALSA pcm device for S/PDIF */
1578         if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1579                                1, 1, &rme96->spdif_pcm)) < 0)
1580         {
1581                 return err;
1582         }
1583         rme96->spdif_pcm->private_data = rme96;
1584         rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1585         strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1586         snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1587         snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1588
1589         rme96->spdif_pcm->info_flags = 0;
1590
1591         /* set up ALSA pcm device for ADAT */
1592         if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
1593                 /* ADAT is not available on the base model */
1594                 rme96->adat_pcm = NULL;
1595         } else {
1596                 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1597                                        1, 1, &rme96->adat_pcm)) < 0)
1598                 {
1599                         return err;
1600                 }
1601                 rme96->adat_pcm->private_data = rme96;
1602                 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1603                 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1604                 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1605                 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1606
1607                 rme96->adat_pcm->info_flags = 0;
1608         }
1609
1610         rme96->playback_periodsize = 0;
1611         rme96->capture_periodsize = 0;
1612
1613         /* make sure playback/capture is stopped, if by some reason active */
1614         snd_rme96_playback_stop(rme96);
1615         snd_rme96_capture_stop(rme96);
1616
1617         /* set default values in registers */
1618         rme96->wcreg =
1619                 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1620                 RME96_WCR_SEL |    /* normal playback */
1621                 RME96_WCR_MASTER | /* set to master clock mode */
1622                 RME96_WCR_INP_0;   /* set coaxial input */
1623
1624         rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1625
1626         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1627         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1628
1629         /* reset the ADC */
1630         writel(rme96->areg | RME96_AR_PD2,
1631                rme96->iobase + RME96_IO_ADDITIONAL_REG);
1632         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1633
1634         /* reset and enable the DAC (order is important). */
1635         snd_rme96_reset_dac(rme96);
1636         rme96->areg |= RME96_AR_DAC_EN;
1637         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1638
1639         /* reset playback and record buffer pointers */
1640         writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1641         writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1642
1643         /* reset volume */
1644         rme96->vol[0] = rme96->vol[1] = 0;
1645         if (RME96_HAS_ANALOG_OUT(rme96)) {
1646                 snd_rme96_apply_dac_volume(rme96);
1647         }
1648
1649         /* init switch interface */
1650         if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1651                 return err;
1652         }
1653
1654         /* init proc interface */
1655         snd_rme96_proc_init(rme96);
1656
1657         return 0;
1658 }
1659
1660 /*
1661  * proc interface
1662  */
1663
1664 static void
1665 snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1666 {
1667         int n;
1668         struct rme96 *rme96 = (struct rme96 *)entry->private_data;
1669
1670         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1671
1672         snd_iprintf(buffer, rme96->card->longname);
1673         snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1674
1675         snd_iprintf(buffer, "\nGeneral settings\n");
1676         if (rme96->wcreg & RME96_WCR_IDIS) {
1677                 snd_iprintf(buffer, "  period size: N/A (interrupts "
1678                             "disabled)\n");
1679         } else if (rme96->wcreg & RME96_WCR_ISEL) {
1680                 snd_iprintf(buffer, "  period size: 2048 bytes\n");
1681         } else {
1682                 snd_iprintf(buffer, "  period size: 8192 bytes\n");
1683         }
1684         snd_iprintf(buffer, "\nInput settings\n");
1685         switch (snd_rme96_getinputtype(rme96)) {
1686         case RME96_INPUT_OPTICAL:
1687                 snd_iprintf(buffer, "  input: optical");
1688                 break;
1689         case RME96_INPUT_COAXIAL:
1690                 snd_iprintf(buffer, "  input: coaxial");
1691                 break;
1692         case RME96_INPUT_INTERNAL:
1693                 snd_iprintf(buffer, "  input: internal");
1694                 break;
1695         case RME96_INPUT_XLR:
1696                 snd_iprintf(buffer, "  input: XLR");
1697                 break;
1698         case RME96_INPUT_ANALOG:
1699                 snd_iprintf(buffer, "  input: analog");
1700                 break;
1701         }
1702         if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1703                 snd_iprintf(buffer, "\n  sample rate: no valid signal\n");
1704         } else {
1705                 if (n) {
1706                         snd_iprintf(buffer, " (8 channels)\n");
1707                 } else {
1708                         snd_iprintf(buffer, " (2 channels)\n");
1709                 }
1710                 snd_iprintf(buffer, "  sample rate: %d Hz\n",
1711                             snd_rme96_capture_getrate(rme96, &n));
1712         }
1713         if (rme96->wcreg & RME96_WCR_MODE24_2) {
1714                 snd_iprintf(buffer, "  sample format: 24 bit\n");
1715         } else {
1716                 snd_iprintf(buffer, "  sample format: 16 bit\n");
1717         }
1718
1719         snd_iprintf(buffer, "\nOutput settings\n");
1720         if (rme96->wcreg & RME96_WCR_SEL) {
1721                 snd_iprintf(buffer, "  output signal: normal playback\n");
1722         } else {
1723                 snd_iprintf(buffer, "  output signal: same as input\n");
1724         }
1725         snd_iprintf(buffer, "  sample rate: %d Hz\n",
1726                     snd_rme96_playback_getrate(rme96));
1727         if (rme96->wcreg & RME96_WCR_MODE24) {
1728                 snd_iprintf(buffer, "  sample format: 24 bit\n");
1729         } else {
1730                 snd_iprintf(buffer, "  sample format: 16 bit\n");
1731         }
1732         if (rme96->areg & RME96_AR_WSEL) {
1733                 snd_iprintf(buffer, "  sample clock source: word clock\n");
1734         } else if (rme96->wcreg & RME96_WCR_MASTER) {
1735                 snd_iprintf(buffer, "  sample clock source: internal\n");
1736         } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1737                 snd_iprintf(buffer, "  sample clock source: autosync (internal anyway due to analog input setting)\n");
1738         } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1739                 snd_iprintf(buffer, "  sample clock source: autosync (internal anyway due to no valid signal)\n");
1740         } else {
1741                 snd_iprintf(buffer, "  sample clock source: autosync\n");
1742         }
1743         if (rme96->wcreg & RME96_WCR_PRO) {
1744                 snd_iprintf(buffer, "  format: AES/EBU (professional)\n");
1745         } else {
1746                 snd_iprintf(buffer, "  format: IEC958 (consumer)\n");
1747         }
1748         if (rme96->wcreg & RME96_WCR_EMP) {
1749                 snd_iprintf(buffer, "  emphasis: on\n");
1750         } else {
1751                 snd_iprintf(buffer, "  emphasis: off\n");
1752         }
1753         if (rme96->wcreg & RME96_WCR_DOLBY) {
1754                 snd_iprintf(buffer, "  non-audio (dolby): on\n");
1755         } else {
1756                 snd_iprintf(buffer, "  non-audio (dolby): off\n");
1757         }
1758         if (RME96_HAS_ANALOG_IN(rme96)) {
1759                 snd_iprintf(buffer, "\nAnalog output settings\n");
1760                 switch (snd_rme96_getmontracks(rme96)) {
1761                 case RME96_MONITOR_TRACKS_1_2:
1762                         snd_iprintf(buffer, "  monitored ADAT tracks: 1+2\n");
1763                         break;
1764                 case RME96_MONITOR_TRACKS_3_4:
1765                         snd_iprintf(buffer, "  monitored ADAT tracks: 3+4\n");
1766                         break;
1767                 case RME96_MONITOR_TRACKS_5_6:
1768                         snd_iprintf(buffer, "  monitored ADAT tracks: 5+6\n");
1769                         break;
1770                 case RME96_MONITOR_TRACKS_7_8:
1771                         snd_iprintf(buffer, "  monitored ADAT tracks: 7+8\n");
1772                         break;
1773                 }
1774                 switch (snd_rme96_getattenuation(rme96)) {
1775                 case RME96_ATTENUATION_0:
1776                         snd_iprintf(buffer, "  attenuation: 0 dB\n");
1777                         break;
1778                 case RME96_ATTENUATION_6:
1779                         snd_iprintf(buffer, "  attenuation: -6 dB\n");
1780                         break;
1781                 case RME96_ATTENUATION_12:
1782                         snd_iprintf(buffer, "  attenuation: -12 dB\n");
1783                         break;
1784                 case RME96_ATTENUATION_18:
1785                         snd_iprintf(buffer, "  attenuation: -18 dB\n");
1786                         break;
1787                 }
1788                 snd_iprintf(buffer, "  volume left: %u\n", rme96->vol[0]);
1789                 snd_iprintf(buffer, "  volume right: %u\n", rme96->vol[1]);
1790         }
1791 }
1792
1793 static void __devinit
1794 snd_rme96_proc_init(struct rme96 *rme96)
1795 {
1796         struct snd_info_entry *entry;
1797
1798         if (! snd_card_proc_new(rme96->card, "rme96", &entry))
1799                 snd_info_set_text_ops(entry, rme96, snd_rme96_proc_read);
1800 }
1801
1802 /*
1803  * control interface
1804  */
1805
1806 #define snd_rme96_info_loopback_control         snd_ctl_boolean_mono_info
1807
1808 static int
1809 snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1810 {
1811         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1812
1813         spin_lock_irq(&rme96->lock);
1814         ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1815         spin_unlock_irq(&rme96->lock);
1816         return 0;
1817 }
1818 static int
1819 snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1820 {
1821         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1822         unsigned int val;
1823         int change;
1824
1825         val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1826         spin_lock_irq(&rme96->lock);
1827         val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1828         change = val != rme96->wcreg;
1829         rme96->wcreg = val;
1830         writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1831         spin_unlock_irq(&rme96->lock);
1832         return change;
1833 }
1834
1835 static int
1836 snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1837 {
1838         static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
1839         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1840         char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] };
1841
1842         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1843         uinfo->count = 1;
1844         switch (rme96->pci->device) {
1845         case PCI_DEVICE_ID_RME_DIGI96:
1846         case PCI_DEVICE_ID_RME_DIGI96_8:
1847                 uinfo->value.enumerated.items = 3;
1848                 break;
1849         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1850                 uinfo->value.enumerated.items = 4;
1851                 break;
1852         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1853                 if (rme96->rev > 4) {
1854                         /* PST */
1855                         uinfo->value.enumerated.items = 4;
1856                         texts[3] = _texts[4]; /* Analog instead of XLR */
1857                 } else {
1858                         /* PAD */
1859                         uinfo->value.enumerated.items = 5;
1860                 }
1861                 break;
1862         default:
1863                 snd_BUG();
1864                 break;
1865         }
1866         if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) {
1867                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1868         }
1869         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1870         return 0;
1871 }
1872 static int
1873 snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1874 {
1875         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1876         unsigned int items = 3;
1877
1878         spin_lock_irq(&rme96->lock);
1879         ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1880
1881         switch (rme96->pci->device) {
1882         case PCI_DEVICE_ID_RME_DIGI96:
1883         case PCI_DEVICE_ID_RME_DIGI96_8:
1884                 items = 3;
1885                 break;
1886         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1887                 items = 4;
1888                 break;
1889         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1890                 if (rme96->rev > 4) {
1891                         /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1892                         if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1893                                 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1894                         }
1895                         items = 4;
1896                 } else {
1897                         items = 5;
1898                 }
1899                 break;
1900         default:
1901                 snd_BUG();
1902                 break;
1903         }
1904         if (ucontrol->value.enumerated.item[0] >= items) {
1905                 ucontrol->value.enumerated.item[0] = items - 1;
1906         }
1907
1908         spin_unlock_irq(&rme96->lock);
1909         return 0;
1910 }
1911 static int
1912 snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1913 {
1914         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1915         unsigned int val;
1916         int change, items = 3;
1917
1918         switch (rme96->pci->device) {
1919         case PCI_DEVICE_ID_RME_DIGI96:
1920         case PCI_DEVICE_ID_RME_DIGI96_8:
1921                 items = 3;
1922                 break;
1923         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1924                 items = 4;
1925                 break;
1926         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1927                 if (rme96->rev > 4) {
1928                         items = 4;
1929                 } else {
1930                         items = 5;
1931                 }
1932                 break;
1933         default:
1934                 snd_BUG();
1935                 break;
1936         }
1937         val = ucontrol->value.enumerated.item[0] % items;
1938
1939         /* special case for PST */
1940         if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
1941                 if (val == RME96_INPUT_XLR) {
1942                         val = RME96_INPUT_ANALOG;
1943                 }
1944         }
1945
1946         spin_lock_irq(&rme96->lock);
1947         change = (int)val != snd_rme96_getinputtype(rme96);
1948         snd_rme96_setinputtype(rme96, val);
1949         spin_unlock_irq(&rme96->lock);
1950         return change;
1951 }
1952
1953 static int
1954 snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1955 {
1956         static char *texts[3] = { "AutoSync", "Internal", "Word" };
1957
1958         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1959         uinfo->count = 1;
1960         uinfo->value.enumerated.items = 3;
1961         if (uinfo->value.enumerated.item > 2) {
1962                 uinfo->value.enumerated.item = 2;
1963         }
1964         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1965         return 0;
1966 }
1967 static int
1968 snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1969 {
1970         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1971
1972         spin_lock_irq(&rme96->lock);
1973         ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
1974         spin_unlock_irq(&rme96->lock);
1975         return 0;
1976 }
1977 static int
1978 snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1979 {
1980         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1981         unsigned int val;
1982         int change;
1983
1984         val = ucontrol->value.enumerated.item[0] % 3;
1985         spin_lock_irq(&rme96->lock);
1986         change = (int)val != snd_rme96_getclockmode(rme96);
1987         snd_rme96_setclockmode(rme96, val);
1988         spin_unlock_irq(&rme96->lock);
1989         return change;
1990 }
1991
1992 static int
1993 snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1994 {
1995         static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
1996
1997         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1998         uinfo->count = 1;
1999         uinfo->value.enumerated.items = 4;
2000         if (uinfo->value.enumerated.item > 3) {
2001                 uinfo->value.enumerated.item = 3;
2002         }
2003         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2004         return 0;
2005 }
2006 static int
2007 snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2008 {
2009         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2010
2011         spin_lock_irq(&rme96->lock);
2012         ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2013         spin_unlock_irq(&rme96->lock);
2014         return 0;
2015 }
2016 static int
2017 snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2018 {
2019         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2020         unsigned int val;
2021         int change;
2022
2023         val = ucontrol->value.enumerated.item[0] % 4;
2024         spin_lock_irq(&rme96->lock);
2025
2026         change = (int)val != snd_rme96_getattenuation(rme96);
2027         snd_rme96_setattenuation(rme96, val);
2028         spin_unlock_irq(&rme96->lock);
2029         return change;
2030 }
2031
2032 static int
2033 snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2034 {
2035         static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2036
2037         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2038         uinfo->count = 1;
2039         uinfo->value.enumerated.items = 4;
2040         if (uinfo->value.enumerated.item > 3) {
2041                 uinfo->value.enumerated.item = 3;
2042         }
2043         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2044         return 0;
2045 }
2046 static int
2047 snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2048 {
2049         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2050
2051         spin_lock_irq(&rme96->lock);
2052         ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2053         spin_unlock_irq(&rme96->lock);
2054         return 0;
2055 }
2056 static int
2057 snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2058 {
2059         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2060         unsigned int val;
2061         int change;
2062
2063         val = ucontrol->value.enumerated.item[0] % 4;
2064         spin_lock_irq(&rme96->lock);
2065         change = (int)val != snd_rme96_getmontracks(rme96);
2066         snd_rme96_setmontracks(rme96, val);
2067         spin_unlock_irq(&rme96->lock);
2068         return change;
2069 }
2070
2071 static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes)
2072 {
2073         u32 val = 0;
2074         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2075         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2076         if (val & RME96_WCR_PRO)
2077                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2078         else
2079                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2080         return val;
2081 }
2082
2083 static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
2084 {
2085         aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2086                          ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2087         if (val & RME96_WCR_PRO)
2088                 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2089         else
2090                 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2091 }
2092
2093 static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2094 {
2095         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2096         uinfo->count = 1;
2097         return 0;
2098 }
2099
2100 static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2101 {
2102         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2103
2104         snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2105         return 0;
2106 }
2107
2108 static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2109 {
2110         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2111         int change;
2112         u32 val;
2113
2114         val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2115         spin_lock_irq(&rme96->lock);
2116         change = val != rme96->wcreg_spdif;
2117         rme96->wcreg_spdif = val;
2118         spin_unlock_irq(&rme96->lock);
2119         return change;
2120 }
2121
2122 static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2123 {
2124         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2125         uinfo->count = 1;
2126         return 0;
2127 }
2128
2129 static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2130 {
2131         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2132
2133         snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2134         return 0;
2135 }
2136
2137 static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2138 {
2139         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2140         int change;
2141         u32 val;
2142
2143         val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2144         spin_lock_irq(&rme96->lock);
2145         change = val != rme96->wcreg_spdif_stream;
2146         rme96->wcreg_spdif_stream = val;
2147         rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2148         rme96->wcreg |= val;
2149         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2150         spin_unlock_irq(&rme96->lock);
2151         return change;
2152 }
2153
2154 static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2155 {
2156         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2157         uinfo->count = 1;
2158         return 0;
2159 }
2160
2161 static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2162 {
2163         ucontrol->value.iec958.status[0] = kcontrol->private_value;
2164         return 0;
2165 }
2166
2167 static int
2168 snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2169 {
2170         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2171
2172         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2173         uinfo->count = 2;
2174         uinfo->value.integer.min = 0;
2175         uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2176         return 0;
2177 }
2178
2179 static int
2180 snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2181 {
2182         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2183
2184         spin_lock_irq(&rme96->lock);
2185         u->value.integer.value[0] = rme96->vol[0];
2186         u->value.integer.value[1] = rme96->vol[1];
2187         spin_unlock_irq(&rme96->lock);
2188
2189         return 0;
2190 }
2191
2192 static int
2193 snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2194 {
2195         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2196         int change = 0;
2197         unsigned int vol, maxvol;
2198
2199
2200         if (!RME96_HAS_ANALOG_OUT(rme96))
2201                 return -EINVAL;
2202         maxvol = RME96_185X_MAX_OUT(rme96);
2203         spin_lock_irq(&rme96->lock);
2204         vol = u->value.integer.value[0];
2205         if (vol != rme96->vol[0] && vol <= maxvol) {
2206                 rme96->vol[0] = vol;
2207                 change = 1;
2208         }
2209         vol = u->value.integer.value[1];
2210         if (vol != rme96->vol[1] && vol <= maxvol) {
2211                 rme96->vol[1] = vol;
2212                 change = 1;
2213         }
2214         if (change)
2215                 snd_rme96_apply_dac_volume(rme96);
2216         spin_unlock_irq(&rme96->lock);
2217
2218         return change;
2219 }
2220
2221 static struct snd_kcontrol_new snd_rme96_controls[] = {
2222 {
2223         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2224         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2225         .info =         snd_rme96_control_spdif_info,
2226         .get =          snd_rme96_control_spdif_get,
2227         .put =          snd_rme96_control_spdif_put
2228 },
2229 {
2230         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2231         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2232         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2233         .info =         snd_rme96_control_spdif_stream_info,
2234         .get =          snd_rme96_control_spdif_stream_get,
2235         .put =          snd_rme96_control_spdif_stream_put
2236 },
2237 {
2238         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2239         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2240         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2241         .info =         snd_rme96_control_spdif_mask_info,
2242         .get =          snd_rme96_control_spdif_mask_get,
2243         .private_value = IEC958_AES0_NONAUDIO |
2244                         IEC958_AES0_PROFESSIONAL |
2245                         IEC958_AES0_CON_EMPHASIS
2246 },
2247 {
2248         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2249         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2250         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2251         .info =         snd_rme96_control_spdif_mask_info,
2252         .get =          snd_rme96_control_spdif_mask_get,
2253         .private_value = IEC958_AES0_NONAUDIO |
2254                         IEC958_AES0_PROFESSIONAL |
2255                         IEC958_AES0_PRO_EMPHASIS
2256 },
2257 {
2258         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2259         .name =         "Input Connector",
2260         .info =         snd_rme96_info_inputtype_control,
2261         .get =          snd_rme96_get_inputtype_control,
2262         .put =          snd_rme96_put_inputtype_control
2263 },
2264 {
2265         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2266         .name =         "Loopback Input",
2267         .info =         snd_rme96_info_loopback_control,
2268         .get =          snd_rme96_get_loopback_control,
2269         .put =          snd_rme96_put_loopback_control
2270 },
2271 {
2272         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2273         .name =         "Sample Clock Source",
2274         .info =         snd_rme96_info_clockmode_control,
2275         .get =          snd_rme96_get_clockmode_control,
2276         .put =          snd_rme96_put_clockmode_control
2277 },
2278 {
2279         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2280         .name =         "Monitor Tracks",
2281         .info =         snd_rme96_info_montracks_control,
2282         .get =          snd_rme96_get_montracks_control,
2283         .put =          snd_rme96_put_montracks_control
2284 },
2285 {
2286         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2287         .name =         "Attenuation",
2288         .info =         snd_rme96_info_attenuation_control,
2289         .get =          snd_rme96_get_attenuation_control,
2290         .put =          snd_rme96_put_attenuation_control
2291 },
2292 {
2293         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2294         .name =         "DAC Playback Volume",
2295         .info =         snd_rme96_dac_volume_info,
2296         .get =          snd_rme96_dac_volume_get,
2297         .put =          snd_rme96_dac_volume_put
2298 }
2299 };
2300
2301 static int
2302 snd_rme96_create_switches(struct snd_card *card,
2303                           struct rme96 *rme96)
2304 {
2305         int idx, err;
2306         struct snd_kcontrol *kctl;
2307
2308         for (idx = 0; idx < 7; idx++) {
2309                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2310                         return err;
2311                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
2312                         rme96->spdif_ctl = kctl;
2313         }
2314
2315         if (RME96_HAS_ANALOG_OUT(rme96)) {
2316                 for (idx = 7; idx < 10; idx++)
2317                         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2318                                 return err;
2319         }
2320
2321         return 0;
2322 }
2323
2324 /*
2325  * Card initialisation
2326  */
2327
2328 static void snd_rme96_card_free(struct snd_card *card)
2329 {
2330         snd_rme96_free(card->private_data);
2331 }
2332
2333 static int __devinit
2334 snd_rme96_probe(struct pci_dev *pci,
2335                 const struct pci_device_id *pci_id)
2336 {
2337         static int dev;
2338         struct rme96 *rme96;
2339         struct snd_card *card;
2340         int err;
2341         u8 val;
2342
2343         if (dev >= SNDRV_CARDS) {
2344                 return -ENODEV;
2345         }
2346         if (!enable[dev]) {
2347                 dev++;
2348                 return -ENOENT;
2349         }
2350         if ((card = snd_card_new(index[dev], id[dev], THIS_MODULE,
2351                                  sizeof(struct rme96))) == NULL)
2352                 return -ENOMEM;
2353         card->private_free = snd_rme96_card_free;
2354         rme96 = (struct rme96 *)card->private_data;
2355         rme96->card = card;
2356         rme96->pci = pci;
2357         snd_card_set_dev(card, &pci->dev);
2358         if ((err = snd_rme96_create(rme96)) < 0) {
2359                 snd_card_free(card);
2360                 return err;
2361         }
2362
2363         strcpy(card->driver, "Digi96");
2364         switch (rme96->pci->device) {
2365         case PCI_DEVICE_ID_RME_DIGI96:
2366                 strcpy(card->shortname, "RME Digi96");
2367                 break;
2368         case PCI_DEVICE_ID_RME_DIGI96_8:
2369                 strcpy(card->shortname, "RME Digi96/8");
2370                 break;
2371         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
2372                 strcpy(card->shortname, "RME Digi96/8 PRO");
2373                 break;
2374         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
2375                 pci_read_config_byte(rme96->pci, 8, &val);
2376                 if (val < 5) {
2377                         strcpy(card->shortname, "RME Digi96/8 PAD");
2378                 } else {
2379                         strcpy(card->shortname, "RME Digi96/8 PST");
2380                 }
2381                 break;
2382         }
2383         sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2384                 rme96->port, rme96->irq);
2385
2386         if ((err = snd_card_register(card)) < 0) {
2387                 snd_card_free(card);
2388                 return err;
2389         }
2390         pci_set_drvdata(pci, card);
2391         dev++;
2392         return 0;
2393 }
2394
2395 static void __devexit snd_rme96_remove(struct pci_dev *pci)
2396 {
2397         snd_card_free(pci_get_drvdata(pci));
2398         pci_set_drvdata(pci, NULL);
2399 }
2400
2401 static struct pci_driver driver = {
2402         .name = "RME Digi96",
2403         .id_table = snd_rme96_ids,
2404         .probe = snd_rme96_probe,
2405         .remove = __devexit_p(snd_rme96_remove),
2406 };
2407
2408 static int __init alsa_card_rme96_init(void)
2409 {
2410         return pci_register_driver(&driver);
2411 }
2412
2413 static void __exit alsa_card_rme96_exit(void)
2414 {
2415         pci_unregister_driver(&driver);
2416 }
2417
2418 module_init(alsa_card_rme96_init)
2419 module_exit(alsa_card_rme96_exit)