git.oblomov.eu Git - linux-2.6/blob - drivers/video/ffb.c

   1 /* ffb.c: Creator/Elite3D frame buffer driver
   2  *
   3  * Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net)
   4  * Copyright (C) 1997,1998,1999 Jakub Jelinek (jj@ultra.linux.cz)
   5  *
   6  * Driver layout based loosely on tgafb.c, see that file for credits.
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/kernel.h>
  11 #include <linux/errno.h>
  12 #include <linux/string.h>
  13 #include <linux/slab.h>
  14 #include <linux/delay.h>
  15 #include <linux/init.h>
  16 #include <linux/fb.h>
  17 #include <linux/mm.h>
  18 #include <linux/timer.h>
  19
  20 #include <asm/io.h>
  21 #include <asm/upa.h>
  22 #include <asm/prom.h>
  23 #include <asm/of_device.h>
  24 #include <asm/fbio.h>
  25
  26 #include "sbuslib.h"
  27
  28 /*
  29  * Local functions.
  30  */
  31
  32 static int ffb_setcolreg(unsigned, unsigned, unsigned, unsigned,
  33                          unsigned, struct fb_info *);
  34 static int ffb_blank(int, struct fb_info *);
  35 static void ffb_init_fix(struct fb_info *);
  36
  37 static void ffb_imageblit(struct fb_info *, const struct fb_image *);
  38 static void ffb_fillrect(struct fb_info *, const struct fb_fillrect *);
  39 static void ffb_copyarea(struct fb_info *, const struct fb_copyarea *);
  40 static int ffb_sync(struct fb_info *);
  41 static int ffb_mmap(struct fb_info *, struct vm_area_struct *);
  42 static int ffb_ioctl(struct fb_info *, unsigned int, unsigned long);
  43 static int ffb_pan_display(struct fb_var_screeninfo *, struct fb_info *);
  44
  45 /*
  46  *  Frame buffer operations
  47  */
  48
  49 static struct fb_ops ffb_ops = {
  50         .owner                  = THIS_MODULE,
  51         .fb_setcolreg           = ffb_setcolreg,
  52         .fb_blank               = ffb_blank,
  53         .fb_pan_display         = ffb_pan_display,
  54         .fb_fillrect            = ffb_fillrect,
  55         .fb_copyarea            = ffb_copyarea,
  56         .fb_imageblit           = ffb_imageblit,
  57         .fb_sync                = ffb_sync,
  58         .fb_mmap                = ffb_mmap,
  59         .fb_ioctl               = ffb_ioctl,
  60 #ifdef CONFIG_COMPAT
  61         .fb_compat_ioctl        = sbusfb_compat_ioctl,
  62 #endif
  63 };
  64
  65 /* Register layout and definitions */
  66 #define FFB_SFB8R_VOFF          0x00000000
  67 #define FFB_SFB8G_VOFF          0x00400000
  68 #define FFB_SFB8B_VOFF          0x00800000
  69 #define FFB_SFB8X_VOFF          0x00c00000
  70 #define FFB_SFB32_VOFF          0x01000000
  71 #define FFB_SFB64_VOFF          0x02000000
  72 #define FFB_FBC_REGS_VOFF       0x04000000
  73 #define FFB_BM_FBC_REGS_VOFF    0x04002000
  74 #define FFB_DFB8R_VOFF          0x04004000
  75 #define FFB_DFB8G_VOFF          0x04404000
  76 #define FFB_DFB8B_VOFF          0x04804000
  77 #define FFB_DFB8X_VOFF          0x04c04000
  78 #define FFB_DFB24_VOFF          0x05004000
  79 #define FFB_DFB32_VOFF          0x06004000
  80 #define FFB_DFB422A_VOFF        0x07004000      /* DFB 422 mode write to A */
  81 #define FFB_DFB422AD_VOFF       0x07804000      /* DFB 422 mode with line doubling */
  82 #define FFB_DFB24B_VOFF         0x08004000      /* DFB 24bit mode write to B */
  83 #define FFB_DFB422B_VOFF        0x09004000      /* DFB 422 mode write to B */
  84 #define FFB_DFB422BD_VOFF       0x09804000      /* DFB 422 mode with line doubling */
  85 #define FFB_SFB16Z_VOFF         0x0a004000      /* 16bit mode Z planes */
  86 #define FFB_SFB8Z_VOFF          0x0a404000      /* 8bit mode Z planes */
  87 #define FFB_SFB422_VOFF         0x0ac04000      /* SFB 422 mode write to A/B */
  88 #define FFB_SFB422D_VOFF        0x0b404000      /* SFB 422 mode with line doubling */
  89 #define FFB_FBC_KREGS_VOFF      0x0bc04000
  90 #define FFB_DAC_VOFF            0x0bc06000
  91 #define FFB_PROM_VOFF           0x0bc08000
  92 #define FFB_EXP_VOFF            0x0bc18000
  93
  94 #define FFB_SFB8R_POFF          0x04000000UL
  95 #define FFB_SFB8G_POFF          0x04400000UL
  96 #define FFB_SFB8B_POFF          0x04800000UL
  97 #define FFB_SFB8X_POFF          0x04c00000UL
  98 #define FFB_SFB32_POFF          0x05000000UL
  99 #define FFB_SFB64_POFF          0x06000000UL
 100 #define FFB_FBC_REGS_POFF       0x00600000UL
 101 #define FFB_BM_FBC_REGS_POFF    0x00600000UL
 102 #define FFB_DFB8R_POFF          0x01000000UL
 103 #define FFB_DFB8G_POFF          0x01400000UL
 104 #define FFB_DFB8B_POFF          0x01800000UL
 105 #define FFB_DFB8X_POFF          0x01c00000UL
 106 #define FFB_DFB24_POFF          0x02000000UL
 107 #define FFB_DFB32_POFF          0x03000000UL
 108 #define FFB_FBC_KREGS_POFF      0x00610000UL
 109 #define FFB_DAC_POFF            0x00400000UL
 110 #define FFB_PROM_POFF           0x00000000UL
 111 #define FFB_EXP_POFF            0x00200000UL
 112 #define FFB_DFB422A_POFF        0x09000000UL
 113 #define FFB_DFB422AD_POFF       0x09800000UL
 114 #define FFB_DFB24B_POFF         0x0a000000UL
 115 #define FFB_DFB422B_POFF        0x0b000000UL
 116 #define FFB_DFB422BD_POFF       0x0b800000UL
 117 #define FFB_SFB16Z_POFF         0x0c800000UL
 118 #define FFB_SFB8Z_POFF          0x0c000000UL
 119 #define FFB_SFB422_POFF         0x0d000000UL
 120 #define FFB_SFB422D_POFF        0x0d800000UL
 121
 122 /* Draw operations */
 123 #define FFB_DRAWOP_DOT          0x00
 124 #define FFB_DRAWOP_AADOT        0x01
 125 #define FFB_DRAWOP_BRLINECAP    0x02
 126 #define FFB_DRAWOP_BRLINEOPEN   0x03
 127 #define FFB_DRAWOP_DDLINE       0x04
 128 #define FFB_DRAWOP_AALINE       0x05
 129 #define FFB_DRAWOP_TRIANGLE     0x06
 130 #define FFB_DRAWOP_POLYGON      0x07
 131 #define FFB_DRAWOP_RECTANGLE    0x08
 132 #define FFB_DRAWOP_FASTFILL     0x09
 133 #define FFB_DRAWOP_BCOPY        0x0a
 134 #define FFB_DRAWOP_VSCROLL      0x0b
 135
 136 /* Pixel processor control */
 137 /* Force WID */
 138 #define FFB_PPC_FW_DISABLE      0x800000
 139 #define FFB_PPC_FW_ENABLE       0xc00000
 140 /* Auxiliary clip */
 141 #define FFB_PPC_ACE_DISABLE     0x040000
 142 #define FFB_PPC_ACE_AUX_SUB     0x080000
 143 #define FFB_PPC_ACE_AUX_ADD     0x0c0000
 144 /* Depth cue */
 145 #define FFB_PPC_DCE_DISABLE     0x020000
 146 #define FFB_PPC_DCE_ENABLE      0x030000
 147 /* Alpha blend */
 148 #define FFB_PPC_ABE_DISABLE     0x008000
 149 #define FFB_PPC_ABE_ENABLE      0x00c000
 150 /* View clip */
 151 #define FFB_PPC_VCE_DISABLE     0x001000
 152 #define FFB_PPC_VCE_2D          0x002000
 153 #define FFB_PPC_VCE_3D          0x003000
 154 /* Area pattern */
 155 #define FFB_PPC_APE_DISABLE     0x000800
 156 #define FFB_PPC_APE_ENABLE      0x000c00
 157 /* Transparent background */
 158 #define FFB_PPC_TBE_OPAQUE      0x000200
 159 #define FFB_PPC_TBE_TRANSPARENT 0x000300
 160 /* Z source */
 161 #define FFB_PPC_ZS_VAR          0x000080
 162 #define FFB_PPC_ZS_CONST        0x0000c0
 163 /* Y source */
 164 #define FFB_PPC_YS_VAR          0x000020
 165 #define FFB_PPC_YS_CONST        0x000030
 166 /* X source */
 167 #define FFB_PPC_XS_WID          0x000004
 168 #define FFB_PPC_XS_VAR          0x000008
 169 #define FFB_PPC_XS_CONST        0x00000c
 170 /* Color (BGR) source */
 171 #define FFB_PPC_CS_VAR          0x000002
 172 #define FFB_PPC_CS_CONST        0x000003
 173
 174 #define FFB_ROP_NEW             0x83
 175 #define FFB_ROP_OLD             0x85
 176 #define FFB_ROP_NEW_XOR_OLD     0x86
 177
 178 #define FFB_UCSR_FIFO_MASK      0x00000fff
 179 #define FFB_UCSR_FB_BUSY        0x01000000
 180 #define FFB_UCSR_RP_BUSY        0x02000000
 181 #define FFB_UCSR_ALL_BUSY       (FFB_UCSR_RP_BUSY|FFB_UCSR_FB_BUSY)
 182 #define FFB_UCSR_READ_ERR       0x40000000
 183 #define FFB_UCSR_FIFO_OVFL      0x80000000
 184 #define FFB_UCSR_ALL_ERRORS     (FFB_UCSR_READ_ERR|FFB_UCSR_FIFO_OVFL)
 185
 186 struct ffb_fbc {
 187         /* Next vertex registers */
 188         u32     xxx1[3];
 189         u32     alpha;
 190         u32     red;
 191         u32     green;
 192         u32     blue;
 193         u32     depth;
 194         u32     y;
 195         u32     x;
 196         u32     xxx2[2];
 197         u32     ryf;
 198         u32     rxf;
 199         u32     xxx3[2];
 200
 201         u32     dmyf;
 202         u32     dmxf;
 203         u32     xxx4[2];
 204         u32     ebyi;
 205         u32     ebxi;
 206         u32     xxx5[2];
 207         u32     by;
 208         u32     bx;
 209         u32     dy;
 210         u32     dx;
 211         u32     bh;
 212         u32     bw;
 213         u32     xxx6[2];
 214
 215         u32     xxx7[32];
 216
 217         /* Setup unit vertex state register */
 218         u32     suvtx;
 219         u32     xxx8[63];
 220
 221         /* Control registers */
 222         u32     ppc;
 223         u32     wid;
 224         u32     fg;
 225         u32     bg;
 226         u32     consty;
 227         u32     constz;
 228         u32     xclip;
 229         u32     dcss;
 230         u32     vclipmin;
 231         u32     vclipmax;
 232         u32     vclipzmin;
 233         u32     vclipzmax;
 234         u32     dcsf;
 235         u32     dcsb;
 236         u32     dczf;
 237         u32     dczb;
 238
 239         u32     xxx9;
 240         u32     blendc;
 241         u32     blendc1;
 242         u32     blendc2;
 243         u32     fbramitc;
 244         u32     fbc;
 245         u32     rop;
 246         u32     cmp;
 247         u32     matchab;
 248         u32     matchc;
 249         u32     magnab;
 250         u32     magnc;
 251         u32     fbcfg0;
 252         u32     fbcfg1;
 253         u32     fbcfg2;
 254         u32     fbcfg3;
 255
 256         u32     ppcfg;
 257         u32     pick;
 258         u32     fillmode;
 259         u32     fbramwac;
 260         u32     pmask;
 261         u32     xpmask;
 262         u32     ypmask;
 263         u32     zpmask;
 264         u32     clip0min;
 265         u32     clip0max;
 266         u32     clip1min;
 267         u32     clip1max;
 268         u32     clip2min;
 269         u32     clip2max;
 270         u32     clip3min;
 271         u32     clip3max;
 272
 273         /* New 3dRAM III support regs */
 274         u32     rawblend2;
 275         u32     rawpreblend;
 276         u32     rawstencil;
 277         u32     rawstencilctl;
 278         u32     threedram1;
 279         u32     threedram2;
 280         u32     passin;
 281         u32     rawclrdepth;
 282         u32     rawpmask;
 283         u32     rawcsrc;
 284         u32     rawmatch;
 285         u32     rawmagn;
 286         u32     rawropblend;
 287         u32     rawcmp;
 288         u32     rawwac;
 289         u32     fbramid;
 290
 291         u32     drawop;
 292         u32     xxx10[2];
 293         u32     fontlpat;
 294         u32     xxx11;
 295         u32     fontxy;
 296         u32     fontw;
 297         u32     fontinc;
 298         u32     font;
 299         u32     xxx12[3];
 300         u32     blend2;
 301         u32     preblend;
 302         u32     stencil;
 303         u32     stencilctl;
 304
 305         u32     xxx13[4];
 306         u32     dcss1;
 307         u32     dcss2;
 308         u32     dcss3;
 309         u32     widpmask;
 310         u32     dcs2;
 311         u32     dcs3;
 312         u32     dcs4;
 313         u32     xxx14;
 314         u32     dcd2;
 315         u32     dcd3;
 316         u32     dcd4;
 317         u32     xxx15;
 318
 319         u32     pattern[32];
 320
 321         u32     xxx16[256];
 322
 323         u32     devid;
 324         u32     xxx17[63];
 325
 326         u32     ucsr;
 327         u32     xxx18[31];
 328
 329         u32     mer;
 330 };
 331
 332 struct ffb_dac {
 333         u32     type;
 334         u32     value;
 335         u32     type2;
 336         u32     value2;
 337 };
 338
 339 #define FFB_DAC_UCTRL           0x1001 /* User Control */
 340 #define FFB_DAC_UCTRL_MANREV    0x00000f00 /* 4-bit Manufacturing Revision */
 341 #define FFB_DAC_UCTRL_MANREV_SHIFT 8
 342 #define FFB_DAC_TGEN            0x6000 /* Timing Generator */
 343 #define FFB_DAC_TGEN_VIDE       0x00000001 /* Video Enable */
 344 #define FFB_DAC_DID             0x8000 /* Device Identification */
 345 #define FFB_DAC_DID_PNUM        0x0ffff000 /* Device Part Number */
 346 #define FFB_DAC_DID_PNUM_SHIFT  12
 347 #define FFB_DAC_DID_REV         0xf0000000 /* Device Revision */
 348 #define FFB_DAC_DID_REV_SHIFT   28
 349
 350 #define FFB_DAC_CUR_CTRL        0x100
 351 #define FFB_DAC_CUR_CTRL_P0     0x00000001
 352 #define FFB_DAC_CUR_CTRL_P1     0x00000002
 353
 354 struct ffb_par {
 355         spinlock_t              lock;
 356         struct ffb_fbc __iomem  *fbc;
 357         struct ffb_dac __iomem  *dac;
 358
 359         u32                     flags;
 360 #define FFB_FLAG_AFB            0x00000001 /* AFB m3 or m6 */
 361 #define FFB_FLAG_BLANKED        0x00000002 /* screen is blanked */
 362 #define FFB_FLAG_INVCURSOR      0x00000004 /* DAC has inverted cursor logic */
 363
 364         u32                     fg_cache __attribute__((aligned (8)));
 365         u32                     bg_cache;
 366         u32                     rop_cache;
 367
 368         int                     fifo_cache;
 369
 370         unsigned long           physbase;
 371         unsigned long           fbsize;
 372
 373         int                     board_type;
 374
 375         u32                     pseudo_palette[16];
 376 };
 377
 378 static void FFBFifo(struct ffb_par *par, int n)
 379 {
 380         struct ffb_fbc __iomem *fbc;
 381         int cache = par->fifo_cache;
 382
 383         if (cache - n < 0) {
 384                 fbc = par->fbc;
 385                 do {
 386                         cache = (upa_readl(&fbc->ucsr) & FFB_UCSR_FIFO_MASK);
 387                         cache -= 8;
 388                 } while (cache - n < 0);
 389         }
 390         par->fifo_cache = cache - n;
 391 }
 392
 393 static void FFBWait(struct ffb_par *par)
 394 {
 395         struct ffb_fbc __iomem *fbc;
 396         int limit = 10000;
 397
 398         fbc = par->fbc;
 399         do {
 400                 if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_BUSY) == 0)
 401                         break;
 402                 if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0) {
 403                         upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr);
 404                 }
 405                 udelay(10);
 406         } while (--limit > 0);
 407 }
 408
 409 static int ffb_sync(struct fb_info *p)
 410 {
 411         struct ffb_par *par = (struct ffb_par *)p->par;
 412
 413         FFBWait(par);
 414         return 0;
 415 }
 416
 417 static __inline__ void ffb_rop(struct ffb_par *par, u32 rop)
 418 {
 419         if (par->rop_cache != rop) {
 420                 FFBFifo(par, 1);
 421                 upa_writel(rop, &par->fbc->rop);
 422                 par->rop_cache = rop;
 423         }
 424 }
 425
 426 static void ffb_switch_from_graph(struct ffb_par *par)
 427 {
 428         struct ffb_fbc __iomem *fbc = par->fbc;
 429         struct ffb_dac __iomem *dac = par->dac;
 430         unsigned long flags;
 431
 432         spin_lock_irqsave(&par->lock, flags);
 433         FFBWait(par);
 434         par->fifo_cache = 0;
 435         FFBFifo(par, 7);
 436         upa_writel(FFB_PPC_VCE_DISABLE | FFB_PPC_TBE_OPAQUE |
 437                    FFB_PPC_APE_DISABLE | FFB_PPC_CS_CONST,
 438                    &fbc->ppc);
 439         upa_writel(0x2000707f, &fbc->fbc);
 440         upa_writel(par->rop_cache, &fbc->rop);
 441         upa_writel(0xffffffff, &fbc->pmask);
 442         upa_writel((1 << 16) | (0 << 0), &fbc->fontinc);
 443         upa_writel(par->fg_cache, &fbc->fg);
 444         upa_writel(par->bg_cache, &fbc->bg);
 445         FFBWait(par);
 446
 447         /* Disable cursor.  */
 448         upa_writel(FFB_DAC_CUR_CTRL, &dac->type2);
 449         if (par->flags & FFB_FLAG_INVCURSOR)
 450                 upa_writel(0, &dac->value2);
 451         else
 452                 upa_writel((FFB_DAC_CUR_CTRL_P0 |
 453                             FFB_DAC_CUR_CTRL_P1), &dac->value2);
 454
 455         spin_unlock_irqrestore(&par->lock, flags);
 456 }
 457
 458 static int ffb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 459 {
 460         struct ffb_par *par = (struct ffb_par *)info->par;
 461
 462         /* We just use this to catch switches out of
 463          * graphics mode.
 464          */
 465         ffb_switch_from_graph(par);
 466
 467         if (var->xoffset || var->yoffset || var->vmode)
 468                 return -EINVAL;
 469         return 0;
 470 }
 471
 472 /**
 473  *      ffb_fillrect - Draws a rectangle on the screen.
 474  *
 475  *      @info: frame buffer structure that represents a single frame buffer
 476  *      @rect: structure defining the rectagle and operation.
 477  */
 478 static void ffb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
 479 {
 480         struct ffb_par *par = (struct ffb_par *)info->par;
 481         struct ffb_fbc __iomem *fbc = par->fbc;
 482         unsigned long flags;
 483         u32 fg;
 484
 485         BUG_ON(rect->rop != ROP_COPY && rect->rop != ROP_XOR);
 486
 487         fg = ((u32 *)info->pseudo_palette)[rect->color];
 488
 489         spin_lock_irqsave(&par->lock, flags);
 490
 491         if (fg != par->fg_cache) {
 492                 FFBFifo(par, 1);
 493                 upa_writel(fg, &fbc->fg);
 494                 par->fg_cache = fg;
 495         }
 496
 497         ffb_rop(par, rect->rop == ROP_COPY ?
 498                      FFB_ROP_NEW :
 499                      FFB_ROP_NEW_XOR_OLD);
 500
 501         FFBFifo(par, 5);
 502         upa_writel(FFB_DRAWOP_RECTANGLE, &fbc->drawop);
 503         upa_writel(rect->dy, &fbc->by);
 504         upa_writel(rect->dx, &fbc->bx);
 505         upa_writel(rect->height, &fbc->bh);
 506         upa_writel(rect->width, &fbc->bw);
 507
 508         spin_unlock_irqrestore(&par->lock, flags);
 509 }
 510
 511 /**
 512  *      ffb_copyarea - Copies on area of the screen to another area.
 513  *
 514  *      @info: frame buffer structure that represents a single frame buffer
 515  *      @area: structure defining the source and destination.
 516  */
 517
 518 static void ffb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
 519 {
 520         struct ffb_par *par = (struct ffb_par *)info->par;
 521         struct ffb_fbc __iomem *fbc = par->fbc;
 522         unsigned long flags;
 523
 524         if (area->dx != area->sx ||
 525             area->dy == area->sy) {
 526                 cfb_copyarea(info, area);
 527                 return;
 528         }
 529
 530         spin_lock_irqsave(&par->lock, flags);
 531
 532         ffb_rop(par, FFB_ROP_OLD);
 533
 534         FFBFifo(par, 7);
 535         upa_writel(FFB_DRAWOP_VSCROLL, &fbc->drawop);
 536         upa_writel(area->sy, &fbc->by);
 537         upa_writel(area->sx, &fbc->bx);
 538         upa_writel(area->dy, &fbc->dy);
 539         upa_writel(area->dx, &fbc->dx);
 540         upa_writel(area->height, &fbc->bh);
 541         upa_writel(area->width, &fbc->bw);
 542
 543         spin_unlock_irqrestore(&par->lock, flags);
 544 }
 545
 546 /**
 547  *      ffb_imageblit - Copies a image from system memory to the screen.
 548  *
 549  *      @info: frame buffer structure that represents a single frame buffer
 550  *      @image: structure defining the image.
 551  */
 552 static void ffb_imageblit(struct fb_info *info, const struct fb_image *image)
 553 {
 554         struct ffb_par *par = (struct ffb_par *)info->par;
 555         struct ffb_fbc __iomem *fbc = par->fbc;
 556         const u8 *data = image->data;
 557         unsigned long flags;
 558         u32 fg, bg, xy;
 559         u64 fgbg;
 560         int i, width, stride;
 561
 562         if (image->depth > 1) {
 563                 cfb_imageblit(info, image);
 564                 return;
 565         }
 566
 567         fg = ((u32 *)info->pseudo_palette)[image->fg_color];
 568         bg = ((u32 *)info->pseudo_palette)[image->bg_color];
 569         fgbg = ((u64) fg << 32) | (u64) bg;
 570         xy = (image->dy << 16) | image->dx;
 571         width = image->width;
 572         stride = ((width + 7) >> 3);
 573
 574         spin_lock_irqsave(&par->lock, flags);
 575
 576         if (fgbg != *(u64 *)&par->fg_cache) {
 577                 FFBFifo(par, 2);
 578                 upa_writeq(fgbg, &fbc->fg);
 579                 *(u64 *)&par->fg_cache = fgbg;
 580         }
 581
 582         if (width >= 32) {
 583                 FFBFifo(par, 1);
 584                 upa_writel(32, &fbc->fontw);
 585         }
 586
 587         while (width >= 32) {
 588                 const u8 *next_data = data + 4;
 589
 590                 FFBFifo(par, 1);
 591                 upa_writel(xy, &fbc->fontxy);
 592                 xy += (32 << 0);
 593
 594                 for (i = 0; i < image->height; i++) {
 595                         u32 val = (((u32)data[0] << 24) |
 596                                    ((u32)data[1] << 16) |
 597                                    ((u32)data[2] <<  8) |
 598                                    ((u32)data[3] <<  0));
 599                         FFBFifo(par, 1);
 600                         upa_writel(val, &fbc->font);
 601
 602                         data += stride;
 603                 }
 604
 605                 data = next_data;
 606                 width -= 32;
 607         }
 608
 609         if (width) {
 610                 FFBFifo(par, 2);
 611                 upa_writel(width, &fbc->fontw);
 612                 upa_writel(xy, &fbc->fontxy);
 613
 614                 for (i = 0; i < image->height; i++) {
 615                         u32 val = (((u32)data[0] << 24) |
 616                                    ((u32)data[1] << 16) |
 617                                    ((u32)data[2] <<  8) |
 618                                    ((u32)data[3] <<  0));
 619                         FFBFifo(par, 1);
 620                         upa_writel(val, &fbc->font);
 621
 622                         data += stride;
 623                 }
 624         }
 625
 626         spin_unlock_irqrestore(&par->lock, flags);
 627 }
 628
 629 static void ffb_fixup_var_rgb(struct fb_var_screeninfo *var)
 630 {
 631         var->red.offset = 0;
 632         var->red.length = 8;
 633         var->green.offset = 8;
 634         var->green.length = 8;
 635         var->blue.offset = 16;
 636         var->blue.length = 8;
 637         var->transp.offset = 0;
 638         var->transp.length = 0;
 639 }
 640
 641 /**
 642  *      ffb_setcolreg - Sets a color register.
 643  *
 644  *      @regno: boolean, 0 copy local, 1 get_user() function
 645  *      @red: frame buffer colormap structure
 646  *      @green: The green value which can be up to 16 bits wide
 647  *      @blue:  The blue value which can be up to 16 bits wide.
 648  *      @transp: If supported the alpha value which can be up to 16 bits wide.
 649  *      @info: frame buffer info structure
 650  */
 651 static int ffb_setcolreg(unsigned regno,
 652                          unsigned red, unsigned green, unsigned blue,
 653                          unsigned transp, struct fb_info *info)
 654 {
 655         u32 value;
 656
 657         if (regno >= 16)
 658                 return 1;
 659
 660         red >>= 8;
 661         green >>= 8;
 662         blue >>= 8;
 663
 664         value = (blue << 16) | (green << 8) | red;
 665         ((u32 *)info->pseudo_palette)[regno] = value;
 666
 667         return 0;
 668 }
 669
 670 /**
 671  *      ffb_blank - Optional function.  Blanks the display.
 672  *      @blank_mode: the blank mode we want.
 673  *      @info: frame buffer structure that represents a single frame buffer
 674  */
 675 static int ffb_blank(int blank, struct fb_info *info)
 676 {
 677         struct ffb_par *par = (struct ffb_par *)info->par;
 678         struct ffb_dac __iomem *dac = par->dac;
 679         unsigned long flags;
 680         u32 val;
 681         int i;
 682
 683         spin_lock_irqsave(&par->lock, flags);
 684
 685         FFBWait(par);
 686
 687         upa_writel(FFB_DAC_TGEN, &dac->type);
 688         val = upa_readl(&dac->value);
 689         switch (blank) {
 690         case FB_BLANK_UNBLANK: /* Unblanking */
 691                 val |= FFB_DAC_TGEN_VIDE;
 692                 par->flags &= ~FFB_FLAG_BLANKED;
 693                 break;
 694
 695         case FB_BLANK_NORMAL: /* Normal blanking */
 696         case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
 697         case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
 698         case FB_BLANK_POWERDOWN: /* Poweroff */
 699                 val &= ~FFB_DAC_TGEN_VIDE;
 700                 par->flags |= FFB_FLAG_BLANKED;
 701                 break;
 702         }
 703         upa_writel(FFB_DAC_TGEN, &dac->type);
 704         upa_writel(val, &dac->value);
 705         for (i = 0; i < 10; i++) {
 706                 upa_writel(FFB_DAC_TGEN, &dac->type);
 707                 upa_readl(&dac->value);
 708         }
 709
 710         spin_unlock_irqrestore(&par->lock, flags);
 711
 712         return 0;
 713 }
 714
 715 static struct sbus_mmap_map ffb_mmap_map[] = {
 716         {
 717                 .voff   = FFB_SFB8R_VOFF,
 718                 .poff   = FFB_SFB8R_POFF,
 719                 .size   = 0x0400000
 720         },
 721         {
 722                 .voff   = FFB_SFB8G_VOFF,
 723                 .poff   = FFB_SFB8G_POFF,
 724                 .size   = 0x0400000
 725         },
 726         {
 727                 .voff   = FFB_SFB8B_VOFF,
 728                 .poff   = FFB_SFB8B_POFF,
 729                 .size   = 0x0400000
 730         },
 731         {
 732                 .voff   = FFB_SFB8X_VOFF,
 733                 .poff   = FFB_SFB8X_POFF,
 734                 .size   = 0x0400000
 735         },
 736         {
 737                 .voff   = FFB_SFB32_VOFF,
 738                 .poff   = FFB_SFB32_POFF,
 739                 .size   = 0x1000000
 740         },
 741         {
 742                 .voff   = FFB_SFB64_VOFF,
 743                 .poff   = FFB_SFB64_POFF,
 744                 .size   = 0x2000000
 745         },
 746         {
 747                 .voff   = FFB_FBC_REGS_VOFF,
 748                 .poff   = FFB_FBC_REGS_POFF,
 749                 .size   = 0x0002000
 750         },
 751         {
 752                 .voff   = FFB_BM_FBC_REGS_VOFF,
 753                 .poff   = FFB_BM_FBC_REGS_POFF,
 754                 .size   = 0x0002000
 755         },
 756         {
 757                 .voff   = FFB_DFB8R_VOFF,
 758                 .poff   = FFB_DFB8R_POFF,
 759                 .size   = 0x0400000
 760         },
 761         {
 762                 .voff   = FFB_DFB8G_VOFF,
 763                 .poff   = FFB_DFB8G_POFF,
 764                 .size   = 0x0400000
 765         },
 766         {
 767                 .voff   = FFB_DFB8B_VOFF,
 768                 .poff   = FFB_DFB8B_POFF,
 769                 .size   = 0x0400000
 770         },
 771         {
 772                 .voff   = FFB_DFB8X_VOFF,
 773                 .poff   = FFB_DFB8X_POFF,
 774                 .size   = 0x0400000
 775         },
 776         {
 777                 .voff   = FFB_DFB24_VOFF,
 778                 .poff   = FFB_DFB24_POFF,
 779                 .size   = 0x1000000
 780         },
 781         {
 782                 .voff   = FFB_DFB32_VOFF,
 783                 .poff   = FFB_DFB32_POFF,
 784                 .size   = 0x1000000
 785         },
 786         {
 787                 .voff   = FFB_FBC_KREGS_VOFF,
 788                 .poff   = FFB_FBC_KREGS_POFF,
 789                 .size   = 0x0002000
 790         },
 791         {
 792                 .voff   = FFB_DAC_VOFF,
 793                 .poff   = FFB_DAC_POFF,
 794                 .size   = 0x0002000
 795         },
 796         {
 797                 .voff   = FFB_PROM_VOFF,
 798                 .poff   = FFB_PROM_POFF,
 799                 .size   = 0x0010000
 800         },
 801         {
 802                 .voff   = FFB_EXP_VOFF,
 803                 .poff   = FFB_EXP_POFF,
 804                 .size   = 0x0002000
 805         },
 806         {
 807                 .voff   = FFB_DFB422A_VOFF,
 808                 .poff   = FFB_DFB422A_POFF,
 809                 .size   = 0x0800000
 810         },
 811         {
 812                 .voff   = FFB_DFB422AD_VOFF,
 813                 .poff   = FFB_DFB422AD_POFF,
 814                 .size   = 0x0800000
 815         },
 816         {
 817                 .voff   = FFB_DFB24B_VOFF,
 818                 .poff   = FFB_DFB24B_POFF,
 819                 .size   = 0x1000000
 820         },
 821         {
 822                 .voff   = FFB_DFB422B_VOFF,
 823                 .poff   = FFB_DFB422B_POFF,
 824                 .size   = 0x0800000
 825         },
 826         {
 827                 .voff   = FFB_DFB422BD_VOFF,
 828                 .poff   = FFB_DFB422BD_POFF,
 829                 .size   = 0x0800000
 830         },
 831         {
 832                 .voff   = FFB_SFB16Z_VOFF,
 833                 .poff   = FFB_SFB16Z_POFF,
 834                 .size   = 0x0800000
 835         },
 836         {
 837                 .voff   = FFB_SFB8Z_VOFF,
 838                 .poff   = FFB_SFB8Z_POFF,
 839                 .size   = 0x0800000
 840         },
 841         {
 842                 .voff   = FFB_SFB422_VOFF,
 843                 .poff   = FFB_SFB422_POFF,
 844                 .size   = 0x0800000
 845         },
 846         {
 847                 .voff   = FFB_SFB422D_VOFF,
 848                 .poff   = FFB_SFB422D_POFF,
 849                 .size   = 0x0800000
 850         },
 851         { .size = 0 }
 852 };
 853
 854 static int ffb_mmap(struct fb_info *info, struct vm_area_struct *vma)
 855 {
 856         struct ffb_par *par = (struct ffb_par *)info->par;
 857
 858         return sbusfb_mmap_helper(ffb_mmap_map,
 859                                   par->physbase, par->fbsize,
 860                                   0, vma);
 861 }
 862
 863 static int ffb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
 864 {
 865         struct ffb_par *par = (struct ffb_par *)info->par;
 866
 867         return sbusfb_ioctl_helper(cmd, arg, info,
 868                                    FBTYPE_CREATOR, 24, par->fbsize);
 869 }
 870
 871 /*
 872  *  Initialisation
 873  */
 874
 875 static void ffb_init_fix(struct fb_info *info)
 876 {
 877         struct ffb_par *par = (struct ffb_par *)info->par;
 878         const char *ffb_type_name;
 879
 880         if (!(par->flags & FFB_FLAG_AFB)) {
 881                 if ((par->board_type & 0x7) == 0x3)
 882                         ffb_type_name = "Creator 3D";
 883                 else
 884                         ffb_type_name = "Creator";
 885         } else
 886                 ffb_type_name = "Elite 3D";
 887
 888         strlcpy(info->fix.id, ffb_type_name, sizeof(info->fix.id));
 889
 890         info->fix.type = FB_TYPE_PACKED_PIXELS;
 891         info->fix.visual = FB_VISUAL_TRUECOLOR;
 892
 893         /* Framebuffer length is the same regardless of resolution. */
 894         info->fix.line_length = 8192;
 895
 896         info->fix.accel = FB_ACCEL_SUN_CREATOR;
 897 }
 898
 899 static int __devinit ffb_probe(struct of_device *op,
 900                                const struct of_device_id *match)
 901 {
 902         struct device_node *dp = op->node;
 903         struct ffb_fbc __iomem *fbc;
 904         struct ffb_dac __iomem *dac;
 905         struct fb_info *info;
 906         struct ffb_par *par;
 907         u32 dac_pnum, dac_rev, dac_mrev;
 908         int err;
 909
 910         info = framebuffer_alloc(sizeof(struct ffb_par), &op->dev);
 911
 912         err = -ENOMEM;
 913         if (!info)
 914                 goto out_err;
 915
 916         par = info->par;
 917
 918         spin_lock_init(&par->lock);
 919         par->fbc = of_ioremap(&op->resource[2], 0,
 920                               sizeof(struct ffb_fbc), "ffb fbc");
 921         if (!par->fbc)
 922                 goto out_release_fb;
 923
 924         par->dac = of_ioremap(&op->resource[1], 0,
 925                               sizeof(struct ffb_dac), "ffb dac");
 926         if (!par->dac)
 927                 goto out_unmap_fbc;
 928
 929         par->rop_cache = FFB_ROP_NEW;
 930         par->physbase = op->resource[0].start;
 931
 932         /* Don't mention copyarea, so SCROLL_REDRAW is always
 933          * used.  It is the fastest on this chip.
 934          */
 935         info->flags = (FBINFO_DEFAULT |
 936                        /* FBINFO_HWACCEL_COPYAREA | */
 937                        FBINFO_HWACCEL_FILLRECT |
 938                        FBINFO_HWACCEL_IMAGEBLIT);
 939
 940         info->fbops = &ffb_ops;
 941
 942         info->screen_base = (char *) par->physbase + FFB_DFB24_POFF;
 943         info->pseudo_palette = par->pseudo_palette;
 944
 945         sbusfb_fill_var(&info->var, dp->node, 32);
 946         par->fbsize = PAGE_ALIGN(info->var.xres * info->var.yres * 4);
 947         ffb_fixup_var_rgb(&info->var);
 948
 949         info->var.accel_flags = FB_ACCELF_TEXT;
 950
 951         if (!strcmp(dp->name, "SUNW,afb"))
 952                 par->flags |= FFB_FLAG_AFB;
 953
 954         par->board_type = of_getintprop_default(dp, "board_type", 0);
 955
 956         fbc = par->fbc;
 957         if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0)
 958                 upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr);
 959
 960         dac = par->dac;
 961         upa_writel(FFB_DAC_DID, &dac->type);
 962         dac_pnum = upa_readl(&dac->value);
 963         dac_rev = (dac_pnum & FFB_DAC_DID_REV) >> FFB_DAC_DID_REV_SHIFT;
 964         dac_pnum = (dac_pnum & FFB_DAC_DID_PNUM) >> FFB_DAC_DID_PNUM_SHIFT;
 965
 966         upa_writel(FFB_DAC_UCTRL, &dac->type);
 967         dac_mrev = upa_readl(&dac->value);
 968         dac_mrev = (dac_mrev & FFB_DAC_UCTRL_MANREV) >>
 969                 FFB_DAC_UCTRL_MANREV_SHIFT;
 970
 971         /* Elite3D has different DAC revision numbering, and no DAC revisions
 972          * have the reversed meaning of cursor enable.  Otherwise, Pacifica 1
 973          * ramdacs with manufacturing revision less than 3 have inverted
 974          * cursor logic.  We identify Pacifica 1 as not Pacifica 2, the
 975          * latter having a part number value of 0x236e.
 976          */
 977         if ((par->flags & FFB_FLAG_AFB) || dac_pnum == 0x236e) {
 978                 par->flags &= ~FFB_FLAG_INVCURSOR;
 979         } else {
 980                 if (dac_mrev < 3)
 981                         par->flags |= FFB_FLAG_INVCURSOR;
 982         }
 983
 984         ffb_switch_from_graph(par);
 985
 986         /* Unblank it just to be sure.  When there are multiple
 987          * FFB/AFB cards in the system, or it is not the OBP
 988          * chosen console, it will have video outputs off in
 989          * the DAC.
 990          */
 991         ffb_blank(0, info);
 992
 993         if (fb_alloc_cmap(&info->cmap, 256, 0))
 994                 goto out_unmap_dac;
 995
 996         ffb_init_fix(info);
 997
 998         err = register_framebuffer(info);
 999         if (err < 0)
1000                 goto out_dealloc_cmap;
1001
1002         dev_set_drvdata(&op->dev, info);
1003
1004         printk("%s: %s at %016lx, type %d, "
1005                "DAC pnum[%x] rev[%d] manuf_rev[%d]\n",
1006                dp->full_name,
1007                ((par->flags & FFB_FLAG_AFB) ? "AFB" : "FFB"),
1008                par->physbase, par->board_type,
1009                dac_pnum, dac_rev, dac_mrev);
1010
1011         return 0;
1012
1013 out_dealloc_cmap:
1014         fb_dealloc_cmap(&info->cmap);
1015
1016 out_unmap_dac:
1017         of_iounmap(&op->resource[2], par->fbc, sizeof(struct ffb_fbc));
1018
1019 out_unmap_fbc:
1020         of_iounmap(&op->resource[2], par->fbc, sizeof(struct ffb_fbc));
1021
1022 out_release_fb:
1023         framebuffer_release(info);
1024
1025 out_err:
1026         return err;
1027 }
1028
1029 static int __devexit ffb_remove(struct of_device *op)
1030 {
1031         struct fb_info *info = dev_get_drvdata(&op->dev);
1032         struct ffb_par *par = info->par;
1033
1034         unregister_framebuffer(info);
1035         fb_dealloc_cmap(&info->cmap);
1036
1037         of_iounmap(&op->resource[2], par->fbc, sizeof(struct ffb_fbc));
1038         of_iounmap(&op->resource[1], par->dac, sizeof(struct ffb_dac));
1039
1040         framebuffer_release(info);
1041
1042         dev_set_drvdata(&op->dev, NULL);
1043
1044         return 0;
1045 }
1046
1047 static struct of_device_id ffb_match[] = {
1048         {
1049                 .name = "SUNW,ffb",
1050         },
1051         {
1052                 .name = "SUNW,afb",
1053         },
1054         {},
1055 };
1056 MODULE_DEVICE_TABLE(of, ffb_match);
1057
1058 static struct of_platform_driver ffb_driver = {
1059         .name           = "ffb",
1060         .match_table    = ffb_match,
1061         .probe          = ffb_probe,
1062         .remove         = __devexit_p(ffb_remove),
1063 };
1064
1065 int __init ffb_init(void)
1066 {
1067         if (fb_get_options("ffb", NULL))
1068                 return -ENODEV;
1069
1070         return of_register_driver(&ffb_driver, &of_bus_type);
1071 }
1072
1073 void __exit ffb_exit(void)
1074 {
1075         of_unregister_driver(&ffb_driver);
1076 }
1077
1078 module_init(ffb_init);
1079 module_exit(ffb_exit);
1080
1081 MODULE_DESCRIPTION("framebuffer driver for Creator/Elite3D chipsets");
1082 MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
1083 MODULE_VERSION("2.0");
1084 MODULE_LICENSE("GPL");