1 /* linux/arch/arm/plat-s3c24xx/clock-dclk.c
3 * Copyright (c) 2004,2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * S3C24XX - definitions for DCLK and CLKOUT registers
14 #include <linux/kernel.h>
15 #include <linux/errno.h>
16 #include <linux/clk.h>
19 #include <mach/regs-clock.h>
20 #include <mach/regs-gpio.h>
21 #include <mach/hardware.h>
23 #include <plat/clock.h>
26 /* clocks that could be registered by external code */
28 static int s3c24xx_dclk_enable(struct clk *clk, int enable)
30 unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
33 dclkcon |= clk->ctrlbit;
35 dclkcon &= ~clk->ctrlbit;
37 __raw_writel(dclkcon, S3C24XX_DCLKCON);
42 static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
44 unsigned long dclkcon;
47 if (parent == &clk_upll)
49 else if (parent == &clk_p)
56 dclkcon = __raw_readl(S3C24XX_DCLKCON);
58 if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
60 dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
62 dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
65 dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
67 dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
70 __raw_writel(dclkcon, S3C24XX_DCLKCON);
74 static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
78 if ((rate == 0) || !clk->parent)
81 div = clk_get_rate(clk->parent) / rate;
90 static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
93 unsigned long div = s3c24xx_calc_div(clk, rate);
98 return clk_get_rate(clk->parent) / div;
101 static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
103 unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
108 if (clk == &s3c24xx_dclk0) {
109 mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
110 S3C2410_DCLKCON_DCLK0_CMP_MASK;
111 data = S3C2410_DCLKCON_DCLK0_DIV(div) |
112 S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
113 } else if (clk == &s3c24xx_dclk1) {
114 mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
115 S3C2410_DCLKCON_DCLK1_CMP_MASK;
116 data = S3C2410_DCLKCON_DCLK1_DIV(div) |
117 S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
121 clk->rate = clk_get_rate(clk->parent) / div;
122 __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
126 static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
129 unsigned long source;
131 /* calculate the MISCCR setting for the clock */
133 if (parent == &clk_xtal)
134 source = S3C2410_MISCCR_CLK0_MPLL;
135 else if (parent == &clk_upll)
136 source = S3C2410_MISCCR_CLK0_UPLL;
137 else if (parent == &clk_f)
138 source = S3C2410_MISCCR_CLK0_FCLK;
139 else if (parent == &clk_h)
140 source = S3C2410_MISCCR_CLK0_HCLK;
141 else if (parent == &clk_p)
142 source = S3C2410_MISCCR_CLK0_PCLK;
143 else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
144 source = S3C2410_MISCCR_CLK0_DCLK0;
145 else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
146 source = S3C2410_MISCCR_CLK0_DCLK0;
150 clk->parent = parent;
152 if (clk == &s3c24xx_clkout0)
153 mask = S3C2410_MISCCR_CLK0_MASK;
156 mask = S3C2410_MISCCR_CLK1_MASK;
159 s3c2410_modify_misccr(mask, source);
163 /* external clock definitions */
165 struct clk s3c24xx_dclk0 = {
168 .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
169 .enable = s3c24xx_dclk_enable,
170 .set_parent = s3c24xx_dclk_setparent,
171 .set_rate = s3c24xx_set_dclk_rate,
172 .round_rate = s3c24xx_round_dclk_rate,
175 struct clk s3c24xx_dclk1 = {
178 .ctrlbit = S3C2410_DCLKCON_DCLK1EN,
179 .enable = s3c24xx_dclk_enable,
180 .set_parent = s3c24xx_dclk_setparent,
181 .set_rate = s3c24xx_set_dclk_rate,
182 .round_rate = s3c24xx_round_dclk_rate,
185 struct clk s3c24xx_clkout0 = {
188 .set_parent = s3c24xx_clkout_setparent,
191 struct clk s3c24xx_clkout1 = {
194 .set_parent = s3c24xx_clkout_setparent,