Merge branch 'linus' into cpumask-for-linus
[linux-2.6] / drivers / i2c / busses / i2c-mpc.c
1 /*
2  * (C) Copyright 2003-2004
3  * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
4
5  * This is a combined i2c adapter and algorithm driver for the
6  * MPC107/Tsi107 PowerPC northbridge and processors that include
7  * the same I2C unit (8240, 8245, 85xx).
8  *
9  * Release 0.8
10  *
11  * This file is licensed under the terms of the GNU General Public
12  * License version 2. This program is licensed "as is" without any
13  * warranty of any kind, whether express or implied.
14  */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/init.h>
20 #include <linux/of_platform.h>
21 #include <linux/of_i2c.h>
22
23 #include <asm/io.h>
24 #include <linux/fsl_devices.h>
25 #include <linux/i2c.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28
29 #define DRV_NAME "mpc-i2c"
30
31 #define MPC_I2C_FDR     0x04
32 #define MPC_I2C_CR      0x08
33 #define MPC_I2C_SR      0x0c
34 #define MPC_I2C_DR      0x10
35 #define MPC_I2C_DFSRR 0x14
36
37 #define CCR_MEN  0x80
38 #define CCR_MIEN 0x40
39 #define CCR_MSTA 0x20
40 #define CCR_MTX  0x10
41 #define CCR_TXAK 0x08
42 #define CCR_RSTA 0x04
43
44 #define CSR_MCF  0x80
45 #define CSR_MAAS 0x40
46 #define CSR_MBB  0x20
47 #define CSR_MAL  0x10
48 #define CSR_SRW  0x04
49 #define CSR_MIF  0x02
50 #define CSR_RXAK 0x01
51
52 struct mpc_i2c {
53         void __iomem *base;
54         u32 interrupt;
55         wait_queue_head_t queue;
56         struct i2c_adapter adap;
57         int irq;
58         u32 flags;
59 };
60
61 static __inline__ void writeccr(struct mpc_i2c *i2c, u32 x)
62 {
63         writeb(x, i2c->base + MPC_I2C_CR);
64 }
65
66 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
67 {
68         struct mpc_i2c *i2c = dev_id;
69         if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
70                 /* Read again to allow register to stabilise */
71                 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
72                 writeb(0, i2c->base + MPC_I2C_SR);
73                 wake_up(&i2c->queue);
74         }
75         return IRQ_HANDLED;
76 }
77
78 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
79  * the bus, because it wants to send ACK.
80  * Following sequence of enabling/disabling and sending start/stop generates
81  * the pulse, so it's all OK.
82  */
83 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
84 {
85         writeccr(i2c, 0);
86         udelay(30);
87         writeccr(i2c, CCR_MEN);
88         udelay(30);
89         writeccr(i2c, CCR_MSTA | CCR_MTX);
90         udelay(30);
91         writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
92         udelay(30);
93         writeccr(i2c, CCR_MEN);
94         udelay(30);
95 }
96
97 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
98 {
99         unsigned long orig_jiffies = jiffies;
100         u32 x;
101         int result = 0;
102
103         if (i2c->irq == NO_IRQ)
104         {
105                 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
106                         schedule();
107                         if (time_after(jiffies, orig_jiffies + timeout)) {
108                                 pr_debug("I2C: timeout\n");
109                                 writeccr(i2c, 0);
110                                 result = -EIO;
111                                 break;
112                         }
113                 }
114                 x = readb(i2c->base + MPC_I2C_SR);
115                 writeb(0, i2c->base + MPC_I2C_SR);
116         } else {
117                 /* Interrupt mode */
118                 result = wait_event_timeout(i2c->queue,
119                         (i2c->interrupt & CSR_MIF), timeout);
120
121                 if (unlikely(!(i2c->interrupt & CSR_MIF))) {
122                         pr_debug("I2C: wait timeout\n");
123                         writeccr(i2c, 0);
124                         result = -ETIMEDOUT;
125                 }
126
127                 x = i2c->interrupt;
128                 i2c->interrupt = 0;
129         }
130
131         if (result < 0)
132                 return result;
133
134         if (!(x & CSR_MCF)) {
135                 pr_debug("I2C: unfinished\n");
136                 return -EIO;
137         }
138
139         if (x & CSR_MAL) {
140                 pr_debug("I2C: MAL\n");
141                 return -EIO;
142         }
143
144         if (writing && (x & CSR_RXAK)) {
145                 pr_debug("I2C: No RXAK\n");
146                 /* generate stop */
147                 writeccr(i2c, CCR_MEN);
148                 return -EIO;
149         }
150         return 0;
151 }
152
153 static void mpc_i2c_setclock(struct mpc_i2c *i2c)
154 {
155         /* Set clock and filters */
156         if (i2c->flags & FSL_I2C_DEV_SEPARATE_DFSRR) {
157                 writeb(0x31, i2c->base + MPC_I2C_FDR);
158                 writeb(0x10, i2c->base + MPC_I2C_DFSRR);
159         } else if (i2c->flags & FSL_I2C_DEV_CLOCK_5200)
160                 writeb(0x3f, i2c->base + MPC_I2C_FDR);
161         else
162                 writel(0x1031, i2c->base + MPC_I2C_FDR);
163 }
164
165 static void mpc_i2c_start(struct mpc_i2c *i2c)
166 {
167         /* Clear arbitration */
168         writeb(0, i2c->base + MPC_I2C_SR);
169         /* Start with MEN */
170         writeccr(i2c, CCR_MEN);
171 }
172
173 static void mpc_i2c_stop(struct mpc_i2c *i2c)
174 {
175         writeccr(i2c, CCR_MEN);
176 }
177
178 static int mpc_write(struct mpc_i2c *i2c, int target,
179                      const u8 * data, int length, int restart)
180 {
181         int i, result;
182         unsigned timeout = i2c->adap.timeout;
183         u32 flags = restart ? CCR_RSTA : 0;
184
185         /* Start with MEN */
186         if (!restart)
187                 writeccr(i2c, CCR_MEN);
188         /* Start as master */
189         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
190         /* Write target byte */
191         writeb((target << 1), i2c->base + MPC_I2C_DR);
192
193         result = i2c_wait(i2c, timeout, 1);
194         if (result < 0)
195                 return result;
196
197         for (i = 0; i < length; i++) {
198                 /* Write data byte */
199                 writeb(data[i], i2c->base + MPC_I2C_DR);
200
201                 result = i2c_wait(i2c, timeout, 1);
202                 if (result < 0)
203                         return result;
204         }
205
206         return 0;
207 }
208
209 static int mpc_read(struct mpc_i2c *i2c, int target,
210                     u8 * data, int length, int restart)
211 {
212         unsigned timeout = i2c->adap.timeout;
213         int i, result;
214         u32 flags = restart ? CCR_RSTA : 0;
215
216         /* Start with MEN */
217         if (!restart)
218                 writeccr(i2c, CCR_MEN);
219         /* Switch to read - restart */
220         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
221         /* Write target address byte - this time with the read flag set */
222         writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
223
224         result = i2c_wait(i2c, timeout, 1);
225         if (result < 0)
226                 return result;
227
228         if (length) {
229                 if (length == 1)
230                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
231                 else
232                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
233                 /* Dummy read */
234                 readb(i2c->base + MPC_I2C_DR);
235         }
236
237         for (i = 0; i < length; i++) {
238                 result = i2c_wait(i2c, timeout, 0);
239                 if (result < 0)
240                         return result;
241
242                 /* Generate txack on next to last byte */
243                 if (i == length - 2)
244                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
245                 /* Generate stop on last byte */
246                 if (i == length - 1)
247                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_TXAK);
248                 data[i] = readb(i2c->base + MPC_I2C_DR);
249         }
250
251         return length;
252 }
253
254 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
255 {
256         struct i2c_msg *pmsg;
257         int i;
258         int ret = 0;
259         unsigned long orig_jiffies = jiffies;
260         struct mpc_i2c *i2c = i2c_get_adapdata(adap);
261
262         mpc_i2c_start(i2c);
263
264         /* Allow bus up to 1s to become not busy */
265         while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
266                 if (signal_pending(current)) {
267                         pr_debug("I2C: Interrupted\n");
268                         writeccr(i2c, 0);
269                         return -EINTR;
270                 }
271                 if (time_after(jiffies, orig_jiffies + HZ)) {
272                         pr_debug("I2C: timeout\n");
273                         if (readb(i2c->base + MPC_I2C_SR) ==
274                             (CSR_MCF | CSR_MBB | CSR_RXAK))
275                                 mpc_i2c_fixup(i2c);
276                         return -EIO;
277                 }
278                 schedule();
279         }
280
281         for (i = 0; ret >= 0 && i < num; i++) {
282                 pmsg = &msgs[i];
283                 pr_debug("Doing %s %d bytes to 0x%02x - %d of %d messages\n",
284                          pmsg->flags & I2C_M_RD ? "read" : "write",
285                          pmsg->len, pmsg->addr, i + 1, num);
286                 if (pmsg->flags & I2C_M_RD)
287                         ret =
288                             mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
289                 else
290                         ret =
291                             mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
292         }
293         mpc_i2c_stop(i2c);
294         return (ret < 0) ? ret : num;
295 }
296
297 static u32 mpc_functionality(struct i2c_adapter *adap)
298 {
299         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
300 }
301
302 static const struct i2c_algorithm mpc_algo = {
303         .master_xfer = mpc_xfer,
304         .functionality = mpc_functionality,
305 };
306
307 static struct i2c_adapter mpc_ops = {
308         .owner = THIS_MODULE,
309         .name = "MPC adapter",
310         .algo = &mpc_algo,
311         .timeout = HZ,
312 };
313
314 static int __devinit fsl_i2c_probe(struct of_device *op, const struct of_device_id *match)
315 {
316         int result = 0;
317         struct mpc_i2c *i2c;
318
319         i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
320         if (!i2c)
321                 return -ENOMEM;
322
323         if (of_get_property(op->node, "dfsrr", NULL))
324                 i2c->flags |= FSL_I2C_DEV_SEPARATE_DFSRR;
325
326         if (of_device_is_compatible(op->node, "fsl,mpc5200-i2c") ||
327                         of_device_is_compatible(op->node, "mpc5200-i2c"))
328                 i2c->flags |= FSL_I2C_DEV_CLOCK_5200;
329
330         init_waitqueue_head(&i2c->queue);
331
332         i2c->base = of_iomap(op->node, 0);
333         if (!i2c->base) {
334                 printk(KERN_ERR "i2c-mpc - failed to map controller\n");
335                 result = -ENOMEM;
336                 goto fail_map;
337         }
338
339         i2c->irq = irq_of_parse_and_map(op->node, 0);
340         if (i2c->irq != NO_IRQ) { /* i2c->irq = NO_IRQ implies polling */
341                 result = request_irq(i2c->irq, mpc_i2c_isr,
342                                      IRQF_SHARED, "i2c-mpc", i2c);
343                 if (result < 0) {
344                         printk(KERN_ERR "i2c-mpc - failed to attach interrupt\n");
345                         goto fail_request;
346                 }
347         }
348         
349         mpc_i2c_setclock(i2c);
350
351         dev_set_drvdata(&op->dev, i2c);
352
353         i2c->adap = mpc_ops;
354         i2c_set_adapdata(&i2c->adap, i2c);
355         i2c->adap.dev.parent = &op->dev;
356
357         result = i2c_add_adapter(&i2c->adap);
358         if (result < 0) {
359                 printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
360                 goto fail_add;
361         }
362         of_register_i2c_devices(&i2c->adap, op->node);
363
364         return result;
365
366  fail_add:
367         dev_set_drvdata(&op->dev, NULL);
368         free_irq(i2c->irq, i2c);
369  fail_request:
370         irq_dispose_mapping(i2c->irq);
371         iounmap(i2c->base);
372  fail_map:
373         kfree(i2c);
374         return result;
375 };
376
377 static int __devexit fsl_i2c_remove(struct of_device *op)
378 {
379         struct mpc_i2c *i2c = dev_get_drvdata(&op->dev);
380
381         i2c_del_adapter(&i2c->adap);
382         dev_set_drvdata(&op->dev, NULL);
383
384         if (i2c->irq != NO_IRQ)
385                 free_irq(i2c->irq, i2c);
386
387         irq_dispose_mapping(i2c->irq);
388         iounmap(i2c->base);
389         kfree(i2c);
390         return 0;
391 };
392
393 static const struct of_device_id mpc_i2c_of_match[] = {
394         {.compatible = "fsl-i2c",},
395         {},
396 };
397 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
398
399
400 /* Structure for a device driver */
401 static struct of_platform_driver mpc_i2c_driver = {
402         .match_table    = mpc_i2c_of_match,
403         .probe          = fsl_i2c_probe,
404         .remove         = __devexit_p(fsl_i2c_remove),
405         .driver         = {
406                 .owner  = THIS_MODULE,
407                 .name   = DRV_NAME,
408         },
409 };
410
411 static int __init fsl_i2c_init(void)
412 {
413         int rv;
414
415         rv = of_register_platform_driver(&mpc_i2c_driver);
416         if (rv)
417                 printk(KERN_ERR DRV_NAME 
418                        " of_register_platform_driver failed (%i)\n", rv);
419         return rv;
420 }
421
422 static void __exit fsl_i2c_exit(void)
423 {
424         of_unregister_platform_driver(&mpc_i2c_driver);
425 }
426
427 module_init(fsl_i2c_init);
428 module_exit(fsl_i2c_exit);
429
430 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
431 MODULE_DESCRIPTION
432     ("I2C-Bus adapter for MPC107 bridge and MPC824x/85xx/52xx processors");
433 MODULE_LICENSE("GPL");