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   1 /*
   2  * MPC8555 CDS Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12
  13 / {
  14         model = "MPC8555CDS";
  15         compatible = "MPC8555CDS", "MPC85xxCDS";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         cpus {
  20                 #cpus = <1>;
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 PowerPC,8555@0 {
  25                         device_type = "cpu";
  26                         reg = <0>;
  27                         d-cache-line-size = <20>;       // 32 bytes
  28                         i-cache-line-size = <20>;       // 32 bytes
  29                         d-cache-size = <8000>;          // L1, 32K
  30                         i-cache-size = <8000>;          // L1, 32K
  31                         timebase-frequency = <0>;       //  33 MHz, from uboot
  32                         bus-frequency = <0>;    // 166 MHz
  33                         clock-frequency = <0>;  // 825 MHz, from uboot
  34                         32-bit;
  35                 };
  36         };
  37
  38         memory {
  39                 device_type = "memory";
  40                 reg = <00000000 08000000>;      // 128M at 0x0
  41         };
  42
  43         soc8555@e0000000 {
  44                 #address-cells = <1>;
  45                 #size-cells = <1>;
  46                 #interrupt-cells = <2>;
  47                 device_type = "soc";
  48                 ranges = <0 e0000000 00100000>;
  49                 reg = <e0000000 00100000>;      // CCSRBAR 1M
  50                 bus-frequency = <0>;
  51
  52                 i2c@3000 {
  53                         device_type = "i2c";
  54                         compatible = "fsl-i2c";
  55                         reg = <3000 100>;
  56                         interrupts = <1b 2>;
  57                         interrupt-parent = <&mpic>;
  58                         dfsrr;
  59                 };
  60
  61                 mdio@24520 {
  62                         #address-cells = <1>;
  63                         #size-cells = <0>;
  64                         device_type = "mdio";
  65                         compatible = "gianfar";
  66                         reg = <24520 20>;
  67                         phy0: ethernet-phy@0 {
  68                                 interrupt-parent = <&mpic>;
  69                                 interrupts = <35 0>;
  70                                 reg = <0>;
  71                                 device_type = "ethernet-phy";
  72                         };
  73                         phy1: ethernet-phy@1 {
  74                                 interrupt-parent = <&mpic>;
  75                                 interrupts = <35 0>;
  76                                 reg = <1>;
  77                                 device_type = "ethernet-phy";
  78                         };
  79                 };
  80
  81                 ethernet@24000 {
  82                         #address-cells = <1>;
  83                         #size-cells = <0>;
  84                         device_type = "network";
  85                         model = "TSEC";
  86                         compatible = "gianfar";
  87                         reg = <24000 1000>;
  88                         local-mac-address = [ 00 E0 0C 00 73 00 ];
  89                         interrupts = <0d 2 0e 2 12 2>;
  90                         interrupt-parent = <&mpic>;
  91                         phy-handle = <&phy0>;
  92                 };
  93
  94                 ethernet@25000 {
  95                         #address-cells = <1>;
  96                         #size-cells = <0>;
  97                         device_type = "network";
  98                         model = "TSEC";
  99                         compatible = "gianfar";
 100                         reg = <25000 1000>;
 101                         local-mac-address = [ 00 E0 0C 00 73 01 ];
 102                         interrupts = <13 2 14 2 18 2>;
 103                         interrupt-parent = <&mpic>;
 104                         phy-handle = <&phy1>;
 105                 };
 106
 107                 serial@4500 {
 108                         device_type = "serial";
 109                         compatible = "ns16550";
 110                         reg = <4500 100>;       // reg base, size
 111                         clock-frequency = <0>;  // should we fill in in uboot?
 112                         interrupts = <1a 2>;
 113                         interrupt-parent = <&mpic>;
 114                 };
 115
 116                 serial@4600 {
 117                         device_type = "serial";
 118                         compatible = "ns16550";
 119                         reg = <4600 100>;       // reg base, size
 120                         clock-frequency = <0>;  // should we fill in in uboot?
 121                         interrupts = <1a 2>;
 122                         interrupt-parent = <&mpic>;
 123                 };
 124
 125                 pci1: pci@8000 {
 126                         interrupt-map-mask = <1f800 0 0 7>;
 127                         interrupt-map = <
 128
 129                                 /* IDSEL 0x10 */
 130                                 08000 0 0 1 &mpic 30 1
 131                                 08000 0 0 2 &mpic 31 1
 132                                 08000 0 0 3 &mpic 32 1
 133                                 08000 0 0 4 &mpic 33 1
 134
 135                                 /* IDSEL 0x11 */
 136                                 08800 0 0 1 &mpic 30 1
 137                                 08800 0 0 2 &mpic 31 1
 138                                 08800 0 0 3 &mpic 32 1
 139                                 08800 0 0 4 &mpic 33 1
 140
 141                                 /* IDSEL 0x12 (Slot 1) */
 142                                 09000 0 0 1 &mpic 30 1
 143                                 09000 0 0 2 &mpic 31 1
 144                                 09000 0 0 3 &mpic 32 1
 145                                 09000 0 0 4 &mpic 33 1
 146
 147                                 /* IDSEL 0x13 (Slot 2) */
 148                                 09800 0 0 1 &mpic 31 1
 149                                 09800 0 0 2 &mpic 32 1
 150                                 09800 0 0 3 &mpic 33 1
 151                                 09800 0 0 4 &mpic 30 1
 152
 153                                 /* IDSEL 0x14 (Slot 3) */
 154                                 0a000 0 0 1 &mpic 32 1
 155                                 0a000 0 0 2 &mpic 33 1
 156                                 0a000 0 0 3 &mpic 30 1
 157                                 0a000 0 0 4 &mpic 31 1
 158
 159                                 /* IDSEL 0x15 (Slot 4) */
 160                                 0a800 0 0 1 &mpic 33 1
 161                                 0a800 0 0 2 &mpic 30 1
 162                                 0a800 0 0 3 &mpic 31 1
 163                                 0a800 0 0 4 &mpic 32 1
 164
 165                                 /* Bus 1 (Tundra Bridge) */
 166                                 /* IDSEL 0x12 (ISA bridge) */
 167                                 19000 0 0 1 &mpic 30 1
 168                                 19000 0 0 2 &mpic 31 1
 169                                 19000 0 0 3 &mpic 32 1
 170                                 19000 0 0 4 &mpic 33 1>;
 171                         interrupt-parent = <&mpic>;
 172                         interrupts = <08 2>;
 173                         bus-range = <0 0>;
 174                         ranges = <02000000 0 80000000 80000000 0 20000000
 175                                   01000000 0 00000000 e2000000 0 00100000>;
 176                         clock-frequency = <3f940aa>;
 177                         #interrupt-cells = <1>;
 178                         #size-cells = <2>;
 179                         #address-cells = <3>;
 180                         reg = <8000 1000>;
 181                         compatible = "85xx";
 182                         device_type = "pci";
 183
 184                         i8259@19000 {
 185                                 clock-frequency = <0>;
 186                                 interrupt-controller;
 187                                 device_type = "interrupt-controller";
 188                                 reg = <19000 0 0 0 1>;
 189                                 #address-cells = <0>;
 190                                 #interrupt-cells = <2>;
 191                                 built-in;
 192                                 compatible = "chrp,iic";
 193                                 big-endian;
 194                                 interrupts = <1>;
 195                                 interrupt-parent = <&pci1>;
 196                         };
 197                 };
 198
 199                 pci@9000 {
 200                         interrupt-map-mask = <f800 0 0 7>;
 201                         interrupt-map = <
 202
 203                                 /* IDSEL 0x15 */
 204                                 a800 0 0 1 &mpic 3b 1
 205                                 a800 0 0 2 &mpic 3b 1
 206                                 a800 0 0 3 &mpic 3b 1
 207                                 a800 0 0 4 &mpic 3b 1>;
 208                         interrupt-parent = <&mpic>;
 209                         interrupts = <09 2>;
 210                         bus-range = <0 0>;
 211                         ranges = <02000000 0 a0000000 a0000000 0 20000000
 212                                   01000000 0 00000000 e3000000 0 00100000>;
 213                         clock-frequency = <3f940aa>;
 214                         #interrupt-cells = <1>;
 215                         #size-cells = <2>;
 216                         #address-cells = <3>;
 217                         reg = <9000 1000>;
 218                         compatible = "85xx";
 219                         device_type = "pci";
 220                 };
 221
 222                 mpic: pic@40000 {
 223                         clock-frequency = <0>;
 224                         interrupt-controller;
 225                         #address-cells = <0>;
 226                         #interrupt-cells = <2>;
 227                         reg = <40000 40000>;
 228                         built-in;
 229                         compatible = "chrp,open-pic";
 230                         device_type = "open-pic";
 231                         big-endian;
 232                 };
 233         };
 234 };