git.oblomov.eu Git - linux-2.6/blob - arch/x86/oprofile/op_model_athlon.c

   1 /*
   2  * @file op_model_athlon.c
   3  * athlon / K7 / K8 / Family 10h model-specific MSR operations
   4  *
   5  * @remark Copyright 2002-2008 OProfile authors
   6  * @remark Read the file COPYING
   7  *
   8  * @author John Levon
   9  * @author Philippe Elie
  10  * @author Graydon Hoare
  11  * @author Robert Richter <robert.richter@amd.com>
  12 */
  13
  14 #include <linux/oprofile.h>
  15 #include <asm/ptrace.h>
  16 #include <asm/msr.h>
  17 #include <asm/nmi.h>
  18
  19 #include "op_x86_model.h"
  20 #include "op_counter.h"
  21
  22 #define NUM_COUNTERS 4
  23 #define NUM_CONTROLS 4
  24
  25 #define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)
  26 #define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0)
  27 #define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1); } while (0)
  28 #define CTR_OVERFLOWED(n) (!((n) & (1U<<31)))
  29
  30 #define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)
  31 #define CTRL_READ(l, h, msrs, c) do {rdmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
  32 #define CTRL_WRITE(l, h, msrs, c) do {wrmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
  33 #define CTRL_SET_ACTIVE(n) (n |= (1<<22))
  34 #define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))
  35 #define CTRL_CLEAR_LO(x) (x &= (1<<21))
  36 #define CTRL_CLEAR_HI(x) (x &= 0xfffffcf0)
  37 #define CTRL_SET_ENABLE(val) (val |= 1<<20)
  38 #define CTRL_SET_USR(val, u) (val |= ((u & 1) << 16))
  39 #define CTRL_SET_KERN(val, k) (val |= ((k & 1) << 17))
  40 #define CTRL_SET_UM(val, m) (val |= (m << 8))
  41 #define CTRL_SET_EVENT_LOW(val, e) (val |= (e & 0xff))
  42 #define CTRL_SET_EVENT_HIGH(val, e) (val |= ((e >> 8) & 0xf))
  43 #define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9))
  44 #define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8))
  45
  46 static unsigned long reset_value[NUM_COUNTERS];
  47
  48 /* functions for op_amd_spec */
  49
  50 static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
  51 {
  52         int i;
  53
  54         for (i = 0; i < NUM_COUNTERS; i++) {
  55                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
  56                         msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
  57                 else
  58                         msrs->counters[i].addr = 0;
  59         }
  60
  61         for (i = 0; i < NUM_CONTROLS; i++) {
  62                 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
  63                         msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
  64                 else
  65                         msrs->controls[i].addr = 0;
  66         }
  67 }
  68
  69
  70 static void op_amd_setup_ctrs(struct op_msrs const * const msrs)
  71 {
  72         unsigned int low, high;
  73         int i;
  74
  75         /* clear all counters */
  76         for (i = 0 ; i < NUM_CONTROLS; ++i) {
  77                 if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
  78                         continue;
  79                 CTRL_READ(low, high, msrs, i);
  80                 CTRL_CLEAR_LO(low);
  81                 CTRL_CLEAR_HI(high);
  82                 CTRL_WRITE(low, high, msrs, i);
  83         }
  84
  85         /* avoid a false detection of ctr overflows in NMI handler */
  86         for (i = 0; i < NUM_COUNTERS; ++i) {
  87                 if (unlikely(!CTR_IS_RESERVED(msrs, i)))
  88                         continue;
  89                 CTR_WRITE(1, msrs, i);
  90         }
  91
  92         /* enable active counters */
  93         for (i = 0; i < NUM_COUNTERS; ++i) {
  94                 if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
  95                         reset_value[i] = counter_config[i].count;
  96
  97                         CTR_WRITE(counter_config[i].count, msrs, i);
  98
  99                         CTRL_READ(low, high, msrs, i);
 100                         CTRL_CLEAR_LO(low);
 101                         CTRL_CLEAR_HI(high);
 102                         CTRL_SET_ENABLE(low);
 103                         CTRL_SET_USR(low, counter_config[i].user);
 104                         CTRL_SET_KERN(low, counter_config[i].kernel);
 105                         CTRL_SET_UM(low, counter_config[i].unit_mask);
 106                         CTRL_SET_EVENT_LOW(low, counter_config[i].event);
 107                         CTRL_SET_EVENT_HIGH(high, counter_config[i].event);
 108                         CTRL_SET_HOST_ONLY(high, 0);
 109                         CTRL_SET_GUEST_ONLY(high, 0);
 110
 111                         CTRL_WRITE(low, high, msrs, i);
 112                 } else {
 113                         reset_value[i] = 0;
 114                 }
 115         }
 116 }
 117
 118
 119 static int op_amd_check_ctrs(struct pt_regs * const regs,
 120                              struct op_msrs const * const msrs)
 121 {
 122         unsigned int low, high;
 123         int i;
 124
 125         for (i = 0 ; i < NUM_COUNTERS; ++i) {
 126                 if (!reset_value[i])
 127                         continue;
 128                 CTR_READ(low, high, msrs, i);
 129                 if (CTR_OVERFLOWED(low)) {
 130                         oprofile_add_sample(regs, i);
 131                         CTR_WRITE(reset_value[i], msrs, i);
 132                 }
 133         }
 134
 135         /* See op_model_ppro.c */
 136         return 1;
 137 }
 138
 139
 140 static void op_amd_start(struct op_msrs const * const msrs)
 141 {
 142         unsigned int low, high;
 143         int i;
 144         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
 145                 if (reset_value[i]) {
 146                         CTRL_READ(low, high, msrs, i);
 147                         CTRL_SET_ACTIVE(low);
 148                         CTRL_WRITE(low, high, msrs, i);
 149                 }
 150         }
 151 }
 152
 153
 154 static void op_amd_stop(struct op_msrs const * const msrs)
 155 {
 156         unsigned int low, high;
 157         int i;
 158
 159         /* Subtle: stop on all counters to avoid race with
 160          * setting our pm callback */
 161         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
 162                 if (!reset_value[i])
 163                         continue;
 164                 CTRL_READ(low, high, msrs, i);
 165                 CTRL_SET_INACTIVE(low);
 166                 CTRL_WRITE(low, high, msrs, i);
 167         }
 168 }
 169
 170 static void op_amd_shutdown(struct op_msrs const * const msrs)
 171 {
 172         int i;
 173
 174         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
 175                 if (CTR_IS_RESERVED(msrs, i))
 176                         release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
 177         }
 178         for (i = 0 ; i < NUM_CONTROLS ; ++i) {
 179                 if (CTRL_IS_RESERVED(msrs, i))
 180                         release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
 181         }
 182 }
 183
 184 static int op_amd_init(struct oprofile_operations *ops)
 185 {
 186         return 0;
 187 }
 188
 189 static void op_amd_exit(void)
 190 {
 191 }
 192
 193 struct op_x86_model_spec const op_amd_spec = {
 194         .init = op_amd_init,
 195         .exit = op_amd_exit,
 196         .num_counters = NUM_COUNTERS,
 197         .num_controls = NUM_CONTROLS,
 198         .fill_in_addresses = &op_amd_fill_in_addresses,
 199         .setup_ctrs = &op_amd_setup_ctrs,
 200         .check_ctrs = &op_amd_check_ctrs,
 201         .start = &op_amd_start,
 202         .stop = &op_amd_stop,
 203         .shutdown = &op_amd_shutdown
 204 };