1 #ifndef __ASM_CPU_SH3_DMA_H
2 #define __ASM_CPU_SH3_DMA_H
4 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
5 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
6 defined(CONFIG_CPU_SUBTYPE_SH7710) || \
7 defined(CONFIG_CPU_SUBTYPE_SH7712)
8 #define SH_DMAC_BASE0 0xa4010020
9 #else /* SH7705/06/07/09 */
10 #define SH_DMAC_BASE0 0xa4000020
16 /* Definitions for the SuperH DMAC */
17 #define TM_BURST 0x00000020
18 #define TS_8 0x00000000
19 #define TS_16 0x00000008
20 #define TS_32 0x00000010
21 #define TS_128 0x00000018
23 #define CHCR_TS_MASK 0x18
24 #define CHCR_TS_SHIFT 3
26 #define DMAOR_INIT DMAOR_DME
29 * The SuperH DMAC supports a number of transmit sizes, we list them here,
30 * with their respective values as they appear in the CHCR registers.
39 static unsigned int ts_shift[] __maybe_unused = {
46 #endif /* __ASM_CPU_SH3_DMA_H */