git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "ath9k.h"
  21 #include "initvals.h"
  22
  23 static int btcoex_enable;
  24 module_param(btcoex_enable, bool, 0);
  25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
  26
  27 #define ATH9K_CLOCK_RATE_CCK            22
  28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  30
  31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
  33                               enum ath9k_ht_macmode macmode);
  34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  35                               struct ar5416_eeprom_def *pEepData,
  36                               u32 reg, u32 value);
  37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  39
  40 /********************/
  41 /* Helper Functions */
  42 /********************/
  43
  44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
  45 {
  46         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  47
  48         if (!ah->curchan) /* should really check for CCK instead */
  49                 return clks / ATH9K_CLOCK_RATE_CCK;
  50         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  51                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
  52
  53         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
  54 }
  55
  56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
  57 {
  58         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  59
  60         if (conf_is_ht40(conf))
  61                 return ath9k_hw_mac_usec(ah, clks) / 2;
  62         else
  63                 return ath9k_hw_mac_usec(ah, clks);
  64 }
  65
  66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  67 {
  68         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  69
  70         if (!ah->curchan) /* should really check for CCK instead */
  71                 return usecs *ATH9K_CLOCK_RATE_CCK;
  72         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  73                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  74         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  75 }
  76
  77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  78 {
  79         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  80
  81         if (conf_is_ht40(conf))
  82                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  83         else
  84                 return ath9k_hw_mac_clks(ah, usecs);
  85 }
  86
  87 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
  88 {
  89         int i;
  90
  91         BUG_ON(timeout < AH_TIME_QUANTUM);
  92
  93         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
  94                 if ((REG_READ(ah, reg) & mask) == val)
  95                         return true;
  96
  97                 udelay(AH_TIME_QUANTUM);
  98         }
  99
 100         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 101                 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 102                 timeout, reg, REG_READ(ah, reg), mask, val);
 103
 104         return false;
 105 }
 106
 107 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 108 {
 109         u32 retval;
 110         int i;
 111
 112         for (i = 0, retval = 0; i < n; i++) {
 113                 retval = (retval << 1) | (val & 1);
 114                 val >>= 1;
 115         }
 116         return retval;
 117 }
 118
 119 bool ath9k_get_channel_edges(struct ath_hw *ah,
 120                              u16 flags, u16 *low,
 121                              u16 *high)
 122 {
 123         struct ath9k_hw_capabilities *pCap = &ah->caps;
 124
 125         if (flags & CHANNEL_5GHZ) {
 126                 *low = pCap->low_5ghz_chan;
 127                 *high = pCap->high_5ghz_chan;
 128                 return true;
 129         }
 130         if ((flags & CHANNEL_2GHZ)) {
 131                 *low = pCap->low_2ghz_chan;
 132                 *high = pCap->high_2ghz_chan;
 133                 return true;
 134         }
 135         return false;
 136 }
 137
 138 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 139                            struct ath_rate_table *rates,
 140                            u32 frameLen, u16 rateix,
 141                            bool shortPreamble)
 142 {
 143         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 144         u32 kbps;
 145
 146         kbps = rates->info[rateix].ratekbps;
 147
 148         if (kbps == 0)
 149                 return 0;
 150
 151         switch (rates->info[rateix].phy) {
 152         case WLAN_RC_PHY_CCK:
 153                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 154                 if (shortPreamble && rates->info[rateix].short_preamble)
 155                         phyTime >>= 1;
 156                 numBits = frameLen << 3;
 157                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 158                 break;
 159         case WLAN_RC_PHY_OFDM:
 160                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 161                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 162                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 163                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 164                         txTime = OFDM_SIFS_TIME_QUARTER
 165                                 + OFDM_PREAMBLE_TIME_QUARTER
 166                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 167                 } else if (ah->curchan &&
 168                            IS_CHAN_HALF_RATE(ah->curchan)) {
 169                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 170                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 171                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 172                         txTime = OFDM_SIFS_TIME_HALF +
 173                                 OFDM_PREAMBLE_TIME_HALF
 174                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 175                 } else {
 176                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 177                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 178                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 179                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 180                                 + (numSymbols * OFDM_SYMBOL_TIME);
 181                 }
 182                 break;
 183         default:
 184                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 185                         "Unknown phy %u (rate ix %u)\n",
 186                         rates->info[rateix].phy, rateix);
 187                 txTime = 0;
 188                 break;
 189         }
 190
 191         return txTime;
 192 }
 193
 194 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 195                                   struct ath9k_channel *chan,
 196                                   struct chan_centers *centers)
 197 {
 198         int8_t extoff;
 199
 200         if (!IS_CHAN_HT40(chan)) {
 201                 centers->ctl_center = centers->ext_center =
 202                         centers->synth_center = chan->channel;
 203                 return;
 204         }
 205
 206         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 207             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 208                 centers->synth_center =
 209                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 210                 extoff = 1;
 211         } else {
 212                 centers->synth_center =
 213                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 214                 extoff = -1;
 215         }
 216
 217         centers->ctl_center =
 218                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 219         centers->ext_center =
 220                 centers->synth_center + (extoff *
 221                          ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 222                           HT40_CHANNEL_CENTER_SHIFT : 15));
 223 }
 224
 225 /******************/
 226 /* Chip Revisions */
 227 /******************/
 228
 229 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 230 {
 231         u32 val;
 232
 233         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 234
 235         if (val == 0xFF) {
 236                 val = REG_READ(ah, AR_SREV);
 237                 ah->hw_version.macVersion =
 238                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 239                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 240                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 241         } else {
 242                 if (!AR_SREV_9100(ah))
 243                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 244
 245                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 246
 247                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 248                         ah->is_pciexpress = true;
 249         }
 250 }
 251
 252 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 253 {
 254         u32 val;
 255         int i;
 256
 257         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 258
 259         for (i = 0; i < 8; i++)
 260                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 261         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 262         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 263
 264         return ath9k_hw_reverse_bits(val, 8);
 265 }
 266
 267 /************************************/
 268 /* HW Attach, Detach, Init Routines */
 269 /************************************/
 270
 271 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 272 {
 273         if (AR_SREV_9100(ah))
 274                 return;
 275
 276         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 277         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 278         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 279         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 280         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 281         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 282         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 283         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 284         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 285
 286         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 287 }
 288
 289 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 290 {
 291         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 292         u32 regHold[2];
 293         u32 patternData[4] = { 0x55555555,
 294                                0xaaaaaaaa,
 295                                0x66666666,
 296                                0x99999999 };
 297         int i, j;
 298
 299         for (i = 0; i < 2; i++) {
 300                 u32 addr = regAddr[i];
 301                 u32 wrData, rdData;
 302
 303                 regHold[i] = REG_READ(ah, addr);
 304                 for (j = 0; j < 0x100; j++) {
 305                         wrData = (j << 16) | j;
 306                         REG_WRITE(ah, addr, wrData);
 307                         rdData = REG_READ(ah, addr);
 308                         if (rdData != wrData) {
 309                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 310                                         "address test failed "
 311                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 312                                         addr, wrData, rdData);
 313                                 return false;
 314                         }
 315                 }
 316                 for (j = 0; j < 4; j++) {
 317                         wrData = patternData[j];
 318                         REG_WRITE(ah, addr, wrData);
 319                         rdData = REG_READ(ah, addr);
 320                         if (wrData != rdData) {
 321                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 322                                         "address test failed "
 323                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 324                                         addr, wrData, rdData);
 325                                 return false;
 326                         }
 327                 }
 328                 REG_WRITE(ah, regAddr[i], regHold[i]);
 329         }
 330         udelay(100);
 331
 332         return true;
 333 }
 334
 335 static const char *ath9k_hw_devname(u16 devid)
 336 {
 337         switch (devid) {
 338         case AR5416_DEVID_PCI:
 339                 return "Atheros 5416";
 340         case AR5416_DEVID_PCIE:
 341                 return "Atheros 5418";
 342         case AR9160_DEVID_PCI:
 343                 return "Atheros 9160";
 344         case AR5416_AR9100_DEVID:
 345                 return "Atheros 9100";
 346         case AR9280_DEVID_PCI:
 347         case AR9280_DEVID_PCIE:
 348                 return "Atheros 9280";
 349         case AR9285_DEVID_PCIE:
 350                 return "Atheros 9285";
 351         }
 352
 353         return NULL;
 354 }
 355
 356 static void ath9k_hw_set_defaults(struct ath_hw *ah)
 357 {
 358         int i;
 359
 360         ah->config.dma_beacon_response_time = 2;
 361         ah->config.sw_beacon_response_time = 10;
 362         ah->config.additional_swba_backoff = 0;
 363         ah->config.ack_6mb = 0x0;
 364         ah->config.cwm_ignore_extcca = 0;
 365         ah->config.pcie_powersave_enable = 0;
 366         ah->config.pcie_l1skp_enable = 0;
 367         ah->config.pcie_clock_req = 0;
 368         ah->config.pcie_power_reset = 0x100;
 369         ah->config.pcie_restore = 0;
 370         ah->config.pcie_waen = 0;
 371         ah->config.analog_shiftreg = 1;
 372         ah->config.ht_enable = 1;
 373         ah->config.ofdm_trig_low = 200;
 374         ah->config.ofdm_trig_high = 500;
 375         ah->config.cck_trig_high = 200;
 376         ah->config.cck_trig_low = 100;
 377         ah->config.enable_ani = 1;
 378         ah->config.noise_immunity_level = 4;
 379         ah->config.ofdm_weaksignal_det = 1;
 380         ah->config.cck_weaksignal_thr = 0;
 381         ah->config.spur_immunity_level = 2;
 382         ah->config.firstep_level = 0;
 383         ah->config.rssi_thr_high = 40;
 384         ah->config.rssi_thr_low = 7;
 385         ah->config.diversity_control = 0;
 386         ah->config.antenna_switch_swap = 0;
 387
 388         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 389                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 390                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 391         }
 392
 393         ah->config.intr_mitigation = 1;
 394
 395         /*
 396          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 397          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 398          * This means we use it for all AR5416 devices, and the few
 399          * minor PCI AR9280 devices out there.
 400          *
 401          * Serialization is required because these devices do not handle
 402          * well the case of two concurrent reads/writes due to the latency
 403          * involved. During one read/write another read/write can be issued
 404          * on another CPU while the previous read/write may still be working
 405          * on our hardware, if we hit this case the hardware poops in a loop.
 406          * We prevent this by serializing reads and writes.
 407          *
 408          * This issue is not present on PCI-Express devices or pre-AR5416
 409          * devices (legacy, 802.11abg).
 410          */
 411         if (num_possible_cpus() > 1)
 412                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 413 }
 414
 415 static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
 416                                         int *status)
 417 {
 418         struct ath_hw *ah;
 419
 420         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
 421         if (ah == NULL) {
 422                 DPRINTF(sc, ATH_DBG_FATAL,
 423                         "Cannot allocate memory for state block\n");
 424                 *status = -ENOMEM;
 425                 return NULL;
 426         }
 427
 428         ah->ah_sc = sc;
 429         ah->hw_version.magic = AR5416_MAGIC;
 430         ah->regulatory.country_code = CTRY_DEFAULT;
 431         ah->hw_version.devid = devid;
 432         ah->hw_version.subvendorid = 0;
 433
 434         ah->ah_flags = 0;
 435         if ((devid == AR5416_AR9100_DEVID))
 436                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 437         if (!AR_SREV_9100(ah))
 438                 ah->ah_flags = AH_USE_EEPROM;
 439
 440         ah->regulatory.power_limit = MAX_RATE_POWER;
 441         ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
 442         ah->atim_window = 0;
 443         ah->diversity_control = ah->config.diversity_control;
 444         ah->antenna_switch_swap =
 445                 ah->config.antenna_switch_swap;
 446         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 447         ah->beacon_interval = 100;
 448         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 449         ah->slottime = (u32) -1;
 450         ah->acktimeout = (u32) -1;
 451         ah->ctstimeout = (u32) -1;
 452         ah->globaltxtimeout = (u32) -1;
 453
 454         ah->gbeacon_rate = 0;
 455
 456         return ah;
 457 }
 458
 459 static int ath9k_hw_rfattach(struct ath_hw *ah)
 460 {
 461         bool rfStatus = false;
 462         int ecode = 0;
 463
 464         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 465         if (!rfStatus) {
 466                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 467                         "RF setup failed, status %u\n", ecode);
 468                 return ecode;
 469         }
 470
 471         return 0;
 472 }
 473
 474 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 475 {
 476         u32 val;
 477
 478         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 479
 480         val = ath9k_hw_get_radiorev(ah);
 481         switch (val & AR_RADIO_SREV_MAJOR) {
 482         case 0:
 483                 val = AR_RAD5133_SREV_MAJOR;
 484                 break;
 485         case AR_RAD5133_SREV_MAJOR:
 486         case AR_RAD5122_SREV_MAJOR:
 487         case AR_RAD2133_SREV_MAJOR:
 488         case AR_RAD2122_SREV_MAJOR:
 489                 break;
 490         default:
 491                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 492                         "5G Radio Chip Rev 0x%02X is not "
 493                         "supported by this driver\n",
 494                         ah->hw_version.analog5GhzRev);
 495                 return -EOPNOTSUPP;
 496         }
 497
 498         ah->hw_version.analog5GhzRev = val;
 499
 500         return 0;
 501 }
 502
 503 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 504 {
 505         u32 sum;
 506         int i;
 507         u16 eeval;
 508
 509         sum = 0;
 510         for (i = 0; i < 3; i++) {
 511                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 512                 sum += eeval;
 513                 ah->macaddr[2 * i] = eeval >> 8;
 514                 ah->macaddr[2 * i + 1] = eeval & 0xff;
 515         }
 516         if (sum == 0 || sum == 0xffff * 3) {
 517                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 518                         "mac address read failed: %pM\n",
 519                         ah->macaddr);
 520                 return -EADDRNOTAVAIL;
 521         }
 522
 523         return 0;
 524 }
 525
 526 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 527 {
 528         u32 rxgain_type;
 529
 530         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 531                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 532
 533                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 534                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 535                         ar9280Modes_backoff_13db_rxgain_9280_2,
 536                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 537                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 538                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 539                         ar9280Modes_backoff_23db_rxgain_9280_2,
 540                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 541                 else
 542                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 543                         ar9280Modes_original_rxgain_9280_2,
 544                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 545         } else {
 546                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 547                         ar9280Modes_original_rxgain_9280_2,
 548                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 549         }
 550 }
 551
 552 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 553 {
 554         u32 txgain_type;
 555
 556         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 557                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 558
 559                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 560                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 561                         ar9280Modes_high_power_tx_gain_9280_2,
 562                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 563                 else
 564                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 565                         ar9280Modes_original_tx_gain_9280_2,
 566                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 567         } else {
 568                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 569                 ar9280Modes_original_tx_gain_9280_2,
 570                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 571         }
 572 }
 573
 574 static int ath9k_hw_post_attach(struct ath_hw *ah)
 575 {
 576         int ecode;
 577
 578         if (!ath9k_hw_chip_test(ah)) {
 579                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 580                         "hardware self-test failed\n");
 581                 return -ENODEV;
 582         }
 583
 584         ecode = ath9k_hw_rf_claim(ah);
 585         if (ecode != 0)
 586                 return ecode;
 587
 588         ecode = ath9k_hw_eeprom_attach(ah);
 589         if (ecode != 0)
 590                 return ecode;
 591         ecode = ath9k_hw_rfattach(ah);
 592         if (ecode != 0)
 593                 return ecode;
 594
 595         if (!AR_SREV_9100(ah)) {
 596                 ath9k_hw_ani_setup(ah);
 597                 ath9k_hw_ani_attach(ah);
 598         }
 599
 600         return 0;
 601 }
 602
 603 static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
 604                                          int *status)
 605 {
 606         struct ath_hw *ah;
 607         int ecode;
 608         u32 i, j;
 609
 610         ah = ath9k_hw_newstate(devid, sc, status);
 611         if (ah == NULL)
 612                 return NULL;
 613
 614         ath9k_hw_set_defaults(ah);
 615
 616         if (ah->config.intr_mitigation != 0)
 617                 ah->intr_mitigation = true;
 618
 619         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 620                 DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n");
 621                 ecode = -EIO;
 622                 goto bad;
 623         }
 624
 625         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 626                 DPRINTF(sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
 627                 ecode = -EIO;
 628                 goto bad;
 629         }
 630
 631         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 632                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 633                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 634                         ah->config.serialize_regmode =
 635                                 SER_REG_MODE_ON;
 636                 } else {
 637                         ah->config.serialize_regmode =
 638                                 SER_REG_MODE_OFF;
 639                 }
 640         }
 641
 642         DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
 643                 ah->config.serialize_regmode);
 644
 645         if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
 646             (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
 647             (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
 648             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
 649                 DPRINTF(sc, ATH_DBG_RESET,
 650                         "Mac Chip Rev 0x%02x.%x is not supported by "
 651                         "this driver\n", ah->hw_version.macVersion,
 652                         ah->hw_version.macRev);
 653                 ecode = -EOPNOTSUPP;
 654                 goto bad;
 655         }
 656
 657         if (AR_SREV_9100(ah)) {
 658                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 659                 ah->supp_cals = IQ_MISMATCH_CAL;
 660                 ah->is_pciexpress = false;
 661         }
 662         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 663
 664         if (AR_SREV_9160_10_OR_LATER(ah)) {
 665                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 666                         ah->iq_caldata.calData = &iq_cal_single_sample;
 667                         ah->adcgain_caldata.calData =
 668                                 &adc_gain_cal_single_sample;
 669                         ah->adcdc_caldata.calData =
 670                                 &adc_dc_cal_single_sample;
 671                         ah->adcdc_calinitdata.calData =
 672                                 &adc_init_dc_cal;
 673                 } else {
 674                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 675                         ah->adcgain_caldata.calData =
 676                                 &adc_gain_cal_multi_sample;
 677                         ah->adcdc_caldata.calData =
 678                                 &adc_dc_cal_multi_sample;
 679                         ah->adcdc_calinitdata.calData =
 680                                 &adc_init_dc_cal;
 681                 }
 682                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 683         }
 684
 685         ah->ani_function = ATH9K_ANI_ALL;
 686         if (AR_SREV_9280_10_OR_LATER(ah))
 687                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 688
 689         DPRINTF(sc, ATH_DBG_RESET,
 690                 "This Mac Chip Rev 0x%02x.%x is \n",
 691                 ah->hw_version.macVersion, ah->hw_version.macRev);
 692
 693         if (AR_SREV_9285_12_OR_LATER(ah)) {
 694
 695                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 696                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 697                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 698                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 699
 700                 if (ah->config.pcie_clock_req) {
 701                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 702                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 703                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 704                 } else {
 705                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 706                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 707                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 708                                   2);
 709                 }
 710         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 711                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 712                                ARRAY_SIZE(ar9285Modes_9285), 6);
 713                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 714                                ARRAY_SIZE(ar9285Common_9285), 2);
 715
 716                 if (ah->config.pcie_clock_req) {
 717                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 718                         ar9285PciePhy_clkreq_off_L1_9285,
 719                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 720                 } else {
 721                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 722                         ar9285PciePhy_clkreq_always_on_L1_9285,
 723                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 724                 }
 725         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 726                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 727                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 728                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 729                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 730
 731                 if (ah->config.pcie_clock_req) {
 732                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 733                                ar9280PciePhy_clkreq_off_L1_9280,
 734                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 735                 } else {
 736                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 737                                ar9280PciePhy_clkreq_always_on_L1_9280,
 738                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 739                 }
 740                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 741                                ar9280Modes_fast_clock_9280_2,
 742                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 743         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 744                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 745                                ARRAY_SIZE(ar9280Modes_9280), 6);
 746                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 747                                ARRAY_SIZE(ar9280Common_9280), 2);
 748         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 749                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 750                                ARRAY_SIZE(ar5416Modes_9160), 6);
 751                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 752                                ARRAY_SIZE(ar5416Common_9160), 2);
 753                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 754                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 755                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 756                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 757                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 758                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 759                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 760                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 761                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 762                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 763                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 764                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 765                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 766                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 767                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 768                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 769                 if (AR_SREV_9160_11(ah)) {
 770                         INIT_INI_ARRAY(&ah->iniAddac,
 771                                        ar5416Addac_91601_1,
 772                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 773                 } else {
 774                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 775                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 776                 }
 777         } else if (AR_SREV_9100_OR_LATER(ah)) {
 778                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 779                                ARRAY_SIZE(ar5416Modes_9100), 6);
 780                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 781                                ARRAY_SIZE(ar5416Common_9100), 2);
 782                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 783                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 784                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 785                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 786                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 787                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 788                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 789                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 790                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 791                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 792                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 793                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 794                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 795                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 796                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 797                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 798                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 799                                ARRAY_SIZE(ar5416Addac_9100), 2);
 800         } else {
 801                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 802                                ARRAY_SIZE(ar5416Modes), 6);
 803                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 804                                ARRAY_SIZE(ar5416Common), 2);
 805                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 806                                ARRAY_SIZE(ar5416Bank0), 2);
 807                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 808                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 809                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 810                                ARRAY_SIZE(ar5416Bank1), 2);
 811                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 812                                ARRAY_SIZE(ar5416Bank2), 2);
 813                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 814                                ARRAY_SIZE(ar5416Bank3), 3);
 815                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 816                                ARRAY_SIZE(ar5416Bank6), 3);
 817                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 818                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 819                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 820                                ARRAY_SIZE(ar5416Bank7), 2);
 821                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 822                                ARRAY_SIZE(ar5416Addac), 2);
 823         }
 824
 825         if (ah->is_pciexpress)
 826                 ath9k_hw_configpcipowersave(ah, 0);
 827         else
 828                 ath9k_hw_disablepcie(ah);
 829
 830         ecode = ath9k_hw_post_attach(ah);
 831         if (ecode != 0)
 832                 goto bad;
 833
 834         if (AR_SREV_9285_12_OR_LATER(ah)) {
 835                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 836
 837                 /* txgain table */
 838                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 839                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 840                         ar9285Modes_high_power_tx_gain_9285_1_2,
 841                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 842                 } else {
 843                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 844                         ar9285Modes_original_tx_gain_9285_1_2,
 845                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
 846                 }
 847
 848         }
 849
 850         /* rxgain table */
 851         if (AR_SREV_9280_20(ah))
 852                 ath9k_hw_init_rxgain_ini(ah);
 853
 854         /* txgain table */
 855         if (AR_SREV_9280_20(ah))
 856                 ath9k_hw_init_txgain_ini(ah);
 857
 858         if (!ath9k_hw_fill_cap_info(ah)) {
 859                 DPRINTF(sc, ATH_DBG_RESET, "failed ath9k_hw_fill_cap_info\n");
 860                 ecode = -EINVAL;
 861                 goto bad;
 862         }
 863
 864         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
 865             test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
 866
 867                 /* EEPROM Fixup */
 868                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
 869                         u32 reg = INI_RA(&ah->iniModes, i, 0);
 870
 871                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
 872                                 u32 val = INI_RA(&ah->iniModes, i, j);
 873
 874                                 INI_RA(&ah->iniModes, i, j) =
 875                                         ath9k_hw_ini_fixup(ah,
 876                                                            &ah->eeprom.def,
 877                                                            reg, val);
 878                         }
 879                 }
 880         }
 881
 882         ecode = ath9k_hw_init_macaddr(ah);
 883         if (ecode != 0) {
 884                 DPRINTF(sc, ATH_DBG_RESET,
 885                         "failed initializing mac address\n");
 886                 goto bad;
 887         }
 888
 889         if (AR_SREV_9285(ah))
 890                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 891         else
 892                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 893
 894         ath9k_init_nfcal_hist_buffer(ah);
 895
 896         return ah;
 897 bad:
 898         if (ah)
 899                 ath9k_hw_detach(ah);
 900         if (status)
 901                 *status = ecode;
 902
 903         return NULL;
 904 }
 905
 906 static void ath9k_hw_init_bb(struct ath_hw *ah,
 907                              struct ath9k_channel *chan)
 908 {
 909         u32 synthDelay;
 910
 911         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 912         if (IS_CHAN_B(chan))
 913                 synthDelay = (4 * synthDelay) / 22;
 914         else
 915                 synthDelay /= 10;
 916
 917         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 918
 919         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 920 }
 921
 922 static void ath9k_hw_init_qos(struct ath_hw *ah)
 923 {
 924         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 925         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 926
 927         REG_WRITE(ah, AR_QOS_NO_ACK,
 928                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 929                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 930                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 931
 932         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 933         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 934         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 935         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 936         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 937 }
 938
 939 static void ath9k_hw_init_pll(struct ath_hw *ah,
 940                               struct ath9k_channel *chan)
 941 {
 942         u32 pll;
 943
 944         if (AR_SREV_9100(ah)) {
 945                 if (chan && IS_CHAN_5GHZ(chan))
 946                         pll = 0x1450;
 947                 else
 948                         pll = 0x1458;
 949         } else {
 950                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 951                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 952
 953                         if (chan && IS_CHAN_HALF_RATE(chan))
 954                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 955                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 956                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 957
 958                         if (chan && IS_CHAN_5GHZ(chan)) {
 959                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
 960
 961
 962                                 if (AR_SREV_9280_20(ah)) {
 963                                         if (((chan->channel % 20) == 0)
 964                                             || ((chan->channel % 10) == 0))
 965                                                 pll = 0x2850;
 966                                         else
 967                                                 pll = 0x142c;
 968                                 }
 969                         } else {
 970                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
 971                         }
 972
 973                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 974
 975                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 976
 977                         if (chan && IS_CHAN_HALF_RATE(chan))
 978                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 979                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 980                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 981
 982                         if (chan && IS_CHAN_5GHZ(chan))
 983                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
 984                         else
 985                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
 986                 } else {
 987                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
 988
 989                         if (chan && IS_CHAN_HALF_RATE(chan))
 990                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
 991                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 992                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
 993
 994                         if (chan && IS_CHAN_5GHZ(chan))
 995                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
 996                         else
 997                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
 998                 }
 999         }
1000         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1001
1002         udelay(RTC_PLL_SETTLE_DELAY);
1003
1004         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1005 }
1006
1007 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1008 {
1009         int rx_chainmask, tx_chainmask;
1010
1011         rx_chainmask = ah->rxchainmask;
1012         tx_chainmask = ah->txchainmask;
1013
1014         switch (rx_chainmask) {
1015         case 0x5:
1016                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1017                             AR_PHY_SWAP_ALT_CHAIN);
1018         case 0x3:
1019                 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1020                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1021                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1022                         break;
1023                 }
1024         case 0x1:
1025         case 0x2:
1026         case 0x7:
1027                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1028                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1029                 break;
1030         default:
1031                 break;
1032         }
1033
1034         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1035         if (tx_chainmask == 0x5) {
1036                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1037                             AR_PHY_SWAP_ALT_CHAIN);
1038         }
1039         if (AR_SREV_9100(ah))
1040                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1041                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1042 }
1043
1044 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1045                                           enum nl80211_iftype opmode)
1046 {
1047         ah->mask_reg = AR_IMR_TXERR |
1048                 AR_IMR_TXURN |
1049                 AR_IMR_RXERR |
1050                 AR_IMR_RXORN |
1051                 AR_IMR_BCNMISC;
1052
1053         if (ah->intr_mitigation)
1054                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1055         else
1056                 ah->mask_reg |= AR_IMR_RXOK;
1057
1058         ah->mask_reg |= AR_IMR_TXOK;
1059
1060         if (opmode == NL80211_IFTYPE_AP)
1061                 ah->mask_reg |= AR_IMR_MIB;
1062
1063         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1064         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1065
1066         if (!AR_SREV_9100(ah)) {
1067                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1068                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1069                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1070         }
1071 }
1072
1073 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1074 {
1075         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1076                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1077                 ah->acktimeout = (u32) -1;
1078                 return false;
1079         } else {
1080                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1081                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1082                 ah->acktimeout = us;
1083                 return true;
1084         }
1085 }
1086
1087 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1088 {
1089         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1090                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1091                 ah->ctstimeout = (u32) -1;
1092                 return false;
1093         } else {
1094                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1095                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1096                 ah->ctstimeout = us;
1097                 return true;
1098         }
1099 }
1100
1101 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1102 {
1103         if (tu > 0xFFFF) {
1104                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1105                         "bad global tx timeout %u\n", tu);
1106                 ah->globaltxtimeout = (u32) -1;
1107                 return false;
1108         } else {
1109                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1110                 ah->globaltxtimeout = tu;
1111                 return true;
1112         }
1113 }
1114
1115 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1116 {
1117         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1118                 ah->misc_mode);
1119
1120         if (ah->misc_mode != 0)
1121                 REG_WRITE(ah, AR_PCU_MISC,
1122                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1123         if (ah->slottime != (u32) -1)
1124                 ath9k_hw_setslottime(ah, ah->slottime);
1125         if (ah->acktimeout != (u32) -1)
1126                 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1127         if (ah->ctstimeout != (u32) -1)
1128                 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1129         if (ah->globaltxtimeout != (u32) -1)
1130                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1131 }
1132
1133 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1134 {
1135         return vendorid == ATHEROS_VENDOR_ID ?
1136                 ath9k_hw_devname(devid) : NULL;
1137 }
1138
1139 void ath9k_hw_detach(struct ath_hw *ah)
1140 {
1141         if (!AR_SREV_9100(ah))
1142                 ath9k_hw_ani_detach(ah);
1143
1144         ath9k_hw_rfdetach(ah);
1145         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1146         kfree(ah);
1147 }
1148
1149 struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1150 {
1151         struct ath_hw *ah = NULL;
1152
1153         switch (devid) {
1154         case AR5416_DEVID_PCI:
1155         case AR5416_DEVID_PCIE:
1156         case AR5416_AR9100_DEVID:
1157         case AR9160_DEVID_PCI:
1158         case AR9280_DEVID_PCI:
1159         case AR9280_DEVID_PCIE:
1160         case AR9285_DEVID_PCIE:
1161                 ah = ath9k_hw_do_attach(devid, sc, error);
1162                 break;
1163         default:
1164                 *error = -ENXIO;
1165                 break;
1166         }
1167
1168         return ah;
1169 }
1170
1171 /*******/
1172 /* INI */
1173 /*******/
1174
1175 static void ath9k_hw_override_ini(struct ath_hw *ah,
1176                                   struct ath9k_channel *chan)
1177 {
1178         /*
1179          * Set the RX_ABORT and RX_DIS and clear if off only after
1180          * RXE is set for MAC. This prevents frames with corrupted
1181          * descriptor status.
1182          */
1183         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1184
1185
1186         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1187             AR_SREV_9280_10_OR_LATER(ah))
1188                 return;
1189
1190         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1191 }
1192
1193 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1194                               struct ar5416_eeprom_def *pEepData,
1195                               u32 reg, u32 value)
1196 {
1197         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1198
1199         switch (ah->hw_version.devid) {
1200         case AR9280_DEVID_PCI:
1201                 if (reg == 0x7894) {
1202                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1203                                 "ini VAL: %x  EEPROM: %x\n", value,
1204                                 (pBase->version & 0xff));
1205
1206                         if ((pBase->version & 0xff) > 0x0a) {
1207                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1208                                         "PWDCLKIND: %d\n",
1209                                         pBase->pwdclkind);
1210                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1211                                 value |= AR_AN_TOP2_PWDCLKIND &
1212                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1213                         } else {
1214                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1215                                         "PWDCLKIND Earlier Rev\n");
1216                         }
1217
1218                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1219                                 "final ini VAL: %x\n", value);
1220                 }
1221                 break;
1222         }
1223
1224         return value;
1225 }
1226
1227 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1228                               struct ar5416_eeprom_def *pEepData,
1229                               u32 reg, u32 value)
1230 {
1231         if (ah->eep_map == EEP_MAP_4KBITS)
1232                 return value;
1233         else
1234                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1235 }
1236
1237 static void ath9k_olc_init(struct ath_hw *ah)
1238 {
1239         u32 i;
1240
1241         for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1242                 ah->originalGain[i] =
1243                         MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1244                                         AR_PHY_TX_GAIN);
1245         ah->PDADCdelta = 0;
1246 }
1247
1248 static int ath9k_hw_process_ini(struct ath_hw *ah,
1249                                 struct ath9k_channel *chan,
1250                                 enum ath9k_ht_macmode macmode)
1251 {
1252         int i, regWrites = 0;
1253         struct ieee80211_channel *channel = chan->chan;
1254         u32 modesIndex, freqIndex;
1255         int status;
1256
1257         switch (chan->chanmode) {
1258         case CHANNEL_A:
1259         case CHANNEL_A_HT20:
1260                 modesIndex = 1;
1261                 freqIndex = 1;
1262                 break;
1263         case CHANNEL_A_HT40PLUS:
1264         case CHANNEL_A_HT40MINUS:
1265                 modesIndex = 2;
1266                 freqIndex = 1;
1267                 break;
1268         case CHANNEL_G:
1269         case CHANNEL_G_HT20:
1270         case CHANNEL_B:
1271                 modesIndex = 4;
1272                 freqIndex = 2;
1273                 break;
1274         case CHANNEL_G_HT40PLUS:
1275         case CHANNEL_G_HT40MINUS:
1276                 modesIndex = 3;
1277                 freqIndex = 2;
1278                 break;
1279
1280         default:
1281                 return -EINVAL;
1282         }
1283
1284         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1285         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1286         ah->eep_ops->set_addac(ah, chan);
1287
1288         if (AR_SREV_5416_22_OR_LATER(ah)) {
1289                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1290         } else {
1291                 struct ar5416IniArray temp;
1292                 u32 addacSize =
1293                         sizeof(u32) * ah->iniAddac.ia_rows *
1294                         ah->iniAddac.ia_columns;
1295
1296                 memcpy(ah->addac5416_21,
1297                        ah->iniAddac.ia_array, addacSize);
1298
1299                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1300
1301                 temp.ia_array = ah->addac5416_21;
1302                 temp.ia_columns = ah->iniAddac.ia_columns;
1303                 temp.ia_rows = ah->iniAddac.ia_rows;
1304                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1305         }
1306
1307         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1308
1309         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1310                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1311                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1312
1313                 REG_WRITE(ah, reg, val);
1314
1315                 if (reg >= 0x7800 && reg < 0x78a0
1316                     && ah->config.analog_shiftreg) {
1317                         udelay(100);
1318                 }
1319
1320                 DO_DELAY(regWrites);
1321         }
1322
1323         if (AR_SREV_9280(ah))
1324                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1325
1326         if (AR_SREV_9280(ah) || (AR_SREV_9285(ah) &&
1327             AR_SREV_9285_12_OR_LATER(ah)))
1328                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1329
1330         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1331                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1332                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1333
1334                 REG_WRITE(ah, reg, val);
1335
1336                 if (reg >= 0x7800 && reg < 0x78a0
1337                     && ah->config.analog_shiftreg) {
1338                         udelay(100);
1339                 }
1340
1341                 DO_DELAY(regWrites);
1342         }
1343
1344         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1345
1346         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1347                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1348                                 regWrites);
1349         }
1350
1351         ath9k_hw_override_ini(ah, chan);
1352         ath9k_hw_set_regs(ah, chan, macmode);
1353         ath9k_hw_init_chain_masks(ah);
1354
1355         if (OLC_FOR_AR9280_20_LATER)
1356                 ath9k_olc_init(ah);
1357
1358         status = ah->eep_ops->set_txpower(ah, chan,
1359                                   ath9k_regd_get_ctl(ah, chan),
1360                                   channel->max_antenna_gain * 2,
1361                                   channel->max_power * 2,
1362                                   min((u32) MAX_RATE_POWER,
1363                                       (u32) ah->regulatory.power_limit));
1364         if (status != 0) {
1365                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1366                         "error init'ing transmit power\n");
1367                 return -EIO;
1368         }
1369
1370         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1371                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1372                         "ar5416SetRfRegs failed\n");
1373                 return -EIO;
1374         }
1375
1376         return 0;
1377 }
1378
1379 /****************************************/
1380 /* Reset and Channel Switching Routines */
1381 /****************************************/
1382
1383 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1384 {
1385         u32 rfMode = 0;
1386
1387         if (chan == NULL)
1388                 return;
1389
1390         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1391                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1392
1393         if (!AR_SREV_9280_10_OR_LATER(ah))
1394                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1395                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1396
1397         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1398                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1399
1400         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1401 }
1402
1403 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1404 {
1405         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1406 }
1407
1408 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1409 {
1410         u32 regval;
1411
1412         regval = REG_READ(ah, AR_AHB_MODE);
1413         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1414
1415         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1416         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1417
1418         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1419
1420         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1421         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1422
1423         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1424
1425         if (AR_SREV_9285(ah)) {
1426                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1427                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1428         } else {
1429                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1430                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1431         }
1432 }
1433
1434 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1435 {
1436         u32 val;
1437
1438         val = REG_READ(ah, AR_STA_ID1);
1439         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1440         switch (opmode) {
1441         case NL80211_IFTYPE_AP:
1442                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1443                           | AR_STA_ID1_KSRCH_MODE);
1444                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1445                 break;
1446         case NL80211_IFTYPE_ADHOC:
1447                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1448                           | AR_STA_ID1_KSRCH_MODE);
1449                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1450                 break;
1451         case NL80211_IFTYPE_STATION:
1452         case NL80211_IFTYPE_MONITOR:
1453                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1454                 break;
1455         }
1456 }
1457
1458 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1459                                                  u32 coef_scaled,
1460                                                  u32 *coef_mantissa,
1461                                                  u32 *coef_exponent)
1462 {
1463         u32 coef_exp, coef_man;
1464
1465         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1466                 if ((coef_scaled >> coef_exp) & 0x1)
1467                         break;
1468
1469         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1470
1471         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1472
1473         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1474         *coef_exponent = coef_exp - 16;
1475 }
1476
1477 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1478                                      struct ath9k_channel *chan)
1479 {
1480         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1481         u32 clockMhzScaled = 0x64000000;
1482         struct chan_centers centers;
1483
1484         if (IS_CHAN_HALF_RATE(chan))
1485                 clockMhzScaled = clockMhzScaled >> 1;
1486         else if (IS_CHAN_QUARTER_RATE(chan))
1487                 clockMhzScaled = clockMhzScaled >> 2;
1488
1489         ath9k_hw_get_channel_centers(ah, chan, &centers);
1490         coef_scaled = clockMhzScaled / centers.synth_center;
1491
1492         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1493                                       &ds_coef_exp);
1494
1495         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1496                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1497         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1498                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1499
1500         coef_scaled = (9 * coef_scaled) / 10;
1501
1502         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1503                                       &ds_coef_exp);
1504
1505         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1506                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1507         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1508                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1509 }
1510
1511 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1512 {
1513         u32 rst_flags;
1514         u32 tmpReg;
1515
1516         if (AR_SREV_9100(ah)) {
1517                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1518                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1519                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1520                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1521                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1522         }
1523
1524         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1525                   AR_RTC_FORCE_WAKE_ON_INT);
1526
1527         if (AR_SREV_9100(ah)) {
1528                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1529                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1530         } else {
1531                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1532                 if (tmpReg &
1533                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1534                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1535                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1536                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1537                 } else {
1538                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1539                 }
1540
1541                 rst_flags = AR_RTC_RC_MAC_WARM;
1542                 if (type == ATH9K_RESET_COLD)
1543                         rst_flags |= AR_RTC_RC_MAC_COLD;
1544         }
1545
1546         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1547         udelay(50);
1548
1549         REG_WRITE(ah, AR_RTC_RC, 0);
1550         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1551                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1552                         "RTC stuck in MAC reset\n");
1553                 return false;
1554         }
1555
1556         if (!AR_SREV_9100(ah))
1557                 REG_WRITE(ah, AR_RC, 0);
1558
1559         ath9k_hw_init_pll(ah, NULL);
1560
1561         if (AR_SREV_9100(ah))
1562                 udelay(50);
1563
1564         return true;
1565 }
1566
1567 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1568 {
1569         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1570                   AR_RTC_FORCE_WAKE_ON_INT);
1571
1572         REG_WRITE(ah, AR_RTC_RESET, 0);
1573         udelay(2);
1574         REG_WRITE(ah, AR_RTC_RESET, 1);
1575
1576         if (!ath9k_hw_wait(ah,
1577                            AR_RTC_STATUS,
1578                            AR_RTC_STATUS_M,
1579                            AR_RTC_STATUS_ON,
1580                            AH_WAIT_TIMEOUT)) {
1581                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1582                 return false;
1583         }
1584
1585         ath9k_hw_read_revisions(ah);
1586
1587         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1588 }
1589
1590 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1591 {
1592         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1593                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1594
1595         switch (type) {
1596         case ATH9K_RESET_POWER_ON:
1597                 return ath9k_hw_set_reset_power_on(ah);
1598                 break;
1599         case ATH9K_RESET_WARM:
1600         case ATH9K_RESET_COLD:
1601                 return ath9k_hw_set_reset(ah, type);
1602                 break;
1603         default:
1604                 return false;
1605         }
1606 }
1607
1608 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1609                               enum ath9k_ht_macmode macmode)
1610 {
1611         u32 phymode;
1612         u32 enableDacFifo = 0;
1613
1614         if (AR_SREV_9285_10_OR_LATER(ah))
1615                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1616                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1617
1618         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1619                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1620
1621         if (IS_CHAN_HT40(chan)) {
1622                 phymode |= AR_PHY_FC_DYN2040_EN;
1623
1624                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1625                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1626                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1627
1628                 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1629                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1630         }
1631         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1632
1633         ath9k_hw_set11nmac2040(ah, macmode);
1634
1635         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1636         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1637 }
1638
1639 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1640                                 struct ath9k_channel *chan)
1641 {
1642         if (OLC_FOR_AR9280_20_LATER) {
1643                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1644                         return false;
1645         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1646                 return false;
1647
1648         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1649                 return false;
1650
1651         ah->chip_fullsleep = false;
1652         ath9k_hw_init_pll(ah, chan);
1653         ath9k_hw_set_rfmode(ah, chan);
1654
1655         return true;
1656 }
1657
1658 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1659                                     struct ath9k_channel *chan,
1660                                     enum ath9k_ht_macmode macmode)
1661 {
1662         struct ieee80211_channel *channel = chan->chan;
1663         u32 synthDelay, qnum;
1664
1665         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1666                 if (ath9k_hw_numtxpending(ah, qnum)) {
1667                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1668                                 "Transmit frames pending on queue %d\n", qnum);
1669                         return false;
1670                 }
1671         }
1672
1673         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1674         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1675                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1676                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1677                         "Could not kill baseband RX\n");
1678                 return false;
1679         }
1680
1681         ath9k_hw_set_regs(ah, chan, macmode);
1682
1683         if (AR_SREV_9280_10_OR_LATER(ah)) {
1684                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1685                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1686                                 "failed to set channel\n");
1687                         return false;
1688                 }
1689         } else {
1690                 if (!(ath9k_hw_set_channel(ah, chan))) {
1691                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1692                                 "failed to set channel\n");
1693                         return false;
1694                 }
1695         }
1696
1697         if (ah->eep_ops->set_txpower(ah, chan,
1698                              ath9k_regd_get_ctl(ah, chan),
1699                              channel->max_antenna_gain * 2,
1700                              channel->max_power * 2,
1701                              min((u32) MAX_RATE_POWER,
1702                                  (u32) ah->regulatory.power_limit)) != 0) {
1703                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1704                         "error init'ing transmit power\n");
1705                 return false;
1706         }
1707
1708         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1709         if (IS_CHAN_B(chan))
1710                 synthDelay = (4 * synthDelay) / 22;
1711         else
1712                 synthDelay /= 10;
1713
1714         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1715
1716         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1717
1718         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1719                 ath9k_hw_set_delta_slope(ah, chan);
1720
1721         if (AR_SREV_9280_10_OR_LATER(ah))
1722                 ath9k_hw_9280_spur_mitigate(ah, chan);
1723         else
1724                 ath9k_hw_spur_mitigate(ah, chan);
1725
1726         if (!chan->oneTimeCalsDone)
1727                 chan->oneTimeCalsDone = true;
1728
1729         return true;
1730 }
1731
1732 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1733 {
1734         int bb_spur = AR_NO_SPUR;
1735         int freq;
1736         int bin, cur_bin;
1737         int bb_spur_off, spur_subchannel_sd;
1738         int spur_freq_sd;
1739         int spur_delta_phase;
1740         int denominator;
1741         int upper, lower, cur_vit_mask;
1742         int tmp, newVal;
1743         int i;
1744         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1745                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1746         };
1747         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1748                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1749         };
1750         int inc[4] = { 0, 100, 0, 0 };
1751         struct chan_centers centers;
1752
1753         int8_t mask_m[123];
1754         int8_t mask_p[123];
1755         int8_t mask_amt;
1756         int tmp_mask;
1757         int cur_bb_spur;
1758         bool is2GHz = IS_CHAN_2GHZ(chan);
1759
1760         memset(&mask_m, 0, sizeof(int8_t) * 123);
1761         memset(&mask_p, 0, sizeof(int8_t) * 123);
1762
1763         ath9k_hw_get_channel_centers(ah, chan, &centers);
1764         freq = centers.synth_center;
1765
1766         ah->config.spurmode = SPUR_ENABLE_EEPROM;
1767         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1768                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1769
1770                 if (is2GHz)
1771                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1772                 else
1773                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1774
1775                 if (AR_NO_SPUR == cur_bb_spur)
1776                         break;
1777                 cur_bb_spur = cur_bb_spur - freq;
1778
1779                 if (IS_CHAN_HT40(chan)) {
1780                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1781                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1782                                 bb_spur = cur_bb_spur;
1783                                 break;
1784                         }
1785                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1786                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1787                         bb_spur = cur_bb_spur;
1788                         break;
1789                 }
1790         }
1791
1792         if (AR_NO_SPUR == bb_spur) {
1793                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1794                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1795                 return;
1796         } else {
1797                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1798                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1799         }
1800
1801         bin = bb_spur * 320;
1802
1803         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1804
1805         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1806                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1807                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1808                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1809         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1810
1811         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1812                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1813                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1814                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1815                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1816         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1817
1818         if (IS_CHAN_HT40(chan)) {
1819                 if (bb_spur < 0) {
1820                         spur_subchannel_sd = 1;
1821                         bb_spur_off = bb_spur + 10;
1822                 } else {
1823                         spur_subchannel_sd = 0;
1824                         bb_spur_off = bb_spur - 10;
1825                 }
1826         } else {
1827                 spur_subchannel_sd = 0;
1828                 bb_spur_off = bb_spur;
1829         }
1830
1831         if (IS_CHAN_HT40(chan))
1832                 spur_delta_phase =
1833                         ((bb_spur * 262144) /
1834                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1835         else
1836                 spur_delta_phase =
1837                         ((bb_spur * 524288) /
1838                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1839
1840         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1841         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1842
1843         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1844                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1845                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1846         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1847
1848         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1849         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1850
1851         cur_bin = -6000;
1852         upper = bin + 100;
1853         lower = bin - 100;
1854
1855         for (i = 0; i < 4; i++) {
1856                 int pilot_mask = 0;
1857                 int chan_mask = 0;
1858                 int bp = 0;
1859                 for (bp = 0; bp < 30; bp++) {
1860                         if ((cur_bin > lower) && (cur_bin < upper)) {
1861                                 pilot_mask = pilot_mask | 0x1 << bp;
1862                                 chan_mask = chan_mask | 0x1 << bp;
1863                         }
1864                         cur_bin += 100;
1865                 }
1866                 cur_bin += inc[i];
1867                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1868                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1869         }
1870
1871         cur_vit_mask = 6100;
1872         upper = bin + 120;
1873         lower = bin - 120;
1874
1875         for (i = 0; i < 123; i++) {
1876                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1877
1878                         /* workaround for gcc bug #37014 */
1879                         volatile int tmp_v = abs(cur_vit_mask - bin);
1880
1881                         if (tmp_v < 75)
1882                                 mask_amt = 1;
1883                         else
1884                                 mask_amt = 0;
1885                         if (cur_vit_mask < 0)
1886                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1887                         else
1888                                 mask_p[cur_vit_mask / 100] = mask_amt;
1889                 }
1890                 cur_vit_mask -= 100;
1891         }
1892
1893         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1894                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1895                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1896                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1897                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1898                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1899                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1900                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1901         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1902         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1903
1904         tmp_mask = (mask_m[31] << 28)
1905                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1906                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1907                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1908                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1909                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1910                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1911                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1912         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1913         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1914
1915         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1916                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1917                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1918                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1919                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1920                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1921                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1922                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1923         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1924         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1925
1926         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1927                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1928                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1929                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1930                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1931                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1932                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1933                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1934         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1935         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1936
1937         tmp_mask = (mask_p[15] << 28)
1938                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1939                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1940                 | (mask_p[10] << 18) | (mask_p[9] << 16)
1941                 | (mask_p[8] << 14) | (mask_p[7] << 12)
1942                 | (mask_p[6] << 10) | (mask_p[5] << 8)
1943                 | (mask_p[4] << 6) | (mask_p[3] << 4)
1944                 | (mask_p[2] << 2) | (mask_p[1] << 0);
1945         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1946         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1947
1948         tmp_mask = (mask_p[30] << 28)
1949                 | (mask_p[29] << 26) | (mask_p[28] << 24)
1950                 | (mask_p[27] << 22) | (mask_p[26] << 20)
1951                 | (mask_p[25] << 18) | (mask_p[24] << 16)
1952                 | (mask_p[23] << 14) | (mask_p[22] << 12)
1953                 | (mask_p[21] << 10) | (mask_p[20] << 8)
1954                 | (mask_p[19] << 6) | (mask_p[18] << 4)
1955                 | (mask_p[17] << 2) | (mask_p[16] << 0);
1956         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1957         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1958
1959         tmp_mask = (mask_p[45] << 28)
1960                 | (mask_p[44] << 26) | (mask_p[43] << 24)
1961                 | (mask_p[42] << 22) | (mask_p[41] << 20)
1962                 | (mask_p[40] << 18) | (mask_p[39] << 16)
1963                 | (mask_p[38] << 14) | (mask_p[37] << 12)
1964                 | (mask_p[36] << 10) | (mask_p[35] << 8)
1965                 | (mask_p[34] << 6) | (mask_p[33] << 4)
1966                 | (mask_p[32] << 2) | (mask_p[31] << 0);
1967         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1968         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1969
1970         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1971                 | (mask_p[59] << 26) | (mask_p[58] << 24)
1972                 | (mask_p[57] << 22) | (mask_p[56] << 20)
1973                 | (mask_p[55] << 18) | (mask_p[54] << 16)
1974                 | (mask_p[53] << 14) | (mask_p[52] << 12)
1975                 | (mask_p[51] << 10) | (mask_p[50] << 8)
1976                 | (mask_p[49] << 6) | (mask_p[48] << 4)
1977                 | (mask_p[47] << 2) | (mask_p[46] << 0);
1978         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1979         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1980 }
1981
1982 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1983 {
1984         int bb_spur = AR_NO_SPUR;
1985         int bin, cur_bin;
1986         int spur_freq_sd;
1987         int spur_delta_phase;
1988         int denominator;
1989         int upper, lower, cur_vit_mask;
1990         int tmp, new;
1991         int i;
1992         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1993                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1994         };
1995         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1996                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1997         };
1998         int inc[4] = { 0, 100, 0, 0 };
1999
2000         int8_t mask_m[123];
2001         int8_t mask_p[123];
2002         int8_t mask_amt;
2003         int tmp_mask;
2004         int cur_bb_spur;
2005         bool is2GHz = IS_CHAN_2GHZ(chan);
2006
2007         memset(&mask_m, 0, sizeof(int8_t) * 123);
2008         memset(&mask_p, 0, sizeof(int8_t) * 123);
2009
2010         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2011                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2012                 if (AR_NO_SPUR == cur_bb_spur)
2013                         break;
2014                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2015                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2016                         bb_spur = cur_bb_spur;
2017                         break;
2018                 }
2019         }
2020
2021         if (AR_NO_SPUR == bb_spur)
2022                 return;
2023
2024         bin = bb_spur * 32;
2025
2026         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2027         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2028                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2029                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2030                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2031
2032         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2033
2034         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2035                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2036                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2037                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2038                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2039         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2040
2041         spur_delta_phase = ((bb_spur * 524288) / 100) &
2042                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2043
2044         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2045         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2046
2047         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2048                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2049                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2050         REG_WRITE(ah, AR_PHY_TIMING11, new);
2051
2052         cur_bin = -6000;
2053         upper = bin + 100;
2054         lower = bin - 100;
2055
2056         for (i = 0; i < 4; i++) {
2057                 int pilot_mask = 0;
2058                 int chan_mask = 0;
2059                 int bp = 0;
2060                 for (bp = 0; bp < 30; bp++) {
2061                         if ((cur_bin > lower) && (cur_bin < upper)) {
2062                                 pilot_mask = pilot_mask | 0x1 << bp;
2063                                 chan_mask = chan_mask | 0x1 << bp;
2064                         }
2065                         cur_bin += 100;
2066                 }
2067                 cur_bin += inc[i];
2068                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2069                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2070         }
2071
2072         cur_vit_mask = 6100;
2073         upper = bin + 120;
2074         lower = bin - 120;
2075
2076         for (i = 0; i < 123; i++) {
2077                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2078
2079                         /* workaround for gcc bug #37014 */
2080                         volatile int tmp_v = abs(cur_vit_mask - bin);
2081
2082                         if (tmp_v < 75)
2083                                 mask_amt = 1;
2084                         else
2085                                 mask_amt = 0;
2086                         if (cur_vit_mask < 0)
2087                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2088                         else
2089                                 mask_p[cur_vit_mask / 100] = mask_amt;
2090                 }
2091                 cur_vit_mask -= 100;
2092         }
2093
2094         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2095                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2096                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2097                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2098                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2099                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2100                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2101                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2102         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2103         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2104
2105         tmp_mask = (mask_m[31] << 28)
2106                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2107                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2108                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2109                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2110                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2111                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2112                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2113         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2114         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2115
2116         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2117                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2118                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2119                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2120                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2121                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2122                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2123                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2124         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2125         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2126
2127         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2128                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2129                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2130                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2131                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2132                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2133                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2134                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2135         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2136         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2137
2138         tmp_mask = (mask_p[15] << 28)
2139                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2140                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2141                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2142                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2143                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2144                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2145                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2146         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2147         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2148
2149         tmp_mask = (mask_p[30] << 28)
2150                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2151                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2152                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2153                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2154                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2155                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2156                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2157         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2158         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2159
2160         tmp_mask = (mask_p[45] << 28)
2161                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2162                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2163                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2164                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2165                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2166                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2167                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2168         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2169         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2170
2171         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2172                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2173                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2174                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2175                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2176                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2177                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2178                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2179         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2180         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2181 }
2182
2183 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2184                     bool bChannelChange)
2185 {
2186         u32 saveLedState;
2187         struct ath_softc *sc = ah->ah_sc;
2188         struct ath9k_channel *curchan = ah->curchan;
2189         u32 saveDefAntenna;
2190         u32 macStaId1;
2191         int i, rx_chainmask, r;
2192
2193         ah->extprotspacing = sc->ht_extprotspacing;
2194         ah->txchainmask = sc->tx_chainmask;
2195         ah->rxchainmask = sc->rx_chainmask;
2196
2197         if (AR_SREV_9285(ah)) {
2198                 ah->txchainmask &= 0x1;
2199                 ah->rxchainmask &= 0x1;
2200         } else if (AR_SREV_9280(ah)) {
2201                 ah->txchainmask &= 0x3;
2202                 ah->rxchainmask &= 0x3;
2203         }
2204
2205         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2206                 return -EIO;
2207
2208         if (curchan)
2209                 ath9k_hw_getnf(ah, curchan);
2210
2211         if (bChannelChange &&
2212             (ah->chip_fullsleep != true) &&
2213             (ah->curchan != NULL) &&
2214             (chan->channel != ah->curchan->channel) &&
2215             ((chan->channelFlags & CHANNEL_ALL) ==
2216              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2217             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2218                                    !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2219
2220                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2221                         ath9k_hw_loadnf(ah, ah->curchan);
2222                         ath9k_hw_start_nfcal(ah);
2223                         return 0;
2224                 }
2225         }
2226
2227         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2228         if (saveDefAntenna == 0)
2229                 saveDefAntenna = 1;
2230
2231         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2232
2233         saveLedState = REG_READ(ah, AR_CFG_LED) &
2234                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2235                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2236
2237         ath9k_hw_mark_phy_inactive(ah);
2238
2239         if (!ath9k_hw_chip_reset(ah, chan)) {
2240                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2241                 return -EINVAL;
2242         }
2243
2244         if (AR_SREV_9280_10_OR_LATER(ah))
2245                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2246
2247         r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2248         if (r)
2249                 return r;
2250
2251         /* Setup MFP options for CCMP */
2252         if (AR_SREV_9280_20_OR_LATER(ah)) {
2253                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2254                  * frames when constructing CCMP AAD. */
2255                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2256                               0xc7ff);
2257                 ah->sw_mgmt_crypto = false;
2258         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2259                 /* Disable hardware crypto for management frames */
2260                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2261                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2262                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2263                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2264                 ah->sw_mgmt_crypto = true;
2265         } else
2266                 ah->sw_mgmt_crypto = true;
2267
2268         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2269                 ath9k_hw_set_delta_slope(ah, chan);
2270
2271         if (AR_SREV_9280_10_OR_LATER(ah))
2272                 ath9k_hw_9280_spur_mitigate(ah, chan);
2273         else
2274                 ath9k_hw_spur_mitigate(ah, chan);
2275
2276         if (!ah->eep_ops->set_board_values(ah, chan)) {
2277                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2278                         "error setting board options\n");
2279                 return -EIO;
2280         }
2281
2282         ath9k_hw_decrease_chain_power(ah, chan);
2283
2284         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2285         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2286                   | macStaId1
2287                   | AR_STA_ID1_RTS_USE_DEF
2288                   | (ah->config.
2289                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2290                   | ah->sta_id1_defaults);
2291         ath9k_hw_set_operating_mode(ah, ah->opmode);
2292
2293         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2294         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2295
2296         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2297
2298         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2299         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2300                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2301
2302         REG_WRITE(ah, AR_ISR, ~0);
2303
2304         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2305
2306         if (AR_SREV_9280_10_OR_LATER(ah)) {
2307                 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2308                         return -EIO;
2309         } else {
2310                 if (!(ath9k_hw_set_channel(ah, chan)))
2311                         return -EIO;
2312         }
2313
2314         for (i = 0; i < AR_NUM_DCU; i++)
2315                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2316
2317         ah->intr_txqs = 0;
2318         for (i = 0; i < ah->caps.total_queues; i++)
2319                 ath9k_hw_resettxqueue(ah, i);
2320
2321         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2322         ath9k_hw_init_qos(ah);
2323
2324 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2325         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2326                 ath9k_enable_rfkill(ah);
2327 #endif
2328         ath9k_hw_init_user_settings(ah);
2329
2330         REG_WRITE(ah, AR_STA_ID1,
2331                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2332
2333         ath9k_hw_set_dma(ah);
2334
2335         REG_WRITE(ah, AR_OBS, 8);
2336
2337         if (ah->intr_mitigation) {
2338
2339                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2340                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2341         }
2342
2343         ath9k_hw_init_bb(ah, chan);
2344
2345         if (!ath9k_hw_init_cal(ah, chan))
2346                 return -EIO;;
2347
2348         rx_chainmask = ah->rxchainmask;
2349         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2350                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2351                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2352         }
2353
2354         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2355
2356         if (AR_SREV_9100(ah)) {
2357                 u32 mask;
2358                 mask = REG_READ(ah, AR_CFG);
2359                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2360                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2361                                 "CFG Byte Swap Set 0x%x\n", mask);
2362                 } else {
2363                         mask =
2364                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2365                         REG_WRITE(ah, AR_CFG, mask);
2366                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2367                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2368                 }
2369         } else {
2370 #ifdef __BIG_ENDIAN
2371                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2372 #endif
2373         }
2374
2375         return 0;
2376 }
2377
2378 /************************/
2379 /* Key Cache Management */
2380 /************************/
2381
2382 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2383 {
2384         u32 keyType;
2385
2386         if (entry >= ah->caps.keycache_size) {
2387                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2388                         "entry %u out of range\n", entry);
2389                 return false;
2390         }
2391
2392         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2393
2394         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2395         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2396         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2397         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2398         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2399         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2400         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2401         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2402
2403         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2404                 u16 micentry = entry + 64;
2405
2406                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2407                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2408                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2409                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2410
2411         }
2412
2413         if (ah->curchan == NULL)
2414                 return true;
2415
2416         return true;
2417 }
2418
2419 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2420 {
2421         u32 macHi, macLo;
2422
2423         if (entry >= ah->caps.keycache_size) {
2424                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2425                         "entry %u out of range\n", entry);
2426                 return false;
2427         }
2428
2429         if (mac != NULL) {
2430                 macHi = (mac[5] << 8) | mac[4];
2431                 macLo = (mac[3] << 24) |
2432                         (mac[2] << 16) |
2433                         (mac[1] << 8) |
2434                         mac[0];
2435                 macLo >>= 1;
2436                 macLo |= (macHi & 1) << 31;
2437                 macHi >>= 1;
2438         } else {
2439                 macLo = macHi = 0;
2440         }
2441         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2442         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2443
2444         return true;
2445 }
2446
2447 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2448                                  const struct ath9k_keyval *k,
2449                                  const u8 *mac)
2450 {
2451         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2452         u32 key0, key1, key2, key3, key4;
2453         u32 keyType;
2454
2455         if (entry >= pCap->keycache_size) {
2456                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2457                         "entry %u out of range\n", entry);
2458                 return false;
2459         }
2460
2461         switch (k->kv_type) {
2462         case ATH9K_CIPHER_AES_OCB:
2463                 keyType = AR_KEYTABLE_TYPE_AES;
2464                 break;
2465         case ATH9K_CIPHER_AES_CCM:
2466                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2467                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2468                                 "AES-CCM not supported by mac rev 0x%x\n",
2469                                 ah->hw_version.macRev);
2470                         return false;
2471                 }
2472                 keyType = AR_KEYTABLE_TYPE_CCM;
2473                 break;
2474         case ATH9K_CIPHER_TKIP:
2475                 keyType = AR_KEYTABLE_TYPE_TKIP;
2476                 if (ATH9K_IS_MIC_ENABLED(ah)
2477                     && entry + 64 >= pCap->keycache_size) {
2478                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2479                                 "entry %u inappropriate for TKIP\n", entry);
2480                         return false;
2481                 }
2482                 break;
2483         case ATH9K_CIPHER_WEP:
2484                 if (k->kv_len < LEN_WEP40) {
2485                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2486                                 "WEP key length %u too small\n", k->kv_len);
2487                         return false;
2488                 }
2489                 if (k->kv_len <= LEN_WEP40)
2490                         keyType = AR_KEYTABLE_TYPE_40;
2491                 else if (k->kv_len <= LEN_WEP104)
2492                         keyType = AR_KEYTABLE_TYPE_104;
2493                 else
2494                         keyType = AR_KEYTABLE_TYPE_128;
2495                 break;
2496         case ATH9K_CIPHER_CLR:
2497                 keyType = AR_KEYTABLE_TYPE_CLR;
2498                 break;
2499         default:
2500                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2501                         "cipher %u not supported\n", k->kv_type);
2502                 return false;
2503         }
2504
2505         key0 = get_unaligned_le32(k->kv_val + 0);
2506         key1 = get_unaligned_le16(k->kv_val + 4);
2507         key2 = get_unaligned_le32(k->kv_val + 6);
2508         key3 = get_unaligned_le16(k->kv_val + 10);
2509         key4 = get_unaligned_le32(k->kv_val + 12);
2510         if (k->kv_len <= LEN_WEP104)
2511                 key4 &= 0xff;
2512
2513         /*
2514          * Note: Key cache registers access special memory area that requires
2515          * two 32-bit writes to actually update the values in the internal
2516          * memory. Consequently, the exact order and pairs used here must be
2517          * maintained.
2518          */
2519
2520         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2521                 u16 micentry = entry + 64;
2522
2523                 /*
2524                  * Write inverted key[47:0] first to avoid Michael MIC errors
2525                  * on frames that could be sent or received at the same time.
2526                  * The correct key will be written in the end once everything
2527                  * else is ready.
2528                  */
2529                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2530                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2531
2532                 /* Write key[95:48] */
2533                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2534                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2535
2536                 /* Write key[127:96] and key type */
2537                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2538                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2539
2540                 /* Write MAC address for the entry */
2541                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2542
2543                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2544                         /*
2545                          * TKIP uses two key cache entries:
2546                          * Michael MIC TX/RX keys in the same key cache entry
2547                          * (idx = main index + 64):
2548                          * key0 [31:0] = RX key [31:0]
2549                          * key1 [15:0] = TX key [31:16]
2550                          * key1 [31:16] = reserved
2551                          * key2 [31:0] = RX key [63:32]
2552                          * key3 [15:0] = TX key [15:0]
2553                          * key3 [31:16] = reserved
2554                          * key4 [31:0] = TX key [63:32]
2555                          */
2556                         u32 mic0, mic1, mic2, mic3, mic4;
2557
2558                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2559                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2560                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2561                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2562                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2563
2564                         /* Write RX[31:0] and TX[31:16] */
2565                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2566                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2567
2568                         /* Write RX[63:32] and TX[15:0] */
2569                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2570                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2571
2572                         /* Write TX[63:32] and keyType(reserved) */
2573                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2574                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2575                                   AR_KEYTABLE_TYPE_CLR);
2576
2577                 } else {
2578                         /*
2579                          * TKIP uses four key cache entries (two for group
2580                          * keys):
2581                          * Michael MIC TX/RX keys are in different key cache
2582                          * entries (idx = main index + 64 for TX and
2583                          * main index + 32 + 96 for RX):
2584                          * key0 [31:0] = TX/RX MIC key [31:0]
2585                          * key1 [31:0] = reserved
2586                          * key2 [31:0] = TX/RX MIC key [63:32]
2587                          * key3 [31:0] = reserved
2588                          * key4 [31:0] = reserved
2589                          *
2590                          * Upper layer code will call this function separately
2591                          * for TX and RX keys when these registers offsets are
2592                          * used.
2593                          */
2594                         u32 mic0, mic2;
2595
2596                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2597                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2598
2599                         /* Write MIC key[31:0] */
2600                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2601                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2602
2603                         /* Write MIC key[63:32] */
2604                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2605                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2606
2607                         /* Write TX[63:32] and keyType(reserved) */
2608                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2609                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2610                                   AR_KEYTABLE_TYPE_CLR);
2611                 }
2612
2613                 /* MAC address registers are reserved for the MIC entry */
2614                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2615                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2616
2617                 /*
2618                  * Write the correct (un-inverted) key[47:0] last to enable
2619                  * TKIP now that all other registers are set with correct
2620                  * values.
2621                  */
2622                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2623                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2624         } else {
2625                 /* Write key[47:0] */
2626                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2627                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2628
2629                 /* Write key[95:48] */
2630                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2631                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2632
2633                 /* Write key[127:96] and key type */
2634                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2635                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2636
2637                 /* Write MAC address for the entry */
2638                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2639         }
2640
2641         return true;
2642 }
2643
2644 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2645 {
2646         if (entry < ah->caps.keycache_size) {
2647                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2648                 if (val & AR_KEYTABLE_VALID)
2649                         return true;
2650         }
2651         return false;
2652 }
2653
2654 /******************************/
2655 /* Power Management (Chipset) */
2656 /******************************/
2657
2658 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2659 {
2660         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2661         if (setChip) {
2662                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2663                             AR_RTC_FORCE_WAKE_EN);
2664                 if (!AR_SREV_9100(ah))
2665                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2666
2667                 REG_CLR_BIT(ah, (AR_RTC_RESET),
2668                             AR_RTC_RESET_EN);
2669         }
2670 }
2671
2672 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2673 {
2674         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2675         if (setChip) {
2676                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2677
2678                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2679                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2680                                   AR_RTC_FORCE_WAKE_ON_INT);
2681                 } else {
2682                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2683                                     AR_RTC_FORCE_WAKE_EN);
2684                 }
2685         }
2686 }
2687
2688 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2689 {
2690         u32 val;
2691         int i;
2692
2693         if (setChip) {
2694                 if ((REG_READ(ah, AR_RTC_STATUS) &
2695                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2696                         if (ath9k_hw_set_reset_reg(ah,
2697                                            ATH9K_RESET_POWER_ON) != true) {
2698                                 return false;
2699                         }
2700                 }
2701                 if (AR_SREV_9100(ah))
2702                         REG_SET_BIT(ah, AR_RTC_RESET,
2703                                     AR_RTC_RESET_EN);
2704
2705                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2706                             AR_RTC_FORCE_WAKE_EN);
2707                 udelay(50);
2708
2709                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2710                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2711                         if (val == AR_RTC_STATUS_ON)
2712                                 break;
2713                         udelay(50);
2714                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2715                                     AR_RTC_FORCE_WAKE_EN);
2716                 }
2717                 if (i == 0) {
2718                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2719                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2720                         return false;
2721                 }
2722         }
2723
2724         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2725
2726         return true;
2727 }
2728
2729 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2730 {
2731         int status = true, setChip = true;
2732         static const char *modes[] = {
2733                 "AWAKE",
2734                 "FULL-SLEEP",
2735                 "NETWORK SLEEP",
2736                 "UNDEFINED"
2737         };
2738
2739         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2740                 modes[ah->power_mode], modes[mode],
2741                 setChip ? "set chip " : "");
2742
2743         switch (mode) {
2744         case ATH9K_PM_AWAKE:
2745                 status = ath9k_hw_set_power_awake(ah, setChip);
2746                 break;
2747         case ATH9K_PM_FULL_SLEEP:
2748                 ath9k_set_power_sleep(ah, setChip);
2749                 ah->chip_fullsleep = true;
2750                 break;
2751         case ATH9K_PM_NETWORK_SLEEP:
2752                 ath9k_set_power_network_sleep(ah, setChip);
2753                 break;
2754         default:
2755                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2756                         "Unknown power mode %u\n", mode);
2757                 return false;
2758         }
2759         ah->power_mode = mode;
2760
2761         return status;
2762 }
2763
2764 /*
2765  * Helper for ASPM support.
2766  *
2767  * Disable PLL when in L0s as well as receiver clock when in L1.
2768  * This power saving option must be enabled through the SerDes.
2769  *
2770  * Programming the SerDes must go through the same 288 bit serial shift
2771  * register as the other analog registers.  Hence the 9 writes.
2772  */
2773 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2774 {
2775         u8 i;
2776
2777         if (ah->is_pciexpress != true)
2778                 return;
2779
2780         /* Do not touch SerDes registers */
2781         if (ah->config.pcie_powersave_enable == 2)
2782                 return;
2783
2784         /* Nothing to do on restore for 11N */
2785         if (restore)
2786                 return;
2787
2788         if (AR_SREV_9280_20_OR_LATER(ah)) {
2789                 /*
2790                  * AR9280 2.0 or later chips use SerDes values from the
2791                  * initvals.h initialized depending on chipset during
2792                  * ath9k_hw_do_attach()
2793                  */
2794                 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2795                         REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2796                                   INI_RA(&ah->iniPcieSerdes, i, 1));
2797                 }
2798         } else if (AR_SREV_9280(ah) &&
2799                    (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2800                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2801                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2802
2803                 /* RX shut off when elecidle is asserted */
2804                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2805                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2806                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2807
2808                 /* Shut off CLKREQ active in L1 */
2809                 if (ah->config.pcie_clock_req)
2810                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2811                 else
2812                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2813
2814                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2815                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2816                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2817
2818                 /* Load the new settings */
2819                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2820
2821         } else {
2822                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2823                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2824
2825                 /* RX shut off when elecidle is asserted */
2826                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2827                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2828                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2829
2830                 /*
2831                  * Ignore ah->ah_config.pcie_clock_req setting for
2832                  * pre-AR9280 11n
2833                  */
2834                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2835
2836                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2837                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2838                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2839
2840                 /* Load the new settings */
2841                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2842         }
2843
2844         udelay(1000);
2845
2846         /* set bit 19 to allow forcing of pcie core into L1 state */
2847         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2848
2849         /* Several PCIe massages to ensure proper behaviour */
2850         if (ah->config.pcie_waen) {
2851                 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2852         } else {
2853                 if (AR_SREV_9285(ah))
2854                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2855                 /*
2856                  * On AR9280 chips bit 22 of 0x4004 needs to be set to
2857                  * otherwise card may disappear.
2858                  */
2859                 else if (AR_SREV_9280(ah))
2860                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2861                 else
2862                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2863         }
2864 }
2865
2866 /**********************/
2867 /* Interrupt Handling */
2868 /**********************/
2869
2870 bool ath9k_hw_intrpend(struct ath_hw *ah)
2871 {
2872         u32 host_isr;
2873
2874         if (AR_SREV_9100(ah))
2875                 return true;
2876
2877         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2878         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2879                 return true;
2880
2881         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2882         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2883             && (host_isr != AR_INTR_SPURIOUS))
2884                 return true;
2885
2886         return false;
2887 }
2888
2889 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2890 {
2891         u32 isr = 0;
2892         u32 mask2 = 0;
2893         struct ath9k_hw_capabilities *pCap = &ah->caps;
2894         u32 sync_cause = 0;
2895         bool fatal_int = false;
2896
2897         if (!AR_SREV_9100(ah)) {
2898                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2899                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2900                             == AR_RTC_STATUS_ON) {
2901                                 isr = REG_READ(ah, AR_ISR);
2902                         }
2903                 }
2904
2905                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2906                         AR_INTR_SYNC_DEFAULT;
2907
2908                 *masked = 0;
2909
2910                 if (!isr && !sync_cause)
2911                         return false;
2912         } else {
2913                 *masked = 0;
2914                 isr = REG_READ(ah, AR_ISR);
2915         }
2916
2917         if (isr) {
2918                 if (isr & AR_ISR_BCNMISC) {
2919                         u32 isr2;
2920                         isr2 = REG_READ(ah, AR_ISR_S2);
2921                         if (isr2 & AR_ISR_S2_TIM)
2922                                 mask2 |= ATH9K_INT_TIM;
2923                         if (isr2 & AR_ISR_S2_DTIM)
2924                                 mask2 |= ATH9K_INT_DTIM;
2925                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2926                                 mask2 |= ATH9K_INT_DTIMSYNC;
2927                         if (isr2 & (AR_ISR_S2_CABEND))
2928                                 mask2 |= ATH9K_INT_CABEND;
2929                         if (isr2 & AR_ISR_S2_GTT)
2930                                 mask2 |= ATH9K_INT_GTT;
2931                         if (isr2 & AR_ISR_S2_CST)
2932                                 mask2 |= ATH9K_INT_CST;
2933                         if (isr2 & AR_ISR_S2_TSFOOR)
2934                                 mask2 |= ATH9K_INT_TSFOOR;
2935                 }
2936
2937                 isr = REG_READ(ah, AR_ISR_RAC);
2938                 if (isr == 0xffffffff) {
2939                         *masked = 0;
2940                         return false;
2941                 }
2942
2943                 *masked = isr & ATH9K_INT_COMMON;
2944
2945                 if (ah->intr_mitigation) {
2946                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2947                                 *masked |= ATH9K_INT_RX;
2948                 }
2949
2950                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2951                         *masked |= ATH9K_INT_RX;
2952                 if (isr &
2953                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2954                      AR_ISR_TXEOL)) {
2955                         u32 s0_s, s1_s;
2956
2957                         *masked |= ATH9K_INT_TX;
2958
2959                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2960                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2961                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2962
2963                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2964                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2965                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2966                 }
2967
2968                 if (isr & AR_ISR_RXORN) {
2969                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2970                                 "receive FIFO overrun interrupt\n");
2971                 }
2972
2973                 if (!AR_SREV_9100(ah)) {
2974                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2975                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2976                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2977                                         *masked |= ATH9K_INT_TIM_TIMER;
2978                         }
2979                 }
2980
2981                 *masked |= mask2;
2982         }
2983
2984         if (AR_SREV_9100(ah))
2985                 return true;
2986
2987         if (sync_cause) {
2988                 fatal_int =
2989                         (sync_cause &
2990                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2991                         ? true : false;
2992
2993                 if (fatal_int) {
2994                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2995                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2996                                         "received PCI FATAL interrupt\n");
2997                         }
2998                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2999                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3000                                         "received PCI PERR interrupt\n");
3001                         }
3002                 }
3003                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3004                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3005                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3006                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3007                         REG_WRITE(ah, AR_RC, 0);
3008                         *masked |= ATH9K_INT_FATAL;
3009                 }
3010                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3011                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3012                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3013                 }
3014
3015                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3016                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3017         }
3018
3019         return true;
3020 }
3021
3022 enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
3023 {
3024         return ah->mask_reg;
3025 }
3026
3027 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3028 {
3029         u32 omask = ah->mask_reg;
3030         u32 mask, mask2;
3031         struct ath9k_hw_capabilities *pCap = &ah->caps;
3032
3033         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3034
3035         if (omask & ATH9K_INT_GLOBAL) {
3036                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3037                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3038                 (void) REG_READ(ah, AR_IER);
3039                 if (!AR_SREV_9100(ah)) {
3040                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3041                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3042
3043                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3044                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3045                 }
3046         }
3047
3048         mask = ints & ATH9K_INT_COMMON;
3049         mask2 = 0;
3050
3051         if (ints & ATH9K_INT_TX) {
3052                 if (ah->txok_interrupt_mask)
3053                         mask |= AR_IMR_TXOK;
3054                 if (ah->txdesc_interrupt_mask)
3055                         mask |= AR_IMR_TXDESC;
3056                 if (ah->txerr_interrupt_mask)
3057                         mask |= AR_IMR_TXERR;
3058                 if (ah->txeol_interrupt_mask)
3059                         mask |= AR_IMR_TXEOL;
3060         }
3061         if (ints & ATH9K_INT_RX) {
3062                 mask |= AR_IMR_RXERR;
3063                 if (ah->intr_mitigation)
3064                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3065                 else
3066                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3067                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3068                         mask |= AR_IMR_GENTMR;
3069         }
3070
3071         if (ints & (ATH9K_INT_BMISC)) {
3072                 mask |= AR_IMR_BCNMISC;
3073                 if (ints & ATH9K_INT_TIM)
3074                         mask2 |= AR_IMR_S2_TIM;
3075                 if (ints & ATH9K_INT_DTIM)
3076                         mask2 |= AR_IMR_S2_DTIM;
3077                 if (ints & ATH9K_INT_DTIMSYNC)
3078                         mask2 |= AR_IMR_S2_DTIMSYNC;
3079                 if (ints & ATH9K_INT_CABEND)
3080                         mask2 |= AR_IMR_S2_CABEND;
3081                 if (ints & ATH9K_INT_TSFOOR)
3082                         mask2 |= AR_IMR_S2_TSFOOR;
3083         }
3084
3085         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3086                 mask |= AR_IMR_BCNMISC;
3087                 if (ints & ATH9K_INT_GTT)
3088                         mask2 |= AR_IMR_S2_GTT;
3089                 if (ints & ATH9K_INT_CST)
3090                         mask2 |= AR_IMR_S2_CST;
3091         }
3092
3093         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3094         REG_WRITE(ah, AR_IMR, mask);
3095         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3096                                            AR_IMR_S2_DTIM |
3097                                            AR_IMR_S2_DTIMSYNC |
3098                                            AR_IMR_S2_CABEND |
3099                                            AR_IMR_S2_CABTO |
3100                                            AR_IMR_S2_TSFOOR |
3101                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3102         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3103         ah->mask_reg = ints;
3104
3105         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3106                 if (ints & ATH9K_INT_TIM_TIMER)
3107                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3108                 else
3109                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3110         }
3111
3112         if (ints & ATH9K_INT_GLOBAL) {
3113                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3114                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3115                 if (!AR_SREV_9100(ah)) {
3116                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3117                                   AR_INTR_MAC_IRQ);
3118                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3119
3120
3121                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3122                                   AR_INTR_SYNC_DEFAULT);
3123                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3124                                   AR_INTR_SYNC_DEFAULT);
3125                 }
3126                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3127                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3128         }
3129
3130         return omask;
3131 }
3132
3133 /*******************/
3134 /* Beacon Handling */
3135 /*******************/
3136
3137 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3138 {
3139         int flags = 0;
3140
3141         ah->beacon_interval = beacon_period;
3142
3143         switch (ah->opmode) {
3144         case NL80211_IFTYPE_STATION:
3145         case NL80211_IFTYPE_MONITOR:
3146                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3147                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3148                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3149                 flags |= AR_TBTT_TIMER_EN;
3150                 break;
3151         case NL80211_IFTYPE_ADHOC:
3152                 REG_SET_BIT(ah, AR_TXCFG,
3153                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3154                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3155                           TU_TO_USEC(next_beacon +
3156                                      (ah->atim_window ? ah->
3157                                       atim_window : 1)));
3158                 flags |= AR_NDP_TIMER_EN;
3159         case NL80211_IFTYPE_AP:
3160                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3161                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3162                           TU_TO_USEC(next_beacon -
3163                                      ah->config.
3164                                      dma_beacon_response_time));
3165                 REG_WRITE(ah, AR_NEXT_SWBA,
3166                           TU_TO_USEC(next_beacon -
3167                                      ah->config.
3168                                      sw_beacon_response_time));
3169                 flags |=
3170                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3171                 break;
3172         default:
3173                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3174                         "%s: unsupported opmode: %d\n",
3175                         __func__, ah->opmode);
3176                 return;
3177                 break;
3178         }
3179
3180         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3181         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3182         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3183         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3184
3185         beacon_period &= ~ATH9K_BEACON_ENA;
3186         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3187                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3188                 ath9k_hw_reset_tsf(ah);
3189         }
3190
3191         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3192 }
3193
3194 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3195                                     const struct ath9k_beacon_state *bs)
3196 {
3197         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3198         struct ath9k_hw_capabilities *pCap = &ah->caps;
3199
3200         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3201
3202         REG_WRITE(ah, AR_BEACON_PERIOD,
3203                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3204         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3205                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3206
3207         REG_RMW_FIELD(ah, AR_RSSI_THR,
3208                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3209
3210         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3211
3212         if (bs->bs_sleepduration > beaconintval)
3213                 beaconintval = bs->bs_sleepduration;
3214
3215         dtimperiod = bs->bs_dtimperiod;
3216         if (bs->bs_sleepduration > dtimperiod)
3217                 dtimperiod = bs->bs_sleepduration;
3218
3219         if (beaconintval == dtimperiod)
3220                 nextTbtt = bs->bs_nextdtim;
3221         else
3222                 nextTbtt = bs->bs_nexttbtt;
3223
3224         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3225         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3226         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3227         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3228
3229         REG_WRITE(ah, AR_NEXT_DTIM,
3230                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3231         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3232
3233         REG_WRITE(ah, AR_SLEEP1,
3234                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3235                   | AR_SLEEP1_ASSUME_DTIM);
3236
3237         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3238                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3239         else
3240                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3241
3242         REG_WRITE(ah, AR_SLEEP2,
3243                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3244
3245         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3246         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3247
3248         REG_SET_BIT(ah, AR_TIMER_MODE,
3249                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3250                     AR_DTIM_TIMER_EN);
3251
3252         /* TSF Out of Range Threshold */
3253         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3254 }
3255
3256 /*******************/
3257 /* HW Capabilities */
3258 /*******************/
3259
3260 bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3261 {
3262         struct ath9k_hw_capabilities *pCap = &ah->caps;
3263         u16 capField = 0, eeval;
3264
3265         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3266         ah->regulatory.current_rd = eeval;
3267
3268         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3269         if (AR_SREV_9285_10_OR_LATER(ah))
3270                 eeval |= AR9285_RDEXT_DEFAULT;
3271         ah->regulatory.current_rd_ext = eeval;
3272
3273         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3274
3275         if (ah->opmode != NL80211_IFTYPE_AP &&
3276             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3277                 if (ah->regulatory.current_rd == 0x64 ||
3278                     ah->regulatory.current_rd == 0x65)
3279                         ah->regulatory.current_rd += 5;
3280                 else if (ah->regulatory.current_rd == 0x41)
3281                         ah->regulatory.current_rd = 0x43;
3282                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3283                         "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3284         }
3285
3286         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3287         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3288
3289         if (eeval & AR5416_OPFLAGS_11A) {
3290                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3291                 if (ah->config.ht_enable) {
3292                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3293                                 set_bit(ATH9K_MODE_11NA_HT20,
3294                                         pCap->wireless_modes);
3295                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3296                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3297                                         pCap->wireless_modes);
3298                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3299                                         pCap->wireless_modes);
3300                         }
3301                 }
3302         }
3303
3304         if (eeval & AR5416_OPFLAGS_11G) {
3305                 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3306                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3307                 if (ah->config.ht_enable) {
3308                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3309                                 set_bit(ATH9K_MODE_11NG_HT20,
3310                                         pCap->wireless_modes);
3311                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3312                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3313                                         pCap->wireless_modes);
3314                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3315                                         pCap->wireless_modes);
3316                         }
3317                 }
3318         }
3319
3320         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3321         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3322             !(eeval & AR5416_OPFLAGS_11A))
3323                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3324         else
3325                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3326
3327         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3328                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3329
3330         pCap->low_2ghz_chan = 2312;
3331         pCap->high_2ghz_chan = 2732;
3332
3333         pCap->low_5ghz_chan = 4920;
3334         pCap->high_5ghz_chan = 6100;
3335
3336         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3337         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3338         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3339
3340         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3341         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3342         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3343
3344         pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3345
3346         if (ah->config.ht_enable)
3347                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3348         else
3349                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3350
3351         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3352         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3353         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3354         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3355
3356         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3357                 pCap->total_queues =
3358                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3359         else
3360                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3361
3362         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3363                 pCap->keycache_size =
3364                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3365         else
3366                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3367
3368         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3369         pCap->num_mr_retries = 4;
3370         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3371
3372         if (AR_SREV_9285_10_OR_LATER(ah))
3373                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3374         else if (AR_SREV_9280_10_OR_LATER(ah))
3375                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3376         else
3377                 pCap->num_gpio_pins = AR_NUM_GPIO;
3378
3379         if (AR_SREV_9280_10_OR_LATER(ah)) {
3380                 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3381                 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3382         } else {
3383                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3384                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3385         }
3386
3387         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3388                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3389                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3390         } else {
3391                 pCap->rts_aggr_limit = (8 * 1024);
3392         }
3393
3394         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3395
3396 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3397         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3398         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3399                 ah->rfkill_gpio =
3400                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3401                 ah->rfkill_polarity =
3402                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3403
3404                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3405         }
3406 #endif
3407
3408         if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3409             (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3410             (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3411             (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3412             (ah->hw_version.macVersion == AR_SREV_VERSION_9280))
3413                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3414         else
3415                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3416
3417         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3418                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3419         else
3420                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3421
3422         if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3423                 pCap->reg_cap =
3424                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3425                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3426                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3427                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3428         } else {
3429                 pCap->reg_cap =
3430                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3431                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3432         }
3433
3434         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3435
3436         pCap->num_antcfg_5ghz =
3437                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3438         pCap->num_antcfg_2ghz =
3439                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3440
3441         if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3442                 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3443                 ah->btactive_gpio = 6;
3444                 ah->wlanactive_gpio = 5;
3445         }
3446
3447         return true;
3448 }
3449
3450 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3451                             u32 capability, u32 *result)
3452 {
3453         switch (type) {
3454         case ATH9K_CAP_CIPHER:
3455                 switch (capability) {
3456                 case ATH9K_CIPHER_AES_CCM:
3457                 case ATH9K_CIPHER_AES_OCB:
3458                 case ATH9K_CIPHER_TKIP:
3459                 case ATH9K_CIPHER_WEP:
3460                 case ATH9K_CIPHER_MIC:
3461                 case ATH9K_CIPHER_CLR:
3462                         return true;
3463                 default:
3464                         return false;
3465                 }
3466         case ATH9K_CAP_TKIP_MIC:
3467                 switch (capability) {
3468                 case 0:
3469                         return true;
3470                 case 1:
3471                         return (ah->sta_id1_defaults &
3472                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3473                         false;
3474                 }
3475         case ATH9K_CAP_TKIP_SPLIT:
3476                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3477                         false : true;
3478         case ATH9K_CAP_DIVERSITY:
3479                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3480                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3481                         true : false;
3482         case ATH9K_CAP_MCAST_KEYSRCH:
3483                 switch (capability) {
3484                 case 0:
3485                         return true;
3486                 case 1:
3487                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3488                                 return false;
3489                         } else {
3490                                 return (ah->sta_id1_defaults &
3491                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3492                                         false;
3493                         }
3494                 }
3495                 return false;
3496         case ATH9K_CAP_TXPOW:
3497                 switch (capability) {
3498                 case 0:
3499                         return 0;
3500                 case 1:
3501                         *result = ah->regulatory.power_limit;
3502                         return 0;
3503                 case 2:
3504                         *result = ah->regulatory.max_power_level;
3505                         return 0;
3506                 case 3:
3507                         *result = ah->regulatory.tp_scale;
3508                         return 0;
3509                 }
3510                 return false;
3511         case ATH9K_CAP_DS:
3512                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3513                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3514                         ? false : true;
3515         default:
3516                 return false;
3517         }
3518 }
3519
3520 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3521                             u32 capability, u32 setting, int *status)
3522 {
3523         u32 v;
3524
3525         switch (type) {
3526         case ATH9K_CAP_TKIP_MIC:
3527                 if (setting)
3528                         ah->sta_id1_defaults |=
3529                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3530                 else
3531                         ah->sta_id1_defaults &=
3532                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3533                 return true;
3534         case ATH9K_CAP_DIVERSITY:
3535                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3536                 if (setting)
3537                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3538                 else
3539                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3540                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3541                 return true;
3542         case ATH9K_CAP_MCAST_KEYSRCH:
3543                 if (setting)
3544                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3545                 else
3546                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3547                 return true;
3548         default:
3549                 return false;
3550         }
3551 }
3552
3553 /****************************/
3554 /* GPIO / RFKILL / Antennae */
3555 /****************************/
3556
3557 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3558                                          u32 gpio, u32 type)
3559 {
3560         int addr;
3561         u32 gpio_shift, tmp;
3562
3563         if (gpio > 11)
3564                 addr = AR_GPIO_OUTPUT_MUX3;
3565         else if (gpio > 5)
3566                 addr = AR_GPIO_OUTPUT_MUX2;
3567         else
3568                 addr = AR_GPIO_OUTPUT_MUX1;
3569
3570         gpio_shift = (gpio % 6) * 5;
3571
3572         if (AR_SREV_9280_20_OR_LATER(ah)
3573             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3574                 REG_RMW(ah, addr, (type << gpio_shift),
3575                         (0x1f << gpio_shift));
3576         } else {
3577                 tmp = REG_READ(ah, addr);
3578                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3579                 tmp &= ~(0x1f << gpio_shift);
3580                 tmp |= (type << gpio_shift);
3581                 REG_WRITE(ah, addr, tmp);
3582         }
3583 }
3584
3585 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3586 {
3587         u32 gpio_shift;
3588
3589         ASSERT(gpio < ah->caps.num_gpio_pins);
3590
3591         gpio_shift = gpio << 1;
3592
3593         REG_RMW(ah,
3594                 AR_GPIO_OE_OUT,
3595                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3596                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3597 }
3598
3599 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3600 {
3601 #define MS_REG_READ(x, y) \
3602         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3603
3604         if (gpio >= ah->caps.num_gpio_pins)
3605                 return 0xffffffff;
3606
3607         if (AR_SREV_9285_10_OR_LATER(ah))
3608                 return MS_REG_READ(AR9285, gpio) != 0;
3609         else if (AR_SREV_9280_10_OR_LATER(ah))
3610                 return MS_REG_READ(AR928X, gpio) != 0;
3611         else
3612                 return MS_REG_READ(AR, gpio) != 0;
3613 }
3614
3615 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3616                          u32 ah_signal_type)
3617 {
3618         u32 gpio_shift;
3619
3620         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3621
3622         gpio_shift = 2 * gpio;
3623
3624         REG_RMW(ah,
3625                 AR_GPIO_OE_OUT,
3626                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3627                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3628 }
3629
3630 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3631 {
3632         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3633                 AR_GPIO_BIT(gpio));
3634 }
3635
3636 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3637 void ath9k_enable_rfkill(struct ath_hw *ah)
3638 {
3639         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3640                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3641
3642         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3643                     AR_GPIO_INPUT_MUX2_RFSILENT);
3644
3645         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3646         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3647 }
3648 #endif
3649
3650 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3651 {
3652         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3653 }
3654
3655 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3656 {
3657         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3658 }
3659
3660 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3661                                enum ath9k_ant_setting settings,
3662                                struct ath9k_channel *chan,
3663                                u8 *tx_chainmask,
3664                                u8 *rx_chainmask,
3665                                u8 *antenna_cfgd)
3666 {
3667         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3668
3669         if (AR_SREV_9280(ah)) {
3670                 if (!tx_chainmask_cfg) {
3671
3672                         tx_chainmask_cfg = *tx_chainmask;
3673                         rx_chainmask_cfg = *rx_chainmask;
3674                 }
3675
3676                 switch (settings) {
3677                 case ATH9K_ANT_FIXED_A:
3678                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3679                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3680                         *antenna_cfgd = true;
3681                         break;
3682                 case ATH9K_ANT_FIXED_B:
3683                         if (ah->caps.tx_chainmask >
3684                             ATH9K_ANTENNA1_CHAINMASK) {
3685                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3686                         }
3687                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3688                         *antenna_cfgd = true;
3689                         break;
3690                 case ATH9K_ANT_VARIABLE:
3691                         *tx_chainmask = tx_chainmask_cfg;
3692                         *rx_chainmask = rx_chainmask_cfg;
3693                         *antenna_cfgd = true;
3694                         break;
3695                 default:
3696                         break;
3697                 }
3698         } else {
3699                 ah->diversity_control = settings;
3700         }
3701
3702         return true;
3703 }
3704
3705 /*********************/
3706 /* General Operation */
3707 /*********************/
3708
3709 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3710 {
3711         u32 bits = REG_READ(ah, AR_RX_FILTER);
3712         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3713
3714         if (phybits & AR_PHY_ERR_RADAR)
3715                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3716         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3717                 bits |= ATH9K_RX_FILTER_PHYERR;
3718
3719         return bits;
3720 }
3721
3722 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3723 {
3724         u32 phybits;
3725
3726         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3727         phybits = 0;
3728         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3729                 phybits |= AR_PHY_ERR_RADAR;
3730         if (bits & ATH9K_RX_FILTER_PHYERR)
3731                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3732         REG_WRITE(ah, AR_PHY_ERR, phybits);
3733
3734         if (phybits)
3735                 REG_WRITE(ah, AR_RXCFG,
3736                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3737         else
3738                 REG_WRITE(ah, AR_RXCFG,
3739                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3740 }
3741
3742 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3743 {
3744         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3745 }
3746
3747 bool ath9k_hw_disable(struct ath_hw *ah)
3748 {
3749         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3750                 return false;
3751
3752         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3753 }
3754
3755 bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3756 {
3757         struct ath9k_channel *chan = ah->curchan;
3758         struct ieee80211_channel *channel = chan->chan;
3759
3760         ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3761
3762         if (ah->eep_ops->set_txpower(ah, chan,
3763                              ath9k_regd_get_ctl(ah, chan),
3764                              channel->max_antenna_gain * 2,
3765                              channel->max_power * 2,
3766                              min((u32) MAX_RATE_POWER,
3767                                  (u32) ah->regulatory.power_limit)) != 0)
3768                 return false;
3769
3770         return true;
3771 }
3772
3773 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3774 {
3775         memcpy(ah->macaddr, mac, ETH_ALEN);
3776 }
3777
3778 void ath9k_hw_setopmode(struct ath_hw *ah)
3779 {
3780         ath9k_hw_set_operating_mode(ah, ah->opmode);
3781 }
3782
3783 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3784 {
3785         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3786         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3787 }
3788
3789 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3790 {
3791         REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3792         REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3793 }
3794
3795 void ath9k_hw_write_associd(struct ath_softc *sc)
3796 {
3797         REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3798         REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3799                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3800 }
3801
3802 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3803 {
3804         u64 tsf;
3805
3806         tsf = REG_READ(ah, AR_TSF_U32);
3807         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3808
3809         return tsf;
3810 }
3811
3812 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3813 {
3814         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3815         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3816 }
3817
3818 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3819 {
3820         int count;
3821
3822         count = 0;
3823         while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3824                 count++;
3825                 if (count > 10) {
3826                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3827                                 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3828                         break;
3829                 }
3830                 udelay(10);
3831         }
3832         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3833 }
3834
3835 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3836 {
3837         if (setting)
3838                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3839         else
3840                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3841
3842         return true;
3843 }
3844
3845 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3846 {
3847         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3848                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3849                 ah->slottime = (u32) -1;
3850                 return false;
3851         } else {
3852                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3853                 ah->slottime = us;
3854                 return true;
3855         }
3856 }
3857
3858 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3859 {
3860         u32 macmode;
3861
3862         if (mode == ATH9K_HT_MACMODE_2040 &&
3863             !ah->config.cwm_ignore_extcca)
3864                 macmode = AR_2040_JOINED_RX_CLEAR;
3865         else
3866                 macmode = 0;
3867
3868         REG_WRITE(ah, AR_2040_MODE, macmode);
3869 }
3870
3871 /***************************/
3872 /*  Bluetooth Coexistence  */
3873 /***************************/
3874
3875 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3876 {
3877         /* connect bt_active to baseband */
3878         REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3879                         (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3880                          AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3881
3882         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3883                         AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3884
3885         /* Set input mux for bt_active to gpio pin */
3886         REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3887                         AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3888                         ah->btactive_gpio);
3889
3890         /* Configure the desired gpio port for input */
3891         ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3892
3893         /* Configure the desired GPIO port for TX_FRAME output */
3894         ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3895                             AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3896 }