2 * AMD Geode definitions
3 * Copyright (C) 2006, Advanced Micro Devices, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of version 2 of the GNU General Public License
7 * as published by the Free Software Foundation.
13 #include <asm/processor.h>
16 /* Generic southbridge functions */
18 #define GEODE_DEV_PMS 0
19 #define GEODE_DEV_ACPI 1
20 #define GEODE_DEV_GPIO 2
21 #define GEODE_DEV_MFGPT 3
23 extern int geode_get_dev_base(unsigned int dev);
26 #define geode_pms_base() geode_get_dev_base(GEODE_DEV_PMS)
27 #define geode_acpi_base() geode_get_dev_base(GEODE_DEV_ACPI)
28 #define geode_gpio_base() geode_get_dev_base(GEODE_DEV_GPIO)
29 #define geode_mfgpt_base() geode_get_dev_base(GEODE_DEV_MFGPT)
33 #define MSR_GLIU_P2D_RO0 0x10000029
35 #define MSR_LX_GLD_MSR_CONFIG 0x48002001
36 #define MSR_LX_MSR_PADSEL 0x48002011 /* NOT 0x48000011; the data
37 * sheet has the wrong value */
38 #define MSR_GLCP_SYS_RSTPLL 0x4C000014
39 #define MSR_GLCP_DOTPLL 0x4C000015
41 #define MSR_LBAR_SMB 0x5140000B
42 #define MSR_LBAR_GPIO 0x5140000C
43 #define MSR_LBAR_MFGPT 0x5140000D
44 #define MSR_LBAR_ACPI 0x5140000E
45 #define MSR_LBAR_PMS 0x5140000F
47 #define MSR_DIVIL_SOFT_RESET 0x51400017
49 #define MSR_PIC_YSEL_LOW 0x51400020
50 #define MSR_PIC_YSEL_HIGH 0x51400021
51 #define MSR_PIC_ZSEL_LOW 0x51400022
52 #define MSR_PIC_ZSEL_HIGH 0x51400023
54 #define MSR_MFGPT_IRQ 0x51400028
55 #define MSR_MFGPT_NR 0x51400029
56 #define MSR_MFGPT_SETUP 0x5140002B
58 #define MSR_LX_SPARE_MSR 0x80000011 /* DC-specific */
60 #define MSR_GX_GLD_MSR_CONFIG 0xC0002001
61 #define MSR_GX_MSR_PADSEL 0xC0002011
65 #define LBAR_GPIO_SIZE 0xFF
66 #define LBAR_MFGPT_SIZE 0x40
67 #define LBAR_ACPI_SIZE 0x40
68 #define LBAR_PMS_SIZE 0x80
70 /* ACPI registers (PMS block) */
73 * PM1_EN is only valid when VSA is enabled for 16 bit reads.
74 * When VSA is not enabled, *always* read both PM1_STS and PM1_EN
75 * with a 32 bit read at offset 0x0
83 #define PM_GPE0_STS 0x18
84 #define PM_GPE0_EN 0x1C
86 /* PMC registers (PMS block) */
91 #define PM_OUT_SLPCTL 0x0C
96 #define PM_IN_SLPCTL 0x20
108 /* VSA2 magic values */
110 #define VSA_VRC_INDEX 0xAC1C
111 #define VSA_VRC_DATA 0xAC1E
112 #define VSA_VR_UNLOCK 0xFC53 /* unlock virtual register */
113 #define VSA_VR_SIGNATURE 0x0003
114 #define VSA_VR_MEM_SIZE 0x0200
115 #define AMD_VSA_SIG 0x4132 /* signature is ascii 'VSA2' */
116 #define GSW_VSA_SIG 0x534d /* General Software signature */
119 #define GPIO_OUTPUT_VAL 0x00
120 #define GPIO_OUTPUT_ENABLE 0x04
121 #define GPIO_OUTPUT_OPEN_DRAIN 0x08
122 #define GPIO_OUTPUT_INVERT 0x0C
123 #define GPIO_OUTPUT_AUX1 0x10
124 #define GPIO_OUTPUT_AUX2 0x14
125 #define GPIO_PULL_UP 0x18
126 #define GPIO_PULL_DOWN 0x1C
127 #define GPIO_INPUT_ENABLE 0x20
128 #define GPIO_INPUT_INVERT 0x24
129 #define GPIO_INPUT_FILTER 0x28
130 #define GPIO_INPUT_EVENT_COUNT 0x2C
131 #define GPIO_READ_BACK 0x30
132 #define GPIO_INPUT_AUX1 0x34
133 #define GPIO_EVENTS_ENABLE 0x38
134 #define GPIO_LOCK_ENABLE 0x3C
135 #define GPIO_POSITIVE_EDGE_EN 0x40
136 #define GPIO_NEGATIVE_EDGE_EN 0x44
137 #define GPIO_POSITIVE_EDGE_STS 0x48
138 #define GPIO_NEGATIVE_EDGE_STS 0x4C
140 #define GPIO_MAP_X 0xE0
141 #define GPIO_MAP_Y 0xE4
142 #define GPIO_MAP_Z 0xE8
143 #define GPIO_MAP_W 0xEC
145 static inline u32 geode_gpio(unsigned int nr)
151 extern void geode_gpio_set(u32, unsigned int);
152 extern void geode_gpio_clear(u32, unsigned int);
153 extern int geode_gpio_isset(u32, unsigned int);
154 extern void geode_gpio_setup_event(unsigned int, int, int);
155 extern void geode_gpio_set_irq(unsigned int, unsigned int);
157 static inline void geode_gpio_event_irq(unsigned int gpio, int pair)
159 geode_gpio_setup_event(gpio, pair, 0);
162 static inline void geode_gpio_event_pme(unsigned int gpio, int pair)
164 geode_gpio_setup_event(gpio, pair, 1);
167 /* Specific geode tests */
169 static inline int is_geode_gx(void)
171 return ((boot_cpu_data.x86_vendor == X86_VENDOR_NSC) &&
172 (boot_cpu_data.x86 == 5) &&
173 (boot_cpu_data.x86_model == 5));
176 static inline int is_geode_lx(void)
178 return ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
179 (boot_cpu_data.x86 == 5) &&
180 (boot_cpu_data.x86_model == 10));
183 static inline int is_geode(void)
185 return (is_geode_gx() || is_geode_lx());
188 #ifdef CONFIG_MGEODE_LX
189 extern int geode_has_vsa2(void);
191 static inline int geode_has_vsa2(void)
199 #define MFGPT_MAX_TIMERS 8
200 #define MFGPT_TIMER_ANY (-1)
202 #define MFGPT_DOMAIN_WORKING 1
203 #define MFGPT_DOMAIN_STANDBY 2
204 #define MFGPT_DOMAIN_ANY (MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY)
209 #define MFGPT_EVENT_IRQ 0
210 #define MFGPT_EVENT_NMI 1
211 #define MFGPT_EVENT_RESET 3
213 #define MFGPT_REG_CMP1 0
214 #define MFGPT_REG_CMP2 2
215 #define MFGPT_REG_COUNTER 4
216 #define MFGPT_REG_SETUP 6
218 #define MFGPT_SETUP_CNTEN (1 << 15)
219 #define MFGPT_SETUP_CMP2 (1 << 14)
220 #define MFGPT_SETUP_CMP1 (1 << 13)
221 #define MFGPT_SETUP_SETUP (1 << 12)
222 #define MFGPT_SETUP_STOPEN (1 << 11)
223 #define MFGPT_SETUP_EXTEN (1 << 10)
224 #define MFGPT_SETUP_REVEN (1 << 5)
225 #define MFGPT_SETUP_CLKSEL (1 << 4)
227 static inline void geode_mfgpt_write(int timer, u16 reg, u16 value)
229 u32 base = geode_get_dev_base(GEODE_DEV_MFGPT);
230 outw(value, base + reg + (timer * 8));
233 static inline u16 geode_mfgpt_read(int timer, u16 reg)
235 u32 base = geode_get_dev_base(GEODE_DEV_MFGPT);
236 return inw(base + reg + (timer * 8));
239 extern int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable);
240 extern int geode_mfgpt_set_irq(int timer, int cmp, int irq, int enable);
241 extern int geode_mfgpt_alloc_timer(int timer, int domain);
243 #define geode_mfgpt_setup_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 1)
244 #define geode_mfgpt_release_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 0)
246 #ifdef CONFIG_GEODE_MFGPT_TIMER
247 extern int __init mfgpt_timer_setup(void);
249 static inline int mfgpt_timer_setup(void) { return 0; }