2 * Suspend support specific for i386.
4 * Distribute under GPLv2
6 * Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
7 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
10 #include <linux/smp.h>
11 #include <linux/suspend.h>
12 #include <asm/proto.h>
14 #include <asm/pgtable.h>
17 /* References to section boundaries */
18 extern const void __nosave_begin, __nosave_end;
20 struct saved_context saved_context;
22 unsigned long saved_context_eax, saved_context_ebx, saved_context_ecx, saved_context_edx;
23 unsigned long saved_context_esp, saved_context_ebp, saved_context_esi, saved_context_edi;
24 unsigned long saved_context_r08, saved_context_r09, saved_context_r10, saved_context_r11;
25 unsigned long saved_context_r12, saved_context_r13, saved_context_r14, saved_context_r15;
26 unsigned long saved_context_eflags;
28 void __save_processor_state(struct saved_context *ctxt)
35 asm volatile ("sgdt %0" : "=m" (ctxt->gdt_limit));
36 asm volatile ("sidt %0" : "=m" (ctxt->idt_limit));
37 asm volatile ("str %0" : "=m" (ctxt->tr));
39 /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
43 asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
44 asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
45 asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
46 asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
47 asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
49 rdmsrl(MSR_FS_BASE, ctxt->fs_base);
50 rdmsrl(MSR_GS_BASE, ctxt->gs_base);
51 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
52 mtrr_save_fixed_ranges(NULL);
57 rdmsrl(MSR_EFER, ctxt->efer);
58 asm volatile ("movq %%cr0, %0" : "=r" (ctxt->cr0));
59 asm volatile ("movq %%cr2, %0" : "=r" (ctxt->cr2));
60 asm volatile ("movq %%cr3, %0" : "=r" (ctxt->cr3));
61 asm volatile ("movq %%cr4, %0" : "=r" (ctxt->cr4));
62 asm volatile ("movq %%cr8, %0" : "=r" (ctxt->cr8));
65 void save_processor_state(void)
67 __save_processor_state(&saved_context);
70 static void do_fpu_end(void)
73 * Restore FPU regs if necessary
78 void __restore_processor_state(struct saved_context *ctxt)
83 wrmsrl(MSR_EFER, ctxt->efer);
84 asm volatile ("movq %0, %%cr8" :: "r" (ctxt->cr8));
85 asm volatile ("movq %0, %%cr4" :: "r" (ctxt->cr4));
86 asm volatile ("movq %0, %%cr3" :: "r" (ctxt->cr3));
87 asm volatile ("movq %0, %%cr2" :: "r" (ctxt->cr2));
88 asm volatile ("movq %0, %%cr0" :: "r" (ctxt->cr0));
91 * now restore the descriptor tables to their proper values
92 * ltr is done i fix_processor_context().
94 asm volatile ("lgdt %0" :: "m" (ctxt->gdt_limit));
95 asm volatile ("lidt %0" :: "m" (ctxt->idt_limit));
100 asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
101 asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
102 asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
103 load_gs_index(ctxt->gs);
104 asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
106 wrmsrl(MSR_FS_BASE, ctxt->fs_base);
107 wrmsrl(MSR_GS_BASE, ctxt->gs_base);
108 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
110 fix_processor_context();
116 void restore_processor_state(void)
118 __restore_processor_state(&saved_context);
121 void fix_processor_context(void)
123 int cpu = smp_processor_id();
124 struct tss_struct *t = &per_cpu(init_tss, cpu);
126 set_tss_desc(cpu,t); /* This just modifies memory; should not be neccessary. But... This is neccessary, because 386 hardware has concept of busy TSS or some similar stupidity. */
128 cpu_gdt(cpu)[GDT_ENTRY_TSS].type = 9;
130 syscall_init(); /* This sets MSR_*STAR and related */
131 load_TR_desc(); /* This does ltr */
132 load_LDT(¤t->active_mm->context); /* This does lldt */
135 * Now maybe reload the debug registers
137 if (current->thread.debugreg7){
138 loaddebug(¤t->thread, 0);
139 loaddebug(¤t->thread, 1);
140 loaddebug(¤t->thread, 2);
141 loaddebug(¤t->thread, 3);
143 loaddebug(¤t->thread, 6);
144 loaddebug(¤t->thread, 7);
149 #ifdef CONFIG_SOFTWARE_SUSPEND
150 /* Defined in arch/x86_64/kernel/suspend_asm.S */
151 extern int restore_image(void);
153 pgd_t *temp_level4_pgt;
155 static int res_phys_pud_init(pud_t *pud, unsigned long address, unsigned long end)
159 i = pud_index(address);
161 for (; i < PTRS_PER_PUD; pud++, i++) {
165 paddr = address + i*PUD_SIZE;
169 pmd = (pmd_t *)get_safe_page(GFP_ATOMIC);
172 set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE));
173 for (j = 0; j < PTRS_PER_PMD; pmd++, j++, paddr += PMD_SIZE) {
178 pe = _PAGE_NX | _PAGE_PSE | _KERNPG_TABLE | paddr;
179 pe &= __supported_pte_mask;
180 set_pmd(pmd, __pmd(pe));
186 static int set_up_temporary_mappings(void)
188 unsigned long start, end, next;
191 temp_level4_pgt = (pgd_t *)get_safe_page(GFP_ATOMIC);
192 if (!temp_level4_pgt)
195 /* It is safe to reuse the original kernel mapping */
196 set_pgd(temp_level4_pgt + pgd_index(__START_KERNEL_map),
197 init_level4_pgt[pgd_index(__START_KERNEL_map)]);
199 /* Set up the direct mapping from scratch */
200 start = (unsigned long)pfn_to_kaddr(0);
201 end = (unsigned long)pfn_to_kaddr(end_pfn);
203 for (; start < end; start = next) {
204 pud_t *pud = (pud_t *)get_safe_page(GFP_ATOMIC);
207 next = start + PGDIR_SIZE;
210 if ((error = res_phys_pud_init(pud, __pa(start), __pa(next))))
212 set_pgd(temp_level4_pgt + pgd_index(start),
213 mk_kernel_pgd(__pa(pud)));
218 int swsusp_arch_resume(void)
222 /* We have got enough memory and from now on we cannot recover */
223 if ((error = set_up_temporary_mappings()))
230 * pfn_is_nosave - check if given pfn is in the 'nosave' section
233 int pfn_is_nosave(unsigned long pfn)
235 unsigned long nosave_begin_pfn = __pa_symbol(&__nosave_begin) >> PAGE_SHIFT;
236 unsigned long nosave_end_pfn = PAGE_ALIGN(__pa_symbol(&__nosave_end)) >> PAGE_SHIFT;
237 return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
239 #endif /* CONFIG_SOFTWARE_SUSPEND */