Merge watchdog driver updates
[linux-2.6] / arch / ppc64 / kernel / pmac_nvram.c
1 /*
2  *  arch/ppc/platforms/pmac_nvram.c
3  *
4  *  Copyright (C) 2002 Benjamin Herrenschmidt (benh@kernel.crashing.org)
5  *
6  *  This program is free software; you can redistribute it and/or
7  *  modify it under the terms of the GNU General Public License
8  *  as published by the Free Software Foundation; either version
9  *  2 of the License, or (at your option) any later version.
10  *
11  *  Todo: - add support for the OF persistent properties
12  */
13 #include <linux/config.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/stddef.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/errno.h>
22 #include <linux/bootmem.h>
23 #include <linux/completion.h>
24 #include <linux/spinlock.h>
25 #include <asm/sections.h>
26 #include <asm/io.h>
27 #include <asm/system.h>
28 #include <asm/prom.h>
29 #include <asm/machdep.h>
30 #include <asm/nvram.h>
31
32 #define DEBUG
33
34 #ifdef DEBUG
35 #define DBG(x...) printk(x)
36 #else
37 #define DBG(x...)
38 #endif
39
40 #define NVRAM_SIZE              0x2000  /* 8kB of non-volatile RAM */
41
42 #define CORE99_SIGNATURE        0x5a
43 #define CORE99_ADLER_START      0x14
44
45 /* On Core99, nvram is either a sharp, a micron or an AMD flash */
46 #define SM_FLASH_STATUS_DONE    0x80
47 #define SM_FLASH_STATUS_ERR     0x38
48
49 #define SM_FLASH_CMD_ERASE_CONFIRM      0xd0
50 #define SM_FLASH_CMD_ERASE_SETUP        0x20
51 #define SM_FLASH_CMD_RESET              0xff
52 #define SM_FLASH_CMD_WRITE_SETUP        0x40
53 #define SM_FLASH_CMD_CLEAR_STATUS       0x50
54 #define SM_FLASH_CMD_READ_STATUS        0x70
55
56 /* CHRP NVRAM header */
57 struct chrp_header {
58   u8            signature;
59   u8            cksum;
60   u16           len;
61   char          name[12];
62   u8            data[0];
63 };
64
65 struct core99_header {
66   struct chrp_header    hdr;
67   u32                   adler;
68   u32                   generation;
69   u32                   reserved[2];
70 };
71
72 /*
73  * Read and write the non-volatile RAM on PowerMacs and CHRP machines.
74  */
75 static volatile unsigned char *nvram_data;
76 static int core99_bank = 0;
77 // XXX Turn that into a sem
78 static DEFINE_SPINLOCK(nv_lock);
79
80 extern int system_running;
81
82 static int (*core99_write_bank)(int bank, u8* datas);
83 static int (*core99_erase_bank)(int bank);
84
85 static char *nvram_image __pmacdata;
86
87
88 static ssize_t __pmac core99_nvram_read(char *buf, size_t count, loff_t *index)
89 {
90         int i;
91
92         if (nvram_image == NULL)
93                 return -ENODEV;
94         if (*index > NVRAM_SIZE)
95                 return 0;
96
97         i = *index;
98         if (i + count > NVRAM_SIZE)
99                 count = NVRAM_SIZE - i;
100
101         memcpy(buf, &nvram_image[i], count);
102         *index = i + count;
103         return count;
104 }
105
106 static ssize_t __pmac core99_nvram_write(char *buf, size_t count, loff_t *index)
107 {
108         int i;
109
110         if (nvram_image == NULL)
111                 return -ENODEV;
112         if (*index > NVRAM_SIZE)
113                 return 0;
114
115         i = *index;
116         if (i + count > NVRAM_SIZE)
117                 count = NVRAM_SIZE - i;
118
119         memcpy(&nvram_image[i], buf, count);
120         *index = i + count;
121         return count;
122 }
123
124 static ssize_t __pmac core99_nvram_size(void)
125 {
126         if (nvram_image == NULL)
127                 return -ENODEV;
128         return NVRAM_SIZE;
129 }
130
131 static u8 __pmac chrp_checksum(struct chrp_header* hdr)
132 {
133         u8 *ptr;
134         u16 sum = hdr->signature;
135         for (ptr = (u8 *)&hdr->len; ptr < hdr->data; ptr++)
136                 sum += *ptr;
137         while (sum > 0xFF)
138                 sum = (sum & 0xFF) + (sum>>8);
139         return sum;
140 }
141
142 static u32 __pmac core99_calc_adler(u8 *buffer)
143 {
144         int cnt;
145         u32 low, high;
146
147         buffer += CORE99_ADLER_START;
148         low = 1;
149         high = 0;
150         for (cnt=0; cnt<(NVRAM_SIZE-CORE99_ADLER_START); cnt++) {
151                 if ((cnt % 5000) == 0) {
152                         high  %= 65521UL;
153                         high %= 65521UL;
154                 }
155                 low += buffer[cnt];
156                 high += low;
157         }
158         low  %= 65521UL;
159         high %= 65521UL;
160
161         return (high << 16) | low;
162 }
163
164 static u32 __pmac core99_check(u8* datas)
165 {
166         struct core99_header* hdr99 = (struct core99_header*)datas;
167
168         if (hdr99->hdr.signature != CORE99_SIGNATURE) {
169                 DBG("Invalid signature\n");
170                 return 0;
171         }
172         if (hdr99->hdr.cksum != chrp_checksum(&hdr99->hdr)) {
173                 DBG("Invalid checksum\n");
174                 return 0;
175         }
176         if (hdr99->adler != core99_calc_adler(datas)) {
177                 DBG("Invalid adler\n");
178                 return 0;
179         }
180         return hdr99->generation;
181 }
182
183 static int __pmac sm_erase_bank(int bank)
184 {
185         int stat, i;
186         unsigned long timeout;
187
188         u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
189
190         DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);
191
192         out_8(base, SM_FLASH_CMD_ERASE_SETUP);
193         out_8(base, SM_FLASH_CMD_ERASE_CONFIRM);
194         timeout = 0;
195         do {
196                 if (++timeout > 1000000) {
197                         printk(KERN_ERR "nvram: Sharp/Miron flash erase timeout !\n");
198                         break;
199                 }
200                 out_8(base, SM_FLASH_CMD_READ_STATUS);
201                 stat = in_8(base);
202         } while (!(stat & SM_FLASH_STATUS_DONE));
203
204         out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
205         out_8(base, SM_FLASH_CMD_RESET);
206
207         for (i=0; i<NVRAM_SIZE; i++)
208                 if (base[i] != 0xff) {
209                         printk(KERN_ERR "nvram: Sharp/Micron flash erase failed !\n");
210                         return -ENXIO;
211                 }
212         return 0;
213 }
214
215 static int __pmac sm_write_bank(int bank, u8* datas)
216 {
217         int i, stat = 0;
218         unsigned long timeout;
219
220         u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
221
222         DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);
223
224         for (i=0; i<NVRAM_SIZE; i++) {
225                 out_8(base+i, SM_FLASH_CMD_WRITE_SETUP);
226                 udelay(1);
227                 out_8(base+i, datas[i]);
228                 timeout = 0;
229                 do {
230                         if (++timeout > 1000000) {
231                                 printk(KERN_ERR "nvram: Sharp/Micron flash write timeout !\n");
232                                 break;
233                         }
234                         out_8(base, SM_FLASH_CMD_READ_STATUS);
235                         stat = in_8(base);
236                 } while (!(stat & SM_FLASH_STATUS_DONE));
237                 if (!(stat & SM_FLASH_STATUS_DONE))
238                         break;
239         }
240         out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
241         out_8(base, SM_FLASH_CMD_RESET);
242         for (i=0; i<NVRAM_SIZE; i++)
243                 if (base[i] != datas[i]) {
244                         printk(KERN_ERR "nvram: Sharp/Micron flash write failed !\n");
245                         return -ENXIO;
246                 }
247         return 0;
248 }
249
250 static int __pmac amd_erase_bank(int bank)
251 {
252         int i, stat = 0;
253         unsigned long timeout;
254
255         u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
256
257         DBG("nvram: AMD Erasing bank %d...\n", bank);
258
259         /* Unlock 1 */
260         out_8(base+0x555, 0xaa);
261         udelay(1);
262         /* Unlock 2 */
263         out_8(base+0x2aa, 0x55);
264         udelay(1);
265
266         /* Sector-Erase */
267         out_8(base+0x555, 0x80);
268         udelay(1);
269         out_8(base+0x555, 0xaa);
270         udelay(1);
271         out_8(base+0x2aa, 0x55);
272         udelay(1);
273         out_8(base, 0x30);
274         udelay(1);
275
276         timeout = 0;
277         do {
278                 if (++timeout > 1000000) {
279                         printk(KERN_ERR "nvram: AMD flash erase timeout !\n");
280                         break;
281                 }
282                 stat = in_8(base) ^ in_8(base);
283         } while (stat != 0);
284         
285         /* Reset */
286         out_8(base, 0xf0);
287         udelay(1);
288         
289         for (i=0; i<NVRAM_SIZE; i++)
290                 if (base[i] != 0xff) {
291                         printk(KERN_ERR "nvram: AMD flash erase failed !\n");
292                         return -ENXIO;
293                 }
294         return 0;
295 }
296
297 static int __pmac amd_write_bank(int bank, u8* datas)
298 {
299         int i, stat = 0;
300         unsigned long timeout;
301
302         u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
303
304         DBG("nvram: AMD Writing bank %d...\n", bank);
305
306         for (i=0; i<NVRAM_SIZE; i++) {
307                 /* Unlock 1 */
308                 out_8(base+0x555, 0xaa);
309                 udelay(1);
310                 /* Unlock 2 */
311                 out_8(base+0x2aa, 0x55);
312                 udelay(1);
313
314                 /* Write single word */
315                 out_8(base+0x555, 0xa0);
316                 udelay(1);
317                 out_8(base+i, datas[i]);
318                 
319                 timeout = 0;
320                 do {
321                         if (++timeout > 1000000) {
322                                 printk(KERN_ERR "nvram: AMD flash write timeout !\n");
323                                 break;
324                         }
325                         stat = in_8(base) ^ in_8(base);
326                 } while (stat != 0);
327                 if (stat != 0)
328                         break;
329         }
330
331         /* Reset */
332         out_8(base, 0xf0);
333         udelay(1);
334
335         for (i=0; i<NVRAM_SIZE; i++)
336                 if (base[i] != datas[i]) {
337                         printk(KERN_ERR "nvram: AMD flash write failed !\n");
338                         return -ENXIO;
339                 }
340         return 0;
341 }
342
343
344 static int __pmac core99_nvram_sync(void)
345 {
346         struct core99_header* hdr99;
347         unsigned long flags;
348
349         spin_lock_irqsave(&nv_lock, flags);
350         if (!memcmp(nvram_image, (u8*)nvram_data + core99_bank*NVRAM_SIZE,
351                 NVRAM_SIZE))
352                 goto bail;
353
354         DBG("Updating nvram...\n");
355
356         hdr99 = (struct core99_header*)nvram_image;
357         hdr99->generation++;
358         hdr99->hdr.signature = CORE99_SIGNATURE;
359         hdr99->hdr.cksum = chrp_checksum(&hdr99->hdr);
360         hdr99->adler = core99_calc_adler(nvram_image);
361         core99_bank = core99_bank ? 0 : 1;
362         if (core99_erase_bank)
363                 if (core99_erase_bank(core99_bank)) {
364                         printk("nvram: Error erasing bank %d\n", core99_bank);
365                         goto bail;
366                 }
367         if (core99_write_bank)
368                 if (core99_write_bank(core99_bank, nvram_image))
369                         printk("nvram: Error writing bank %d\n", core99_bank);
370  bail:
371         spin_unlock_irqrestore(&nv_lock, flags);
372
373         return 0;
374 }
375
376 int __init pmac_nvram_init(void)
377 {
378         struct device_node *dp;
379         u32 gen_bank0, gen_bank1;
380         int i;
381
382         dp = find_devices("nvram");
383         if (dp == NULL) {
384                 printk(KERN_ERR "Can't find NVRAM device\n");
385                 return -ENODEV;
386         }
387         if (!device_is_compatible(dp, "nvram,flash")) {
388                 printk(KERN_ERR "Incompatible type of NVRAM\n");
389                 return -ENXIO;
390         }
391
392         nvram_image = alloc_bootmem(NVRAM_SIZE);
393         if (nvram_image == NULL) {
394                 printk(KERN_ERR "nvram: can't allocate ram image\n");
395                 return -ENOMEM;
396         }
397         nvram_data = ioremap(dp->addrs[0].address, NVRAM_SIZE*2);
398         
399         DBG("nvram: Checking bank 0...\n");
400
401         gen_bank0 = core99_check((u8 *)nvram_data);
402         gen_bank1 = core99_check((u8 *)nvram_data + NVRAM_SIZE);
403         core99_bank = (gen_bank0 < gen_bank1) ? 1 : 0;
404
405         DBG("nvram: gen0=%d, gen1=%d\n", gen_bank0, gen_bank1);
406         DBG("nvram: Active bank is: %d\n", core99_bank);
407
408         for (i=0; i<NVRAM_SIZE; i++)
409                 nvram_image[i] = nvram_data[i + core99_bank*NVRAM_SIZE];
410
411         ppc_md.nvram_read       = core99_nvram_read;
412         ppc_md.nvram_write      = core99_nvram_write;
413         ppc_md.nvram_size       = core99_nvram_size;
414         ppc_md.nvram_sync       = core99_nvram_sync;
415         
416         /* 
417          * Maybe we could be smarter here though making an exclusive list
418          * of known flash chips is a bit nasty as older OF didn't provide us
419          * with a useful "compatible" entry. A solution would be to really
420          * identify the chip using flash id commands and base ourselves on
421          * a list of known chips IDs
422          */
423         if (device_is_compatible(dp, "amd-0137")) {
424                 core99_erase_bank = amd_erase_bank;
425                 core99_write_bank = amd_write_bank;
426         } else {
427                 core99_erase_bank = sm_erase_bank;
428                 core99_write_bank = sm_write_bank;
429         }
430
431         return 0;
432 }
433
434 int __pmac pmac_get_partition(int partition)
435 {
436         struct nvram_partition *part;
437         const char *name;
438         int sig;
439
440         switch(partition) {
441         case pmac_nvram_OF:
442                 name = "common";
443                 sig = NVRAM_SIG_SYS;
444                 break;
445         case pmac_nvram_XPRAM:
446                 name = "APL,MacOS75";
447                 sig = NVRAM_SIG_OS;
448                 break;
449         case pmac_nvram_NR:
450         default:
451                 /* Oldworld stuff */
452                 return -ENODEV;
453         }
454
455         part = nvram_find_partition(sig, name);
456         if (part == NULL)
457                 return 0;
458
459         return part->index;
460 }
461
462 u8 __pmac pmac_xpram_read(int xpaddr)
463 {
464         int offset = pmac_get_partition(pmac_nvram_XPRAM);
465         loff_t index;
466         u8 buf;
467         ssize_t count;
468
469         if (offset < 0 || xpaddr < 0 || xpaddr > 0x100)
470                 return 0xff;
471         index = offset + xpaddr;
472
473         count = ppc_md.nvram_read(&buf, 1, &index);
474         if (count != 1)
475                 return 0xff;
476         return buf;
477 }
478
479 void __pmac pmac_xpram_write(int xpaddr, u8 data)
480 {
481         int offset = pmac_get_partition(pmac_nvram_XPRAM);
482         loff_t index;
483         u8 buf;
484
485         if (offset < 0 || xpaddr < 0 || xpaddr > 0x100)
486                 return;
487         index = offset + xpaddr;
488         buf = data;
489
490         ppc_md.nvram_write(&buf, 1, &index);
491 }
492
493 EXPORT_SYMBOL(pmac_get_partition);
494 EXPORT_SYMBOL(pmac_xpram_read);
495 EXPORT_SYMBOL(pmac_xpram_write);