git.oblomov.eu Git - linux-2.6/blob - arch/blackfin/mach-common/cpufreq.c

   1 /*
   2  * File:         arch/blackfin/mach-common/cpufreq.c
   3  * Based on:
   4  * Author:
   5  *
   6  * Created:
   7  * Description:  Blackfin core clock scaling
   8  *
   9  * Modified:
  10  *               Copyright 2004-2008 Analog Devices Inc.
  11  *
  12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, see the file COPYING, or write
  26  * to the Free Software Foundation, Inc.,
  27  * 51 Franklin St, Fifth Floor, Boston, MA      02110-1301      USA
  28  */
  29
  30 #include <linux/kernel.h>
  31 #include <linux/types.h>
  32 #include <linux/init.h>
  33 #include <linux/cpufreq.h>
  34 #include <linux/fs.h>
  35 #include <asm/blackfin.h>
  36 #include <asm/time.h>
  37
  38
  39 /* this is the table of CCLK frequencies, in Hz */
  40 /* .index is the entry in the auxillary dpm_state_table[] */
  41 static struct cpufreq_frequency_table bfin_freq_table[] = {
  42         {
  43                 .frequency = CPUFREQ_TABLE_END,
  44                 .index = 0,
  45         },
  46         {
  47                 .frequency = CPUFREQ_TABLE_END,
  48                 .index = 1,
  49         },
  50         {
  51                 .frequency = CPUFREQ_TABLE_END,
  52                 .index = 2,
  53         },
  54         {
  55                 .frequency = CPUFREQ_TABLE_END,
  56                 .index = 0,
  57         },
  58 };
  59
  60 static struct bfin_dpm_state {
  61         unsigned int csel; /* system clock divider */
  62         unsigned int tscale; /* change the divider on the core timer interrupt */
  63 } dpm_state_table[3];
  64
  65 /**************************************************************************/
  66
  67 static unsigned int bfin_getfreq(unsigned int cpu)
  68 {
  69         /* The driver only support single cpu */
  70         if (cpu != 0)
  71                 return -1;
  72
  73         return get_cclk();
  74 }
  75
  76
  77 static int bfin_target(struct cpufreq_policy *policy,
  78                         unsigned int target_freq, unsigned int relation)
  79 {
  80         unsigned int index, plldiv, tscale;
  81         unsigned long flags, cclk_hz;
  82         struct cpufreq_freqs freqs;
  83
  84         if (cpufreq_frequency_table_target(policy, bfin_freq_table,
  85                  target_freq, relation, &index))
  86                 return -EINVAL;
  87
  88         cclk_hz = bfin_freq_table[index].frequency;
  89
  90         freqs.old = bfin_getfreq(0);
  91         freqs.new = cclk_hz;
  92         freqs.cpu = 0;
  93
  94         pr_debug("cpufreq: changing cclk to %lu; target = %u, oldfreq = %u\n",
  95                  cclk_hz, target_freq, freqs.old);
  96
  97         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
  98         local_irq_save(flags);
  99                 plldiv = (bfin_read_PLL_DIV() & SSEL) | dpm_state_table[index].csel;
 100                 tscale = dpm_state_table[index].tscale;
 101                 bfin_write_PLL_DIV(plldiv);
 102                 /* we have to adjust the core timer, because it is using cclk */
 103                 bfin_write_TSCALE(tscale);
 104                 SSYNC();
 105         local_irq_restore(flags);
 106         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 107
 108         return 0;
 109 }
 110
 111 static int bfin_verify_speed(struct cpufreq_policy *policy)
 112 {
 113         return cpufreq_frequency_table_verify(policy, bfin_freq_table);
 114 }
 115
 116 static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
 117 {
 118
 119         unsigned long cclk, sclk, csel, min_cclk;
 120         int index;
 121
 122 #ifdef CONFIG_CYCLES_CLOCKSOURCE
 123 /*
 124  * Clocksource CYCLES is still CONTINUOUS but not longer with a constant tick rate in case we enable
 125  * CPU frequency scaling, since CYCLES runs off Core Clock.
 126  */
 127         printk(KERN_WARNING "CPU frequency scaling not supported: Clocksource not suitable\n"
 128                 return -ENODEV;
 129 #endif
 130
 131         if (policy->cpu != 0)
 132                 return -EINVAL;
 133
 134         cclk = get_cclk();
 135         sclk = get_sclk();
 136
 137 #if ANOMALY_05000273 || (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_DCACHE))
 138         min_cclk = sclk * 2;
 139 #else
 140         min_cclk = sclk;
 141 #endif
 142         csel = ((bfin_read_PLL_DIV() & CSEL) >> 4);
 143
 144         for (index = 0;  (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) {
 145                 bfin_freq_table[index].frequency = cclk >> index;
 146                 dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
 147                 dpm_state_table[index].tscale =  (TIME_SCALE / (1 << csel)) - 1;
 148
 149                 pr_debug("cpufreq: freq:%d csel:%d tscale:%d\n",
 150                                                  bfin_freq_table[index].frequency,
 151                                                  dpm_state_table[index].csel,
 152                                                  dpm_state_table[index].tscale);
 153         }
 154
 155         policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
 156
 157         policy->cpuinfo.transition_latency = (bfin_read_PLL_LOCKCNT() / (sclk / 1000000)) * 1000;
 158         /*Now ,only support one cpu */
 159         policy->cur = cclk;
 160         cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu);
 161         return cpufreq_frequency_table_cpuinfo(policy, bfin_freq_table);
 162 }
 163
 164 static struct freq_attr *bfin_freq_attr[] = {
 165         &cpufreq_freq_attr_scaling_available_freqs,
 166         NULL,
 167 };
 168
 169 static struct cpufreq_driver bfin_driver = {
 170         .verify = bfin_verify_speed,
 171         .target = bfin_target,
 172         .get = bfin_getfreq,
 173         .init = __bfin_cpu_init,
 174         .name = "bfin cpufreq",
 175         .owner = THIS_MODULE,
 176         .attr = bfin_freq_attr,
 177 };
 178
 179 static int __init bfin_cpu_init(void)
 180 {
 181         return cpufreq_register_driver(&bfin_driver);
 182 }
 183
 184 static void __exit bfin_cpu_exit(void)
 185 {
 186         cpufreq_unregister_driver(&bfin_driver);
 187 }
 188
 189 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
 190 MODULE_DESCRIPTION("cpufreq driver for Blackfin");
 191 MODULE_LICENSE("GPL");
 192
 193 module_init(bfin_cpu_init);
 194 module_exit(bfin_cpu_exit);