2 * drivers/video/aty/radeon_base.c
4 * framebuffer driver for ATI Radeon chipset video boards
6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
11 * Special thanks to ATI DevRel team for their hardware donations.
13 * ...Insert GPL boilerplate here...
15 * Significant portions of this driver apdated from XFree86 Radeon
16 * driver which has the following copyright notice:
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19 * VA Linux Systems Inc., Fremont, California.
21 * All Rights Reserved.
23 * Permission is hereby granted, free of charge, to any person obtaining
24 * a copy of this software and associated documentation files (the
25 * "Software"), to deal in the Software without restriction, including
26 * without limitation on the rights to use, copy, modify, merge,
27 * publish, distribute, sublicense, and/or sell copies of the Software,
28 * and to permit persons to whom the Software is furnished to do so,
29 * subject to the following conditions:
31 * The above copyright notice and this permission notice (including the
32 * next paragraph) shall be included in all copies or substantial
33 * portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 * DEALINGS IN THE SOFTWARE.
44 * XFree86 driver authors:
46 * Kevin E. Martin <martin@xfree86.org>
47 * Rickard E. Faith <faith@valinux.com>
48 * Alan Hourihane <alanh@fairlite.demon.co.uk>
53 #define RADEON_VERSION "0.2.0"
55 #include <linux/module.h>
56 #include <linux/moduleparam.h>
57 #include <linux/kernel.h>
58 #include <linux/errno.h>
59 #include <linux/string.h>
61 #include <linux/slab.h>
62 #include <linux/delay.h>
63 #include <linux/time.h>
65 #include <linux/ioport.h>
66 #include <linux/init.h>
67 #include <linux/pci.h>
68 #include <linux/vmalloc.h>
69 #include <linux/device.h>
72 #include <asm/uaccess.h>
76 #include <asm/pci-bridge.h>
77 #include "../macmodes.h"
79 #ifdef CONFIG_BOOTX_TEXT
80 #include <asm/btext.h>
83 #endif /* CONFIG_PPC_OF */
89 #include <video/radeon.h>
90 #include <linux/radeonfb.h>
92 #include "../edid.h" // MOVE THAT TO include/video
96 #define MAX_MAPPED_VRAM (2048*2048*4)
97 #define MIN_MAPPED_VRAM (1024*768*1)
99 #define CHIP_DEF(id, family, flags) \
100 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
102 static struct pci_device_id radeonfb_pci_table[] = {
104 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
105 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
107 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
108 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
109 CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2),
110 /* Radeon IGP320M (U1) */
111 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
112 /* Radeon IGP320 (A3) */
113 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
114 /* IGP330M/340M/350M (U2) */
115 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
116 /* IGP330/340/350 (A4) */
117 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
118 /* Mobility 7000 IGP */
119 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
121 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
123 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
124 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
126 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
128 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
130 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
132 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
133 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
135 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
136 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
138 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
139 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
140 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
141 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
143 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
144 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
145 /* Mobility 9100 IGP (U3) */
146 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
147 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
149 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
150 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
151 /* Mobility 9200 (M9+) */
152 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
153 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
155 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
156 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
157 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
158 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
160 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
161 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
162 /* 9600TX / FireGL Z1 */
163 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
164 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
165 /* 9700/9500/Pro/FireGL X1 */
166 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
167 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
168 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
169 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
170 /* Mobility M10/M11 */
171 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
172 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
173 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
174 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
175 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
176 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
178 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
179 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
180 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
181 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
182 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
183 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
184 /* 9800/Pro/FileGL X2 */
185 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
186 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
187 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
188 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
189 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
190 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
191 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
192 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
194 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
195 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
196 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
197 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
198 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
199 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
200 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
201 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
202 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
203 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
204 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
205 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
206 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
207 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
208 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
209 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
210 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
211 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
212 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
213 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
214 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
215 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
216 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
217 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
218 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
219 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
220 /* Original Radeon/7200 */
221 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
222 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
223 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
224 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
227 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
236 /* these common regs are cleared before mode setting so they do not
237 * interfere with anything
239 static reg_val common_regs[] = {
241 { OVR_WID_LEFT_RIGHT, 0 },
242 { OVR_WID_TOP_BOTTOM, 0 },
243 { OV0_SCALE_CNTL, 0 },
248 { CAP0_TRIG_CNTL, 0 },
249 { CAP1_TRIG_CNTL, 0 },
256 static char *mode_option;
257 static char *monitor_layout;
258 static int noaccel = 0;
259 static int default_dynclk = -2;
260 static int nomodeset = 0;
261 static int ignore_edid = 0;
262 static int mirror = 0;
263 static int panel_yres = 0;
264 static int force_dfp = 0;
265 static int force_measure_pll = 0;
267 static int nomtrr = 0;
269 static int force_sleep;
270 static int ignore_devlist;
276 static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
278 if (!rinfo->bios_seg)
280 pci_unmap_rom(dev, rinfo->bios_seg);
283 static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
290 /* If this is a primary card, there is a shadow copy of the
291 * ROM somewhere in the first meg. We will just ignore the copy
292 * and use the ROM directly.
295 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
297 temp = INREG(MPP_TB_CONFIG);
300 OUTREG(MPP_TB_CONFIG, temp);
301 temp = INREG(MPP_TB_CONFIG);
303 rom = pci_map_rom(dev, &rom_size);
305 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
306 pci_name(rinfo->pdev));
310 rinfo->bios_seg = rom;
312 /* Very simple test to make sure it appeared */
313 if (BIOS_IN16(0) != 0xaa55) {
314 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
315 "should be 0xaa55\n",
316 pci_name(rinfo->pdev), BIOS_IN16(0));
319 /* Look for the PCI data to check the ROM type */
320 dptr = BIOS_IN16(0x18);
322 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
323 * for now, until I've verified this works everywhere. The goal here is more
324 * to phase out Open Firmware images.
326 * Currently, we only look at the first PCI data, we could iteratre and deal with
327 * them all, and we should use fb_bios_start relative to start of image and not
328 * relative start of ROM, but so far, I never found a dual-image ATI card
331 * u32 signature; + 0x00
334 * u16 reserved_1; + 0x08
336 * u8 drevision; + 0x0c
337 * u8 class_hi; + 0x0d
338 * u16 class_lo; + 0x0e
340 * u16 irevision; + 0x12
342 * u8 indicator; + 0x15
343 * u16 reserved_2; + 0x16
346 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
347 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
348 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
351 rom_type = BIOS_IN8(dptr + 0x14);
354 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
357 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
360 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
363 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
367 /* Locate the flat panel infos, do some sanity checking !!! */
368 rinfo->fp_bios_start = BIOS_IN16(0x48);
372 rinfo->bios_seg = NULL;
373 radeon_unmap_ROM(rinfo, dev);
378 static int __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
380 /* I simplified this code as we used to miss the signatures in
381 * a lot of case. It's now closer to XFree, we just don't check
382 * for signatures at all... Something better will have to be done
383 * if we end up having conflicts
386 void __iomem *rom_base = NULL;
388 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
389 rom_base = ioremap(segstart, 0x10000);
390 if (rom_base == NULL)
392 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
397 if (rom_base == NULL)
400 /* Locate the flat panel infos, do some sanity checking !!! */
401 rinfo->bios_seg = rom_base;
402 rinfo->fp_bios_start = BIOS_IN16(0x48);
410 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
411 * tree. Hopefully, ATI OF driver is kind enough to fill these
413 static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
415 struct device_node *dp = rinfo->of_node;
420 val = get_property(dp, "ATY,RefCLK", NULL);
422 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
426 rinfo->pll.ref_clk = (*val) / 10;
428 val = get_property(dp, "ATY,SCLK", NULL);
430 rinfo->pll.sclk = (*val) / 10;
432 val = get_property(dp, "ATY,MCLK", NULL);
434 rinfo->pll.mclk = (*val) / 10;
438 #endif /* CONFIG_PPC_OF */
441 * Read PLL infos from chip registers
443 static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
445 unsigned char ppll_div_sel;
447 unsigned sclk, mclk, tmp, ref_div;
448 int hTotal, vTotal, num, denom, m, n;
449 unsigned long long hz, vclk;
451 struct timeval start_tv, stop_tv;
452 long total_secs, total_usecs;
455 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
459 /* Flush PCI buffers ? */
460 tmp = INREG16(DEVICE_ID);
464 for(i=0; i<1000000; i++)
465 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
468 do_gettimeofday(&start_tv);
470 for(i=0; i<1000000; i++)
471 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
474 for(i=0; i<1000000; i++)
475 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
478 do_gettimeofday(&stop_tv);
482 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
485 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
486 total_usecs += total_secs * 1000000;
488 total_usecs = -total_usecs;
489 hz = 1000000/total_usecs;
491 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
492 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
493 vclk = (long long)hTotal * (long long)vTotal * hz;
495 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
502 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
503 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
508 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
509 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
515 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
516 radeon_pll_errata_after_index(rinfo);
518 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
519 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
524 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
546 do_div(vclk, 1000 * num);
549 if ((xtal > 26900) && (xtal < 27100))
551 else if ((xtal > 14200) && (xtal < 14400))
553 else if ((xtal > 29400) && (xtal < 29600))
556 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
560 tmp = INPLL(M_SPLL_REF_FB_DIV);
561 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
563 Ns = (tmp & 0xff0000) >> 16;
564 Nm = (tmp & 0xff00) >> 8;
566 sclk = round_div((2 * Ns * xtal), (2 * M));
567 mclk = round_div((2 * Nm * xtal), (2 * M));
569 /* we're done, hopefully these are sane values */
570 rinfo->pll.ref_clk = xtal;
571 rinfo->pll.ref_div = ref_div;
572 rinfo->pll.sclk = sclk;
573 rinfo->pll.mclk = mclk;
579 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
581 static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
584 * In the case nothing works, these are defaults; they are mostly
585 * incomplete, however. It does provide ppll_max and _min values
586 * even for most other methods, however.
588 switch (rinfo->chipset) {
589 case PCI_DEVICE_ID_ATI_RADEON_QW:
590 case PCI_DEVICE_ID_ATI_RADEON_QX:
591 rinfo->pll.ppll_max = 35000;
592 rinfo->pll.ppll_min = 12000;
593 rinfo->pll.mclk = 23000;
594 rinfo->pll.sclk = 23000;
595 rinfo->pll.ref_clk = 2700;
597 case PCI_DEVICE_ID_ATI_RADEON_QL:
598 case PCI_DEVICE_ID_ATI_RADEON_QN:
599 case PCI_DEVICE_ID_ATI_RADEON_QO:
600 case PCI_DEVICE_ID_ATI_RADEON_Ql:
601 case PCI_DEVICE_ID_ATI_RADEON_BB:
602 rinfo->pll.ppll_max = 35000;
603 rinfo->pll.ppll_min = 12000;
604 rinfo->pll.mclk = 27500;
605 rinfo->pll.sclk = 27500;
606 rinfo->pll.ref_clk = 2700;
608 case PCI_DEVICE_ID_ATI_RADEON_Id:
609 case PCI_DEVICE_ID_ATI_RADEON_Ie:
610 case PCI_DEVICE_ID_ATI_RADEON_If:
611 case PCI_DEVICE_ID_ATI_RADEON_Ig:
612 rinfo->pll.ppll_max = 35000;
613 rinfo->pll.ppll_min = 12000;
614 rinfo->pll.mclk = 25000;
615 rinfo->pll.sclk = 25000;
616 rinfo->pll.ref_clk = 2700;
618 case PCI_DEVICE_ID_ATI_RADEON_ND:
619 case PCI_DEVICE_ID_ATI_RADEON_NE:
620 case PCI_DEVICE_ID_ATI_RADEON_NF:
621 case PCI_DEVICE_ID_ATI_RADEON_NG:
622 rinfo->pll.ppll_max = 40000;
623 rinfo->pll.ppll_min = 20000;
624 rinfo->pll.mclk = 27000;
625 rinfo->pll.sclk = 27000;
626 rinfo->pll.ref_clk = 2700;
628 case PCI_DEVICE_ID_ATI_RADEON_QD:
629 case PCI_DEVICE_ID_ATI_RADEON_QE:
630 case PCI_DEVICE_ID_ATI_RADEON_QF:
631 case PCI_DEVICE_ID_ATI_RADEON_QG:
633 rinfo->pll.ppll_max = 35000;
634 rinfo->pll.ppll_min = 12000;
635 rinfo->pll.mclk = 16600;
636 rinfo->pll.sclk = 16600;
637 rinfo->pll.ref_clk = 2700;
640 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
645 * Retrieve PLL infos from Open Firmware first
647 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
648 printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n");
651 #endif /* CONFIG_PPC_OF */
654 * Check out if we have an X86 which gave us some PLL informations
655 * and if yes, retrieve them
657 if (!force_measure_pll && rinfo->bios_seg) {
658 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
660 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
661 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
662 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
663 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
664 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
665 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
667 printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
672 * We didn't get PLL parameters from either OF or BIOS, we try to
675 if (radeon_probe_pll_params(rinfo) == 0) {
676 printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n");
681 * Fall back to already-set defaults...
683 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
687 * Some methods fail to retrieve SCLK and MCLK values, we apply default
688 * settings in this case (200Mhz). If that really happne often, we could
689 * fetch from registers instead...
691 if (rinfo->pll.mclk == 0)
692 rinfo->pll.mclk = 20000;
693 if (rinfo->pll.sclk == 0)
694 rinfo->pll.sclk = 20000;
696 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
697 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
699 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
700 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
701 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
704 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
706 struct radeonfb_info *rinfo = info->par;
707 struct fb_var_screeninfo v;
711 if (radeon_match_mode(rinfo, &v, var))
714 switch (v.bits_per_pixel) {
716 v.bits_per_pixel = 8;
719 v.bits_per_pixel = 16;
722 #if 0 /* Doesn't seem to work */
723 v.bits_per_pixel = 24;
728 v.bits_per_pixel = 32;
734 switch (var_to_depth(&v)) {
737 v.red.offset = v.green.offset = v.blue.offset = 0;
738 v.red.length = v.green.length = v.blue.length = 8;
739 v.transp.offset = v.transp.length = 0;
747 v.red.length = v.green.length = v.blue.length = 5;
748 v.transp.offset = v.transp.length = 0;
759 v.transp.offset = v.transp.length = 0;
767 v.red.length = v.blue.length = v.green.length = 8;
768 v.transp.offset = v.transp.length = 0;
776 v.red.length = v.blue.length = v.green.length = 8;
777 v.transp.offset = 24;
781 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
782 var->xres, var->yres, var->bits_per_pixel);
786 if (v.yres_virtual < v.yres)
787 v.yres_virtual = v.yres;
788 if (v.xres_virtual < v.xres)
789 v.xres_virtual = v.xres;
792 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
793 * with some panels, though I don't quite like this solution
795 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
796 v.xres_virtual = v.xres_virtual & ~7ul;
798 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
800 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
803 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
806 if (v.xres_virtual < v.xres)
807 v.xres = v.xres_virtual;
814 if (v.xoffset > v.xres_virtual - v.xres)
815 v.xoffset = v.xres_virtual - v.xres - 1;
817 if (v.yoffset > v.yres_virtual - v.yres)
818 v.yoffset = v.yres_virtual - v.yres - 1;
820 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
821 v.transp.offset = v.transp.length =
822 v.transp.msb_right = 0;
824 memcpy(var, &v, sizeof(v));
830 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
831 struct fb_info *info)
833 struct radeonfb_info *rinfo = info->par;
835 if ((var->xoffset + var->xres > var->xres_virtual)
836 || (var->yoffset + var->yres > var->yres_virtual))
843 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
844 * var->bits_per_pixel / 8) & ~7);
849 static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
852 struct radeonfb_info *rinfo = info->par;
859 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
860 * and do something better using 2nd CRTC instead of just hackish
861 * routing to second output
863 case FBIO_RADEON_SET_MIRROR:
864 if (!rinfo->is_mobility)
867 rc = get_user(value, (__u32 __user *)arg);
874 tmp = INREG(LVDS_GEN_CNTL);
876 tmp |= (LVDS_ON | LVDS_BLON);
878 tmp = INREG(LVDS_GEN_CNTL);
880 tmp &= ~(LVDS_ON | LVDS_BLON);
883 OUTREG(LVDS_GEN_CNTL, tmp);
886 tmp = INREG(CRTC_EXT_CNTL);
891 tmp = INREG(CRTC_EXT_CNTL);
897 OUTREG(CRTC_EXT_CNTL, tmp);
900 case FBIO_RADEON_GET_MIRROR:
901 if (!rinfo->is_mobility)
904 tmp = INREG(LVDS_GEN_CNTL);
905 if ((LVDS_ON | LVDS_BLON) & tmp)
908 tmp = INREG(CRTC_EXT_CNTL);
909 if (CRTC_CRT_ON & tmp)
912 return put_user(value, (__u32 __user *)arg);
921 int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
927 if (rinfo->lock_blank)
930 radeon_engine_idle();
932 val = INREG(CRTC_EXT_CNTL);
933 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
936 case FB_BLANK_VSYNC_SUSPEND:
937 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
939 case FB_BLANK_HSYNC_SUSPEND:
940 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
942 case FB_BLANK_POWERDOWN:
943 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
946 case FB_BLANK_NORMAL:
947 val |= CRTC_DISPLAY_DIS;
949 case FB_BLANK_UNBLANK:
953 OUTREG(CRTC_EXT_CNTL, val);
956 switch (rinfo->mon1_type) {
959 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
960 ~(FP_FPON | FP_TMDS_EN));
962 if (mode_switch || blank == FB_BLANK_NORMAL)
964 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
968 del_timer_sync(&rinfo->lvds_timer);
969 val = INREG(LVDS_GEN_CNTL);
971 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
972 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
973 & (LVDS_DIGON | LVDS_BL_MOD_EN));
974 if ((val ^ target_val) == LVDS_DISPLAY_DIS)
975 OUTREG(LVDS_GEN_CNTL, target_val);
976 else if ((val ^ target_val) != 0) {
977 OUTREG(LVDS_GEN_CNTL, target_val
978 & ~(LVDS_ON | LVDS_BL_MOD_EN));
979 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
980 rinfo->init_state.lvds_gen_cntl |=
981 target_val & LVDS_STATE_MASK;
983 radeon_msleep(rinfo->panel_info.pwr_delay);
984 OUTREG(LVDS_GEN_CNTL, target_val);
987 rinfo->pending_lvds_gen_cntl = target_val;
988 mod_timer(&rinfo->lvds_timer,
990 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
994 val |= LVDS_DISPLAY_DIS;
995 OUTREG(LVDS_GEN_CNTL, val);
997 /* We don't do a full switch-off on a simple mode switch */
998 if (mode_switch || blank == FB_BLANK_NORMAL)
1001 /* Asic bug, when turning off LVDS_ON, we have to make sure
1002 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1004 tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1005 if (rinfo->is_mobility || rinfo->is_IGP)
1006 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1007 val &= ~(LVDS_BL_MOD_EN);
1008 OUTREG(LVDS_GEN_CNTL, val);
1010 val &= ~(LVDS_ON | LVDS_EN);
1011 OUTREG(LVDS_GEN_CNTL, val);
1013 rinfo->pending_lvds_gen_cntl = val;
1014 mod_timer(&rinfo->lvds_timer,
1016 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1017 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1018 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1019 if (rinfo->is_mobility || rinfo->is_IGP)
1020 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1024 // todo: powerdown DAC
1029 /* let fbcon do a soft blank for us */
1030 return (blank == FB_BLANK_NORMAL) ? -EINVAL : 0;
1033 static int radeonfb_blank (int blank, struct fb_info *info)
1035 struct radeonfb_info *rinfo = info->par;
1040 return radeon_screen_blank(rinfo, blank, 0);
1043 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1044 unsigned blue, unsigned transp,
1045 struct radeonfb_info *rinfo)
1057 rinfo->palette[regno].red = red;
1058 rinfo->palette[regno].green = green;
1059 rinfo->palette[regno].blue = blue;
1064 if (!rinfo->asleep) {
1065 radeon_fifo_wait(9);
1067 if (rinfo->bpp == 16) {
1070 if (rinfo->depth == 16 && regno > 63)
1072 if (rinfo->depth == 15 && regno > 31)
1075 /* For 565, the green component is mixed one order
1078 if (rinfo->depth == 16) {
1079 OUTREG(PALETTE_INDEX, pindex>>1);
1080 OUTREG(PALETTE_DATA,
1081 (rinfo->palette[regno>>1].red << 16) |
1083 (rinfo->palette[regno>>1].blue));
1084 green = rinfo->palette[regno<<1].green;
1088 if (rinfo->depth != 16 || regno < 32) {
1089 OUTREG(PALETTE_INDEX, pindex);
1090 OUTREG(PALETTE_DATA, (red << 16) |
1091 (green << 8) | blue);
1095 u32 *pal = rinfo->info->pseudo_palette;
1096 switch (rinfo->depth) {
1098 pal[regno] = (regno << 10) | (regno << 5) | regno;
1101 pal[regno] = (regno << 11) | (regno << 5) | regno;
1104 pal[regno] = (regno << 16) | (regno << 8) | regno;
1107 i = (regno << 8) | regno;
1108 pal[regno] = (i << 16) | i;
1115 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1116 unsigned blue, unsigned transp,
1117 struct fb_info *info)
1119 struct radeonfb_info *rinfo = info->par;
1120 u32 dac_cntl2, vclk_cntl = 0;
1123 if (!rinfo->asleep) {
1124 if (rinfo->is_mobility) {
1125 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1126 OUTPLL(VCLK_ECP_CNTL,
1127 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1130 /* Make sure we are on first palette */
1131 if (rinfo->has_CRTC2) {
1132 dac_cntl2 = INREG(DAC_CNTL2);
1133 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1134 OUTREG(DAC_CNTL2, dac_cntl2);
1138 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1140 if (!rinfo->asleep && rinfo->is_mobility)
1141 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1146 static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1148 struct radeonfb_info *rinfo = info->par;
1149 u16 *red, *green, *blue, *transp;
1150 u32 dac_cntl2, vclk_cntl = 0;
1151 int i, start, rc = 0;
1153 if (!rinfo->asleep) {
1154 if (rinfo->is_mobility) {
1155 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1156 OUTPLL(VCLK_ECP_CNTL,
1157 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1160 /* Make sure we are on first palette */
1161 if (rinfo->has_CRTC2) {
1162 dac_cntl2 = INREG(DAC_CNTL2);
1163 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1164 OUTREG(DAC_CNTL2, dac_cntl2);
1169 green = cmap->green;
1171 transp = cmap->transp;
1172 start = cmap->start;
1174 for (i = 0; i < cmap->len; i++) {
1175 u_int hred, hgreen, hblue, htransp = 0xffff;
1181 htransp = *transp++;
1182 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
1188 if (!rinfo->asleep && rinfo->is_mobility)
1189 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1194 static void radeon_save_state (struct radeonfb_info *rinfo,
1195 struct radeon_regs *save)
1198 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1199 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1200 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1201 save->dac_cntl = INREG(DAC_CNTL);
1202 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1203 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1204 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1205 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1206 save->crtc_pitch = INREG(CRTC_PITCH);
1207 save->surface_cntl = INREG(SURFACE_CNTL);
1210 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1211 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1212 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1213 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1214 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1215 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1216 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1217 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1218 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1219 save->tmds_crc = INREG(TMDS_CRC);
1220 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1221 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1224 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1225 radeon_pll_errata_after_index(rinfo);
1226 save->ppll_div_3 = INPLL(PPLL_DIV_3);
1227 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1231 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1235 radeon_fifo_wait(20);
1237 /* Workaround from XFree */
1238 if (rinfo->is_mobility) {
1239 /* A temporal workaround for the occational blanking on certain laptop
1240 * panels. This appears to related to the PLL divider registers
1241 * (fail to lock?). It occurs even when all dividers are the same
1242 * with their old settings. In this case we really don't need to
1243 * fiddle with PLL registers. By doing this we can avoid the blanking
1244 * problem with some panels.
1246 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1247 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1248 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1249 /* We still have to force a switch to selected PPLL div thanks to
1250 * an XFree86 driver bug which will switch it away in some cases
1251 * even when using UseFDev */
1252 OUTREGP(CLOCK_CNTL_INDEX,
1253 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1254 ~PPLL_DIV_SEL_MASK);
1255 radeon_pll_errata_after_index(rinfo);
1256 radeon_pll_errata_after_data(rinfo);
1261 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1262 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1264 /* Reset PPLL & enable atomic update */
1266 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1267 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1269 /* Switch to selected PPLL divider */
1270 OUTREGP(CLOCK_CNTL_INDEX,
1271 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1272 ~PPLL_DIV_SEL_MASK);
1273 radeon_pll_errata_after_index(rinfo);
1274 radeon_pll_errata_after_data(rinfo);
1276 /* Set PPLL ref. div */
1277 if (rinfo->family == CHIP_FAMILY_R300 ||
1278 rinfo->family == CHIP_FAMILY_RS300 ||
1279 rinfo->family == CHIP_FAMILY_R350 ||
1280 rinfo->family == CHIP_FAMILY_RV350) {
1281 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1282 /* When restoring console mode, use saved PPLL_REF_DIV
1285 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1287 /* R300 uses ref_div_acc field as real ref divider */
1288 OUTPLLP(PPLL_REF_DIV,
1289 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1290 ~R300_PPLL_REF_DIV_ACC_MASK);
1293 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1295 /* Set PPLL divider 3 & post divider*/
1296 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1297 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1300 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1302 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1304 /* Wait read update complete */
1305 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1306 the cause yet, but this workaround will mask the problem for now.
1307 Other chips usually will pass at the very first test, so the
1308 workaround shouldn't have any effect on them. */
1309 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1312 OUTPLL(HTOTAL_CNTL, 0);
1314 /* Clear reset & atomic update */
1315 OUTPLLP(PPLL_CNTL, 0,
1316 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1318 /* We may want some locking ... oh well */
1321 /* Switch back VCLK source to PPLL */
1322 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1326 * Timer function for delayed LVDS panel power up/down
1328 static void radeon_lvds_timer_func(unsigned long data)
1330 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1332 radeon_engine_idle();
1334 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1338 * Apply a video mode. This will apply the whole register set, including
1339 * the PLL registers, to the card
1341 void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1345 int primary_mon = PRIMARY_MONITOR(rinfo);
1351 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1353 radeon_fifo_wait(31);
1354 for (i=0; i<10; i++)
1355 OUTREG(common_regs[i].reg, common_regs[i].val);
1357 /* Apply surface registers */
1358 for (i=0; i<8; i++) {
1359 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1360 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1361 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1364 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1365 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1366 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1367 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1368 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1369 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1370 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1371 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1372 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1373 OUTREG(CRTC_OFFSET, 0);
1374 OUTREG(CRTC_OFFSET_CNTL, 0);
1375 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1376 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1378 radeon_write_pll_regs(rinfo, mode);
1380 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1381 radeon_fifo_wait(10);
1382 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1383 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1384 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1385 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1386 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1387 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1388 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1389 OUTREG(TMDS_CRC, mode->tmds_crc);
1390 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1394 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1396 radeon_fifo_wait(2);
1397 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1403 * Calculate the PLL values for a given mode
1405 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1423 int fb_div, pll_output_freq = 0;
1426 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1427 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1428 * recent than an r(v)100...
1431 /* XXX I had reports of flicker happening with the cinema display
1432 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1433 * this case. This could just be a bandwidth calculation issue, I
1434 * haven't implemented the bandwidth code yet, but in the meantime,
1435 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1436 * I haven't seen a case were were absolutely needed an odd PLL
1437 * divider. I'll find a better fix once I have more infos on the
1438 * real cause of the problem.
1440 while (rinfo->has_CRTC2) {
1441 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1442 u32 disp_output_cntl;
1445 /* FP2 path not enabled */
1446 if ((fp2_gen_cntl & FP2_ON) == 0)
1448 /* Not all chip revs have the same format for this register,
1449 * extract the source selection
1451 if (rinfo->family == CHIP_FAMILY_R200 ||
1452 rinfo->family == CHIP_FAMILY_R300 ||
1453 rinfo->family == CHIP_FAMILY_R350 ||
1454 rinfo->family == CHIP_FAMILY_RV350) {
1455 source = (fp2_gen_cntl >> 10) & 0x3;
1456 /* sourced from transform unit, check for transform unit
1460 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1461 source = (disp_output_cntl >> 12) & 0x3;
1464 source = (fp2_gen_cntl >> 13) & 0x1;
1465 /* sourced from CRTC2 -> exit */
1469 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1476 if (freq > rinfo->pll.ppll_max)
1477 freq = rinfo->pll.ppll_max;
1478 if (freq*12 < rinfo->pll.ppll_min)
1479 freq = rinfo->pll.ppll_min / 12;
1480 RTRACE("freq = %lu, PLL min = %u, PLL max = %u\n",
1481 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1483 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1484 pll_output_freq = post_div->divider * freq;
1485 /* If we output to the DVO port (external TMDS), we don't allow an
1486 * odd PLL divider as those aren't supported on this path
1488 if (uses_dvo && (post_div->divider & 1))
1490 if (pll_output_freq >= rinfo->pll.ppll_min &&
1491 pll_output_freq <= rinfo->pll.ppll_max)
1495 /* If we fall through the bottom, try the "default value"
1496 given by the terminal post_div->bitvalue */
1497 if ( !post_div->divider ) {
1498 post_div = &post_divs[post_div->bitvalue];
1499 pll_output_freq = post_div->divider * freq;
1501 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1502 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1505 /* If we fall through the bottom, try the "default value"
1506 given by the terminal post_div->bitvalue */
1507 if ( !post_div->divider ) {
1508 post_div = &post_divs[post_div->bitvalue];
1509 pll_output_freq = post_div->divider * freq;
1511 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1512 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1515 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1516 rinfo->pll.ref_clk);
1517 regs->ppll_ref_div = rinfo->pll.ref_div;
1518 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1520 RTRACE("post div = 0x%x\n", post_div->bitvalue);
1521 RTRACE("fb_div = 0x%x\n", fb_div);
1522 RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1525 static int radeonfb_set_par(struct fb_info *info)
1527 struct radeonfb_info *rinfo = info->par;
1528 struct fb_var_screeninfo *mode = &info->var;
1529 struct radeon_regs *newmode;
1530 int hTotal, vTotal, hSyncStart, hSyncEnd,
1531 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1532 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1533 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1534 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1538 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1539 int primary_mon = PRIMARY_MONITOR(rinfo);
1540 int depth = var_to_depth(mode);
1543 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1547 /* We always want engine to be idle on a mode switch, even
1548 * if we won't actually change the mode
1550 radeon_engine_idle();
1552 hSyncStart = mode->xres + mode->right_margin;
1553 hSyncEnd = hSyncStart + mode->hsync_len;
1554 hTotal = hSyncEnd + mode->left_margin;
1556 vSyncStart = mode->yres + mode->lower_margin;
1557 vSyncEnd = vSyncStart + mode->vsync_len;
1558 vTotal = vSyncEnd + mode->upper_margin;
1559 pixClock = mode->pixclock;
1562 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1563 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1565 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1566 if (rinfo->panel_info.xres < mode->xres)
1567 mode->xres = rinfo->panel_info.xres;
1568 if (rinfo->panel_info.yres < mode->yres)
1569 mode->yres = rinfo->panel_info.yres;
1571 hTotal = mode->xres + rinfo->panel_info.hblank;
1572 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1573 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1575 vTotal = mode->yres + rinfo->panel_info.vblank;
1576 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1577 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1579 h_sync_pol = !rinfo->panel_info.hAct_high;
1580 v_sync_pol = !rinfo->panel_info.vAct_high;
1582 pixClock = 100000000 / rinfo->panel_info.clock;
1584 if (rinfo->panel_info.use_bios_dividers) {
1586 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1587 (rinfo->panel_info.post_divider << 16);
1588 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1591 dotClock = 1000000000 / pixClock;
1592 freq = dotClock / 10; /* x100 */
1594 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1595 hSyncStart, hSyncEnd, hTotal);
1596 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1597 vSyncStart, vSyncEnd, vTotal);
1599 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1600 vsync_wid = vSyncEnd - vSyncStart;
1603 else if (hsync_wid > 0x3f) /* max */
1608 else if (vsync_wid > 0x1f) /* max */
1611 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1612 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1614 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1616 format = radeon_get_dstbpp(depth);
1617 bytpp = mode->bits_per_pixel >> 3;
1619 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1620 hsync_fudge = hsync_fudge_fp[format-1];
1622 hsync_fudge = hsync_adj_tab[format-1];
1624 hsync_start = hSyncStart - 8 + hsync_fudge;
1626 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1629 /* Clear auto-center etc... */
1630 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1631 newmode->crtc_more_cntl &= 0xfffffff0;
1633 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1634 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1636 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1638 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1641 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1645 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1648 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1649 (((mode->xres / 8) - 1) << 16));
1651 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1652 (hsync_wid << 16) | (h_sync_pol << 23));
1654 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1655 ((mode->yres - 1) << 16);
1657 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1658 (vsync_wid << 16) | (v_sync_pol << 23));
1660 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1661 /* We first calculate the engine pitch */
1662 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1665 /* Then, re-multiply it to get the CRTC pitch */
1666 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1668 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1670 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1673 * It looks like recent chips have a problem with SURFACE_CNTL,
1674 * setting SURF_TRANSLATION_DIS completely disables the
1675 * swapper as well, so we leave it unset now.
1677 newmode->surface_cntl = 0;
1679 #if defined(__BIG_ENDIAN)
1681 /* Setup swapping on both apertures, though we currently
1682 * only use aperture 0, enabling swapper on aperture 1
1685 switch (mode->bits_per_pixel) {
1687 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1688 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1692 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1693 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1698 /* Clear surface registers */
1699 for (i=0; i<8; i++) {
1700 newmode->surf_lower_bound[i] = 0;
1701 newmode->surf_upper_bound[i] = 0x1f;
1702 newmode->surf_info[i] = 0;
1705 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1706 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1707 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1708 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1710 rinfo->bpp = mode->bits_per_pixel;
1711 rinfo->depth = depth;
1713 RTRACE("pixclock = %lu\n", (unsigned long)pixClock);
1714 RTRACE("freq = %lu\n", (unsigned long)freq);
1716 /* We use PPLL_DIV_3 */
1717 newmode->clk_cntl_index = 0x300;
1719 /* Calculate PPLL value if necessary */
1721 radeon_calc_pll_regs(rinfo, newmode, freq);
1723 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1725 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1726 unsigned int hRatio, vRatio;
1728 if (mode->xres > rinfo->panel_info.xres)
1729 mode->xres = rinfo->panel_info.xres;
1730 if (mode->yres > rinfo->panel_info.yres)
1731 mode->yres = rinfo->panel_info.yres;
1733 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1734 << HORZ_PANEL_SHIFT);
1735 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1736 << VERT_PANEL_SHIFT);
1738 if (mode->xres != rinfo->panel_info.xres) {
1739 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1740 rinfo->panel_info.xres);
1741 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1742 (newmode->fp_horz_stretch &
1743 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1744 HORZ_AUTO_RATIO_INC)));
1745 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1746 HORZ_STRETCH_ENABLE);
1749 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1751 if (mode->yres != rinfo->panel_info.yres) {
1752 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1753 rinfo->panel_info.yres);
1754 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1755 (newmode->fp_vert_stretch &
1756 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1757 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1758 VERT_STRETCH_ENABLE);
1761 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1763 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1765 FP_RMX_HVSYNC_CONTROL_EN |
1770 FP_CRTC_USE_SHADOW_VEND |
1773 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1774 FP_CRTC_DONT_SHADOW_HEND |
1777 if (IS_R300_VARIANT(rinfo) ||
1778 (rinfo->family == CHIP_FAMILY_R200)) {
1779 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1781 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1783 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1785 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1787 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1788 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1789 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1790 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1792 if (primary_mon == MT_LCD) {
1793 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1794 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1797 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1798 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1799 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1800 if (IS_R300_VARIANT(rinfo) ||
1801 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1802 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1804 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1805 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1808 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1809 (((mode->xres / 8) - 1) << 16));
1810 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1811 ((mode->yres - 1) << 16);
1812 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1813 (hsync_wid << 16) | (h_sync_pol << 23));
1814 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1815 (vsync_wid << 16) | (v_sync_pol << 23));
1819 if (!rinfo->asleep) {
1820 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1821 radeon_write_mode (rinfo, newmode, 0);
1822 /* (re)initialize the engine */
1823 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1824 radeonfb_engine_init (rinfo);
1827 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1828 info->fix.line_length = rinfo->pitch*64;
1830 info->fix.line_length = mode->xres_virtual
1831 * ((mode->bits_per_pixel + 1) / 8);
1832 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1833 : FB_VISUAL_DIRECTCOLOR;
1835 #ifdef CONFIG_BOOTX_TEXT
1836 /* Update debug text engine */
1837 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1838 rinfo->depth, info->fix.line_length);
1846 static struct fb_ops radeonfb_ops = {
1847 .owner = THIS_MODULE,
1848 .fb_check_var = radeonfb_check_var,
1849 .fb_set_par = radeonfb_set_par,
1850 .fb_setcolreg = radeonfb_setcolreg,
1851 .fb_setcmap = radeonfb_setcmap,
1852 .fb_pan_display = radeonfb_pan_display,
1853 .fb_blank = radeonfb_blank,
1854 .fb_ioctl = radeonfb_ioctl,
1855 .fb_sync = radeonfb_sync,
1856 .fb_fillrect = radeonfb_fillrect,
1857 .fb_copyarea = radeonfb_copyarea,
1858 .fb_imageblit = radeonfb_imageblit,
1862 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1864 struct fb_info *info = rinfo->info;
1867 info->pseudo_palette = rinfo->pseudo_palette;
1868 info->flags = FBINFO_DEFAULT
1869 | FBINFO_HWACCEL_COPYAREA
1870 | FBINFO_HWACCEL_FILLRECT
1871 | FBINFO_HWACCEL_XPAN
1872 | FBINFO_HWACCEL_YPAN;
1873 info->fbops = &radeonfb_ops;
1874 info->screen_base = rinfo->fb_base;
1875 info->screen_size = rinfo->mapped_vram;
1876 /* Fill fix common fields */
1877 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1878 info->fix.smem_start = rinfo->fb_base_phys;
1879 info->fix.smem_len = rinfo->video_ram;
1880 info->fix.type = FB_TYPE_PACKED_PIXELS;
1881 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1882 info->fix.xpanstep = 8;
1883 info->fix.ypanstep = 1;
1884 info->fix.ywrapstep = 0;
1885 info->fix.type_aux = 0;
1886 info->fix.mmio_start = rinfo->mmio_base_phys;
1887 info->fix.mmio_len = RADEON_REGSIZE;
1888 info->fix.accel = FB_ACCEL_ATI_RADEON;
1890 fb_alloc_cmap(&info->cmap, 256, 0);
1893 info->flags |= FBINFO_HWACCEL_DISABLED;
1899 * This reconfigure the card's internal memory map. In theory, we'd like
1900 * to setup the card's memory at the same address as it's PCI bus address,
1901 * and the AGP aperture right after that so that system RAM on 32 bits
1902 * machines at least, is directly accessible. However, doing so would
1903 * conflict with the current XFree drivers...
1904 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1905 * on the proper way to set this up and duplicate this here. In the meantime,
1906 * I put the card's memory at 0 in card space and AGP at some random high
1907 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1909 #ifdef CONFIG_PPC_OF
1910 #undef SET_MC_FB_FROM_APERTURE
1911 static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1913 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
1914 u32 save_crtc_ext_cntl;
1915 u32 aper_base, aper_size;
1918 /* First, we disable display to avoid interfering */
1919 if (rinfo->has_CRTC2) {
1920 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1921 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1923 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1924 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1926 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1927 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1930 aper_base = INREG(CONFIG_APER_0_BASE);
1931 aper_size = INREG(CONFIG_APER_SIZE);
1933 #ifdef SET_MC_FB_FROM_APERTURE
1934 /* Set framebuffer to be at the same address as set in PCI BAR */
1935 OUTREG(MC_FB_LOCATION,
1936 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1937 rinfo->fb_local_base = aper_base;
1939 OUTREG(MC_FB_LOCATION, 0x7fff0000);
1940 rinfo->fb_local_base = 0;
1942 agp_base = aper_base + aper_size;
1943 if (agp_base & 0xf0000000)
1944 agp_base = (aper_base | 0x0fffffff) + 1;
1946 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
1947 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
1948 * always the case on PPCs afaik.
1950 #ifdef SET_MC_FB_FROM_APERTURE
1951 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
1953 OUTREG(MC_AGP_LOCATION, 0xffffe000);
1956 /* Fixup the display base addresses & engine offsets while we
1959 #ifdef SET_MC_FB_FROM_APERTURE
1960 OUTREG(DISPLAY_BASE_ADDR, aper_base);
1961 if (rinfo->has_CRTC2)
1962 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
1963 OUTREG(OV0_BASE_ADDR, aper_base);
1965 OUTREG(DISPLAY_BASE_ADDR, 0);
1966 if (rinfo->has_CRTC2)
1967 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
1968 OUTREG(OV0_BASE_ADDR, 0);
1972 /* Restore display settings */
1973 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
1974 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
1975 if (rinfo->has_CRTC2)
1976 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
1978 RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
1980 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
1981 0xffff0000 | (agp_base >> 16));
1983 #endif /* CONFIG_PPC_OF */
1986 static void radeon_identify_vram(struct radeonfb_info *rinfo)
1990 /* framebuffer size */
1991 if ((rinfo->family == CHIP_FAMILY_RS100) ||
1992 (rinfo->family == CHIP_FAMILY_RS200) ||
1993 (rinfo->family == CHIP_FAMILY_RS300)) {
1994 u32 tom = INREG(NB_TOM);
1995 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
1997 radeon_fifo_wait(6);
1998 OUTREG(MC_FB_LOCATION, tom);
1999 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2000 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2001 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2003 /* This is supposed to fix the crtc2 noise problem. */
2004 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2006 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2007 (rinfo->family == CHIP_FAMILY_RS200)) {
2008 /* This is to workaround the asic bug for RMX, some versions
2009 of BIOS dosen't have this register initialized correctly.
2011 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2012 ~CRTC_H_CUTOFF_ACTIVE_EN);
2015 tmp = INREG(CONFIG_MEMSIZE);
2018 /* mem size is bits [28:0], mask off the rest */
2019 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2022 * Hack to get around some busted production M6's
2025 if (rinfo->video_ram == 0) {
2026 switch (rinfo->pdev->device) {
2027 case PCI_CHIP_RADEON_LY:
2028 case PCI_CHIP_RADEON_LZ:
2029 rinfo->video_ram = 8192 * 1024;
2038 * Now try to identify VRAM type
2040 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2041 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2042 rinfo->vram_ddr = 1;
2044 rinfo->vram_ddr = 0;
2046 tmp = INREG(MEM_CNTL);
2047 if (IS_R300_VARIANT(rinfo)) {
2048 tmp &= R300_MEM_NUM_CHANNELS_MASK;
2050 case 0: rinfo->vram_width = 64; break;
2051 case 1: rinfo->vram_width = 128; break;
2052 case 2: rinfo->vram_width = 256; break;
2053 default: rinfo->vram_width = 128; break;
2055 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2056 (rinfo->family == CHIP_FAMILY_RS100) ||
2057 (rinfo->family == CHIP_FAMILY_RS200)){
2058 if (tmp & RV100_MEM_HALF_MODE)
2059 rinfo->vram_width = 32;
2061 rinfo->vram_width = 64;
2063 if (tmp & MEM_NUM_CHANNELS_MASK)
2064 rinfo->vram_width = 128;
2066 rinfo->vram_width = 64;
2069 /* This may not be correct, as some cards can have half of channel disabled
2070 * ToDo: identify these cases
2073 RTRACE("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2074 pci_name(rinfo->pdev),
2075 rinfo->video_ram / 1024,
2076 rinfo->vram_ddr ? "DDR" : "SDRAM",
2084 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2086 if (off > EDID_LENGTH)
2089 if (off + count > EDID_LENGTH)
2090 count = EDID_LENGTH - off;
2092 memcpy(buf, edid + off, count);
2098 static ssize_t radeon_show_edid1(struct kobject *kobj, char *buf, loff_t off, size_t count)
2100 struct device *dev = container_of(kobj, struct device, kobj);
2101 struct pci_dev *pdev = to_pci_dev(dev);
2102 struct fb_info *info = pci_get_drvdata(pdev);
2103 struct radeonfb_info *rinfo = info->par;
2105 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2109 static ssize_t radeon_show_edid2(struct kobject *kobj, char *buf, loff_t off, size_t count)
2111 struct device *dev = container_of(kobj, struct device, kobj);
2112 struct pci_dev *pdev = to_pci_dev(dev);
2113 struct fb_info *info = pci_get_drvdata(pdev);
2114 struct radeonfb_info *rinfo = info->par;
2116 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2119 static struct bin_attribute edid1_attr = {
2122 .owner = THIS_MODULE,
2125 .size = EDID_LENGTH,
2126 .read = radeon_show_edid1,
2129 static struct bin_attribute edid2_attr = {
2132 .owner = THIS_MODULE,
2135 .size = EDID_LENGTH,
2136 .read = radeon_show_edid2,
2140 static int __devinit radeonfb_pci_register (struct pci_dev *pdev,
2141 const struct pci_device_id *ent)
2143 struct fb_info *info;
2144 struct radeonfb_info *rinfo;
2147 RTRACE("radeonfb_pci_register BEGIN\n");
2149 /* Enable device in PCI config */
2150 ret = pci_enable_device(pdev);
2152 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2157 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2159 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2168 spin_lock_init(&rinfo->reg_lock);
2169 init_timer(&rinfo->lvds_timer);
2170 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2171 rinfo->lvds_timer.data = (unsigned long)rinfo;
2173 strcpy(rinfo->name, "ATI Radeon XX ");
2174 rinfo->name[11] = ent->device >> 8;
2175 rinfo->name[12] = ent->device & 0xFF;
2176 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2177 rinfo->chipset = pdev->device;
2178 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2179 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2180 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2182 /* Set base addrs */
2183 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2184 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2186 /* request the mem regions */
2187 ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
2189 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
2190 pci_name(rinfo->pdev));
2191 goto err_release_fb;
2194 ret = pci_request_region(pdev, 2, "radeonfb mmio");
2196 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
2197 pci_name(rinfo->pdev));
2198 goto err_release_pci0;
2201 /* map the regions */
2202 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2203 if (!rinfo->mmio_base) {
2204 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
2205 pci_name(rinfo->pdev));
2207 goto err_release_pci2;
2210 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2216 if (rinfo->family == CHIP_FAMILY_R300 &&
2217 (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2219 rinfo->errata |= CHIP_ERRATA_R300_CG;
2221 if (rinfo->family == CHIP_FAMILY_RV200 ||
2222 rinfo->family == CHIP_FAMILY_RS200)
2223 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2225 if (rinfo->family == CHIP_FAMILY_RV100 ||
2226 rinfo->family == CHIP_FAMILY_RS100 ||
2227 rinfo->family == CHIP_FAMILY_RS200)
2228 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2230 #ifdef CONFIG_PPC_OF
2231 /* On PPC, we obtain the OF device-node pointer to the firmware
2232 * data for this chip
2234 rinfo->of_node = pci_device_to_OF_node(pdev);
2235 if (rinfo->of_node == NULL)
2236 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2237 pci_name(rinfo->pdev));
2239 /* On PPC, the firmware sets up a memory mapping that tends
2240 * to cause lockups when enabling the engine. We reconfigure
2241 * the card internal memory mappings properly
2243 fixup_memory_mappings(rinfo);
2244 #endif /* CONFIG_PPC_OF */
2246 /* Get VRAM size and type */
2247 radeon_identify_vram(rinfo);
2249 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2252 rinfo->fb_base = ioremap (rinfo->fb_base_phys,
2253 rinfo->mapped_vram);
2254 } while ( rinfo->fb_base == 0 &&
2255 ((rinfo->mapped_vram /=2) >= MIN_MAPPED_VRAM) );
2257 if (rinfo->fb_base == NULL) {
2258 printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2259 pci_name(rinfo->pdev));
2264 RTRACE("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2265 rinfo->mapped_vram/1024);
2268 * Map the BIOS ROM if any and retrieve PLL parameters from
2269 * the BIOS. We skip that on mobility chips as the real panel
2270 * values we need aren't in the ROM but in the BIOS image in
2271 * memory. This is definitely not the best meacnism though,
2272 * we really need the arch code to tell us which is the "primary"
2273 * video adapter to use the memory image (or better, the arch
2274 * should provide us a copy of the BIOS image to shield us from
2275 * archs who would store that elsewhere and/or could initialize
2276 * more than one adapter during boot).
2278 if (!rinfo->is_mobility)
2279 radeon_map_ROM(rinfo, pdev);
2282 * On x86, the primary display on laptop may have it's BIOS
2283 * ROM elsewhere, try to locate it at the legacy memory hole.
2284 * We probably need to make sure this is the primary display,
2285 * but that is difficult without some arch support.
2288 if (rinfo->bios_seg == NULL)
2289 radeon_find_mem_vbios(rinfo);
2292 /* If both above failed, try the BIOS ROM again for mobility
2295 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2296 radeon_map_ROM(rinfo, pdev);
2298 /* Get informations about the board's PLL */
2299 radeon_get_pllinfo(rinfo);
2301 #ifdef CONFIG_FB_RADEON_I2C
2302 /* Register I2C bus */
2303 radeon_create_i2c_busses(rinfo);
2306 /* set all the vital stuff */
2307 radeon_set_fbinfo (rinfo);
2309 /* Probe screen types */
2310 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2312 /* Build mode list, check out panel native model */
2313 radeon_check_modes(rinfo, mode_option);
2315 /* Register some sysfs stuff (should be done better) */
2316 if (rinfo->mon1_EDID)
2317 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2318 if (rinfo->mon2_EDID)
2319 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2321 /* save current mode regs before we switch into the new one
2322 * so we can restore this upon __exit
2324 radeon_save_state (rinfo, &rinfo->init_state);
2325 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2327 /* Setup Power Management capabilities */
2328 if (default_dynclk < -1) {
2329 /* -2 is special: means ON on mobility chips and do not
2332 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep);
2334 radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep);
2336 pci_set_drvdata(pdev, info);
2338 /* Register with fbdev layer */
2339 ret = register_framebuffer(info);
2341 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2342 pci_name(rinfo->pdev));
2347 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2349 MTRR_TYPE_WRCOMB, 1);
2352 radeonfb_bl_init(rinfo);
2354 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2356 if (rinfo->bios_seg)
2357 radeon_unmap_ROM(rinfo, pdev);
2358 RTRACE("radeonfb_pci_register END\n");
2362 iounmap(rinfo->fb_base);
2364 kfree(rinfo->mon1_EDID);
2365 kfree(rinfo->mon2_EDID);
2366 if (rinfo->mon1_modedb)
2367 fb_destroy_modedb(rinfo->mon1_modedb);
2368 fb_dealloc_cmap(&info->cmap);
2369 #ifdef CONFIG_FB_RADEON_I2C
2370 radeon_delete_i2c_busses(rinfo);
2372 if (rinfo->bios_seg)
2373 radeon_unmap_ROM(rinfo, pdev);
2374 iounmap(rinfo->mmio_base);
2376 pci_release_region(pdev, 2);
2378 pci_release_region(pdev, 0);
2380 framebuffer_release(info);
2388 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2390 struct fb_info *info = pci_get_drvdata(pdev);
2391 struct radeonfb_info *rinfo = info->par;
2396 radeonfb_pm_exit(rinfo);
2398 if (rinfo->mon1_EDID)
2399 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2400 if (rinfo->mon2_EDID)
2401 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2404 /* restore original state
2406 * Doesn't quite work yet, I suspect if we come from a legacy
2407 * VGA mode (or worse, text mode), we need to do some VGA black
2408 * magic here that I know nothing about. --BenH
2410 radeon_write_mode (rinfo, &rinfo->init_state, 1);
2413 del_timer_sync(&rinfo->lvds_timer);
2416 if (rinfo->mtrr_hdl >= 0)
2417 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2420 unregister_framebuffer(info);
2422 radeonfb_bl_exit(rinfo);
2424 iounmap(rinfo->mmio_base);
2425 iounmap(rinfo->fb_base);
2427 pci_release_region(pdev, 2);
2428 pci_release_region(pdev, 0);
2430 kfree(rinfo->mon1_EDID);
2431 kfree(rinfo->mon2_EDID);
2432 if (rinfo->mon1_modedb)
2433 fb_destroy_modedb(rinfo->mon1_modedb);
2434 #ifdef CONFIG_FB_RADEON_I2C
2435 radeon_delete_i2c_busses(rinfo);
2437 fb_dealloc_cmap(&info->cmap);
2438 framebuffer_release(info);
2442 static struct pci_driver radeonfb_driver = {
2444 .id_table = radeonfb_pci_table,
2445 .probe = radeonfb_pci_register,
2446 .remove = __devexit_p(radeonfb_pci_unregister),
2448 .suspend = radeonfb_pci_suspend,
2449 .resume = radeonfb_pci_resume,
2450 #endif /* CONFIG_PM */
2454 static int __init radeonfb_setup (char *options)
2458 if (!options || !*options)
2461 while ((this_opt = strsep (&options, ",")) != NULL) {
2465 if (!strncmp(this_opt, "noaccel", 7)) {
2467 } else if (!strncmp(this_opt, "mirror", 6)) {
2469 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2471 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2472 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2474 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2477 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2479 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2480 force_measure_pll = 1;
2481 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2483 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2484 } else if (!strncmp(this_opt, "force_sleep", 11)) {
2486 } else if (!strncmp(this_opt, "ignore_devlist", 14)) {
2490 mode_option = this_opt;
2496 static int __init radeonfb_init (void)
2499 char *option = NULL;
2501 if (fb_get_options("radeonfb", &option))
2503 radeonfb_setup(option);
2505 return pci_register_driver (&radeonfb_driver);
2509 static void __exit radeonfb_exit (void)
2511 pci_unregister_driver (&radeonfb_driver);
2514 module_init(radeonfb_init);
2515 module_exit(radeonfb_exit);
2517 MODULE_AUTHOR("Ani Joshi");
2518 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2519 MODULE_LICENSE("GPL");
2520 module_param(noaccel, bool, 0);
2521 module_param(default_dynclk, int, 0);
2522 MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2523 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2524 module_param(nomodeset, bool, 0);
2525 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2526 module_param(mirror, bool, 0);
2527 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2528 module_param(force_dfp, bool, 0);
2529 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2530 module_param(ignore_edid, bool, 0);
2531 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2532 module_param(monitor_layout, charp, 0);
2533 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2534 module_param(force_measure_pll, bool, 0);
2535 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2537 module_param(nomtrr, bool, 0);
2538 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2540 module_param(panel_yres, int, 0);
2541 MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2542 module_param(mode_option, charp, 0);
2543 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2544 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2545 module_param(force_sleep, bool, 0);
2546 MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware");
2547 module_param(ignore_devlist, bool, 0);
2548 MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops");
projects / linux-2.6 / blob