Merge branch 'drm-patches' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied...
[linux-2.6] / arch / sparc64 / kernel / pci_sun4v.c
1 /* pci_sun4v.c: SUN4V specific PCI controller support.
2  *
3  * Copyright (C) 2006, 2007 David S. Miller (davem@davemloft.net)
4  */
5
6 #include <linux/kernel.h>
7 #include <linux/types.h>
8 #include <linux/pci.h>
9 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12 #include <linux/percpu.h>
13 #include <linux/irq.h>
14 #include <linux/msi.h>
15 #include <linux/log2.h>
16
17 #include <asm/iommu.h>
18 #include <asm/irq.h>
19 #include <asm/upa.h>
20 #include <asm/pstate.h>
21 #include <asm/oplib.h>
22 #include <asm/hypervisor.h>
23 #include <asm/prom.h>
24
25 #include "pci_impl.h"
26 #include "iommu_common.h"
27
28 #include "pci_sun4v.h"
29
30 static unsigned long vpci_major = 1;
31 static unsigned long vpci_minor = 1;
32
33 #define PGLIST_NENTS    (PAGE_SIZE / sizeof(u64))
34
35 struct iommu_batch {
36         struct device   *dev;           /* Device mapping is for.       */
37         unsigned long   prot;           /* IOMMU page protections       */
38         unsigned long   entry;          /* Index into IOTSB.            */
39         u64             *pglist;        /* List of physical pages       */
40         unsigned long   npages;         /* Number of pages in list.     */
41 };
42
43 static DEFINE_PER_CPU(struct iommu_batch, iommu_batch);
44
45 /* Interrupts must be disabled.  */
46 static inline void iommu_batch_start(struct device *dev, unsigned long prot, unsigned long entry)
47 {
48         struct iommu_batch *p = &__get_cpu_var(iommu_batch);
49
50         p->dev          = dev;
51         p->prot         = prot;
52         p->entry        = entry;
53         p->npages       = 0;
54 }
55
56 /* Interrupts must be disabled.  */
57 static long iommu_batch_flush(struct iommu_batch *p)
58 {
59         struct pci_pbm_info *pbm = p->dev->archdata.host_controller;
60         unsigned long devhandle = pbm->devhandle;
61         unsigned long prot = p->prot;
62         unsigned long entry = p->entry;
63         u64 *pglist = p->pglist;
64         unsigned long npages = p->npages;
65
66         while (npages != 0) {
67                 long num;
68
69                 num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),
70                                           npages, prot, __pa(pglist));
71                 if (unlikely(num < 0)) {
72                         if (printk_ratelimit())
73                                 printk("iommu_batch_flush: IOMMU map of "
74                                        "[%08lx:%08lx:%lx:%lx:%lx] failed with "
75                                        "status %ld\n",
76                                        devhandle, HV_PCI_TSBID(0, entry),
77                                        npages, prot, __pa(pglist), num);
78                         return -1;
79                 }
80
81                 entry += num;
82                 npages -= num;
83                 pglist += num;
84         }
85
86         p->entry = entry;
87         p->npages = 0;
88
89         return 0;
90 }
91
92 /* Interrupts must be disabled.  */
93 static inline long iommu_batch_add(u64 phys_page)
94 {
95         struct iommu_batch *p = &__get_cpu_var(iommu_batch);
96
97         BUG_ON(p->npages >= PGLIST_NENTS);
98
99         p->pglist[p->npages++] = phys_page;
100         if (p->npages == PGLIST_NENTS)
101                 return iommu_batch_flush(p);
102
103         return 0;
104 }
105
106 /* Interrupts must be disabled.  */
107 static inline long iommu_batch_end(void)
108 {
109         struct iommu_batch *p = &__get_cpu_var(iommu_batch);
110
111         BUG_ON(p->npages >= PGLIST_NENTS);
112
113         return iommu_batch_flush(p);
114 }
115
116 static long arena_alloc(struct iommu_arena *arena, unsigned long npages)
117 {
118         unsigned long n, i, start, end, limit;
119         int pass;
120
121         limit = arena->limit;
122         start = arena->hint;
123         pass = 0;
124
125 again:
126         n = find_next_zero_bit(arena->map, limit, start);
127         end = n + npages;
128         if (unlikely(end >= limit)) {
129                 if (likely(pass < 1)) {
130                         limit = start;
131                         start = 0;
132                         pass++;
133                         goto again;
134                 } else {
135                         /* Scanned the whole thing, give up. */
136                         return -1;
137                 }
138         }
139
140         for (i = n; i < end; i++) {
141                 if (test_bit(i, arena->map)) {
142                         start = i + 1;
143                         goto again;
144                 }
145         }
146
147         for (i = n; i < end; i++)
148                 __set_bit(i, arena->map);
149
150         arena->hint = end;
151
152         return n;
153 }
154
155 static void arena_free(struct iommu_arena *arena, unsigned long base,
156                        unsigned long npages)
157 {
158         unsigned long i;
159
160         for (i = base; i < (base + npages); i++)
161                 __clear_bit(i, arena->map);
162 }
163
164 static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
165                                    dma_addr_t *dma_addrp, gfp_t gfp)
166 {
167         struct iommu *iommu;
168         unsigned long flags, order, first_page, npages, n;
169         void *ret;
170         long entry;
171
172         size = IO_PAGE_ALIGN(size);
173         order = get_order(size);
174         if (unlikely(order >= MAX_ORDER))
175                 return NULL;
176
177         npages = size >> IO_PAGE_SHIFT;
178
179         first_page = __get_free_pages(gfp, order);
180         if (unlikely(first_page == 0UL))
181                 return NULL;
182
183         memset((char *)first_page, 0, PAGE_SIZE << order);
184
185         iommu = dev->archdata.iommu;
186
187         spin_lock_irqsave(&iommu->lock, flags);
188         entry = arena_alloc(&iommu->arena, npages);
189         spin_unlock_irqrestore(&iommu->lock, flags);
190
191         if (unlikely(entry < 0L))
192                 goto arena_alloc_fail;
193
194         *dma_addrp = (iommu->page_table_map_base +
195                       (entry << IO_PAGE_SHIFT));
196         ret = (void *) first_page;
197         first_page = __pa(first_page);
198
199         local_irq_save(flags);
200
201         iommu_batch_start(dev,
202                           (HV_PCI_MAP_ATTR_READ |
203                            HV_PCI_MAP_ATTR_WRITE),
204                           entry);
205
206         for (n = 0; n < npages; n++) {
207                 long err = iommu_batch_add(first_page + (n * PAGE_SIZE));
208                 if (unlikely(err < 0L))
209                         goto iommu_map_fail;
210         }
211
212         if (unlikely(iommu_batch_end() < 0L))
213                 goto iommu_map_fail;
214
215         local_irq_restore(flags);
216
217         return ret;
218
219 iommu_map_fail:
220         /* Interrupts are disabled.  */
221         spin_lock(&iommu->lock);
222         arena_free(&iommu->arena, entry, npages);
223         spin_unlock_irqrestore(&iommu->lock, flags);
224
225 arena_alloc_fail:
226         free_pages(first_page, order);
227         return NULL;
228 }
229
230 static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu,
231                                  dma_addr_t dvma)
232 {
233         struct pci_pbm_info *pbm;
234         struct iommu *iommu;
235         unsigned long flags, order, npages, entry;
236         u32 devhandle;
237
238         npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
239         iommu = dev->archdata.iommu;
240         pbm = dev->archdata.host_controller;
241         devhandle = pbm->devhandle;
242         entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
243
244         spin_lock_irqsave(&iommu->lock, flags);
245
246         arena_free(&iommu->arena, entry, npages);
247
248         do {
249                 unsigned long num;
250
251                 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
252                                             npages);
253                 entry += num;
254                 npages -= num;
255         } while (npages != 0);
256
257         spin_unlock_irqrestore(&iommu->lock, flags);
258
259         order = get_order(size);
260         if (order < 10)
261                 free_pages((unsigned long)cpu, order);
262 }
263
264 static dma_addr_t dma_4v_map_single(struct device *dev, void *ptr, size_t sz,
265                                     enum dma_data_direction direction)
266 {
267         struct iommu *iommu;
268         unsigned long flags, npages, oaddr;
269         unsigned long i, base_paddr;
270         u32 bus_addr, ret;
271         unsigned long prot;
272         long entry;
273
274         iommu = dev->archdata.iommu;
275
276         if (unlikely(direction == DMA_NONE))
277                 goto bad;
278
279         oaddr = (unsigned long)ptr;
280         npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
281         npages >>= IO_PAGE_SHIFT;
282
283         spin_lock_irqsave(&iommu->lock, flags);
284         entry = arena_alloc(&iommu->arena, npages);
285         spin_unlock_irqrestore(&iommu->lock, flags);
286
287         if (unlikely(entry < 0L))
288                 goto bad;
289
290         bus_addr = (iommu->page_table_map_base +
291                     (entry << IO_PAGE_SHIFT));
292         ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
293         base_paddr = __pa(oaddr & IO_PAGE_MASK);
294         prot = HV_PCI_MAP_ATTR_READ;
295         if (direction != DMA_TO_DEVICE)
296                 prot |= HV_PCI_MAP_ATTR_WRITE;
297
298         local_irq_save(flags);
299
300         iommu_batch_start(dev, prot, entry);
301
302         for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
303                 long err = iommu_batch_add(base_paddr);
304                 if (unlikely(err < 0L))
305                         goto iommu_map_fail;
306         }
307         if (unlikely(iommu_batch_end() < 0L))
308                 goto iommu_map_fail;
309
310         local_irq_restore(flags);
311
312         return ret;
313
314 bad:
315         if (printk_ratelimit())
316                 WARN_ON(1);
317         return DMA_ERROR_CODE;
318
319 iommu_map_fail:
320         /* Interrupts are disabled.  */
321         spin_lock(&iommu->lock);
322         arena_free(&iommu->arena, entry, npages);
323         spin_unlock_irqrestore(&iommu->lock, flags);
324
325         return DMA_ERROR_CODE;
326 }
327
328 static void dma_4v_unmap_single(struct device *dev, dma_addr_t bus_addr,
329                                 size_t sz, enum dma_data_direction direction)
330 {
331         struct pci_pbm_info *pbm;
332         struct iommu *iommu;
333         unsigned long flags, npages;
334         long entry;
335         u32 devhandle;
336
337         if (unlikely(direction == DMA_NONE)) {
338                 if (printk_ratelimit())
339                         WARN_ON(1);
340                 return;
341         }
342
343         iommu = dev->archdata.iommu;
344         pbm = dev->archdata.host_controller;
345         devhandle = pbm->devhandle;
346
347         npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
348         npages >>= IO_PAGE_SHIFT;
349         bus_addr &= IO_PAGE_MASK;
350
351         spin_lock_irqsave(&iommu->lock, flags);
352
353         entry = (bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT;
354         arena_free(&iommu->arena, entry, npages);
355
356         do {
357                 unsigned long num;
358
359                 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
360                                             npages);
361                 entry += num;
362                 npages -= num;
363         } while (npages != 0);
364
365         spin_unlock_irqrestore(&iommu->lock, flags);
366 }
367
368 #define SG_ENT_PHYS_ADDRESS(SG) \
369         (__pa(page_address((SG)->page)) + (SG)->offset)
370
371 static inline long fill_sg(long entry, struct device *dev,
372                            struct scatterlist *sg,
373                            int nused, int nelems, unsigned long prot)
374 {
375         struct scatterlist *dma_sg = sg;
376         struct scatterlist *sg_end = sg + nelems;
377         unsigned long flags;
378         int i;
379
380         local_irq_save(flags);
381
382         iommu_batch_start(dev, prot, entry);
383
384         for (i = 0; i < nused; i++) {
385                 unsigned long pteval = ~0UL;
386                 u32 dma_npages;
387
388                 dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
389                               dma_sg->dma_length +
390                               ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
391                 do {
392                         unsigned long offset;
393                         signed int len;
394
395                         /* If we are here, we know we have at least one
396                          * more page to map.  So walk forward until we
397                          * hit a page crossing, and begin creating new
398                          * mappings from that spot.
399                          */
400                         for (;;) {
401                                 unsigned long tmp;
402
403                                 tmp = SG_ENT_PHYS_ADDRESS(sg);
404                                 len = sg->length;
405                                 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
406                                         pteval = tmp & IO_PAGE_MASK;
407                                         offset = tmp & (IO_PAGE_SIZE - 1UL);
408                                         break;
409                                 }
410                                 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
411                                         pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
412                                         offset = 0UL;
413                                         len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
414                                         break;
415                                 }
416                                 sg++;
417                         }
418
419                         pteval = (pteval & IOPTE_PAGE);
420                         while (len > 0) {
421                                 long err;
422
423                                 err = iommu_batch_add(pteval);
424                                 if (unlikely(err < 0L))
425                                         goto iommu_map_failed;
426
427                                 pteval += IO_PAGE_SIZE;
428                                 len -= (IO_PAGE_SIZE - offset);
429                                 offset = 0;
430                                 dma_npages--;
431                         }
432
433                         pteval = (pteval & IOPTE_PAGE) + len;
434                         sg++;
435
436                         /* Skip over any tail mappings we've fully mapped,
437                          * adjusting pteval along the way.  Stop when we
438                          * detect a page crossing event.
439                          */
440                         while (sg < sg_end &&
441                                (pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
442                                (pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
443                                ((pteval ^
444                                  (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
445                                 pteval += sg->length;
446                                 sg++;
447                         }
448                         if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
449                                 pteval = ~0UL;
450                 } while (dma_npages != 0);
451                 dma_sg++;
452         }
453
454         if (unlikely(iommu_batch_end() < 0L))
455                 goto iommu_map_failed;
456
457         local_irq_restore(flags);
458         return 0;
459
460 iommu_map_failed:
461         local_irq_restore(flags);
462         return -1L;
463 }
464
465 static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
466                          int nelems, enum dma_data_direction direction)
467 {
468         struct iommu *iommu;
469         unsigned long flags, npages, prot;
470         u32 dma_base;
471         struct scatterlist *sgtmp;
472         long entry, err;
473         int used;
474
475         /* Fast path single entry scatterlists. */
476         if (nelems == 1) {
477                 sglist->dma_address =
478                         dma_4v_map_single(dev,
479                                           (page_address(sglist->page) +
480                                            sglist->offset),
481                                           sglist->length, direction);
482                 if (unlikely(sglist->dma_address == DMA_ERROR_CODE))
483                         return 0;
484                 sglist->dma_length = sglist->length;
485                 return 1;
486         }
487
488         iommu = dev->archdata.iommu;
489         
490         if (unlikely(direction == DMA_NONE))
491                 goto bad;
492
493         /* Step 1: Prepare scatter list. */
494         npages = prepare_sg(sglist, nelems);
495
496         /* Step 2: Allocate a cluster and context, if necessary. */
497         spin_lock_irqsave(&iommu->lock, flags);
498         entry = arena_alloc(&iommu->arena, npages);
499         spin_unlock_irqrestore(&iommu->lock, flags);
500
501         if (unlikely(entry < 0L))
502                 goto bad;
503
504         dma_base = iommu->page_table_map_base +
505                 (entry << IO_PAGE_SHIFT);
506
507         /* Step 3: Normalize DMA addresses. */
508         used = nelems;
509
510         sgtmp = sglist;
511         while (used && sgtmp->dma_length) {
512                 sgtmp->dma_address += dma_base;
513                 sgtmp++;
514                 used--;
515         }
516         used = nelems - used;
517
518         /* Step 4: Create the mappings. */
519         prot = HV_PCI_MAP_ATTR_READ;
520         if (direction != DMA_TO_DEVICE)
521                 prot |= HV_PCI_MAP_ATTR_WRITE;
522
523         err = fill_sg(entry, dev, sglist, used, nelems, prot);
524         if (unlikely(err < 0L))
525                 goto iommu_map_failed;
526
527         return used;
528
529 bad:
530         if (printk_ratelimit())
531                 WARN_ON(1);
532         return 0;
533
534 iommu_map_failed:
535         spin_lock_irqsave(&iommu->lock, flags);
536         arena_free(&iommu->arena, entry, npages);
537         spin_unlock_irqrestore(&iommu->lock, flags);
538
539         return 0;
540 }
541
542 static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
543                             int nelems, enum dma_data_direction direction)
544 {
545         struct pci_pbm_info *pbm;
546         struct iommu *iommu;
547         unsigned long flags, i, npages;
548         long entry;
549         u32 devhandle, bus_addr;
550
551         if (unlikely(direction == DMA_NONE)) {
552                 if (printk_ratelimit())
553                         WARN_ON(1);
554         }
555
556         iommu = dev->archdata.iommu;
557         pbm = dev->archdata.host_controller;
558         devhandle = pbm->devhandle;
559         
560         bus_addr = sglist->dma_address & IO_PAGE_MASK;
561
562         for (i = 1; i < nelems; i++)
563                 if (sglist[i].dma_length == 0)
564                         break;
565         i--;
566         npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) -
567                   bus_addr) >> IO_PAGE_SHIFT;
568
569         entry = ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
570
571         spin_lock_irqsave(&iommu->lock, flags);
572
573         arena_free(&iommu->arena, entry, npages);
574
575         do {
576                 unsigned long num;
577
578                 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
579                                             npages);
580                 entry += num;
581                 npages -= num;
582         } while (npages != 0);
583
584         spin_unlock_irqrestore(&iommu->lock, flags);
585 }
586
587 static void dma_4v_sync_single_for_cpu(struct device *dev,
588                                        dma_addr_t bus_addr, size_t sz,
589                                        enum dma_data_direction direction)
590 {
591         /* Nothing to do... */
592 }
593
594 static void dma_4v_sync_sg_for_cpu(struct device *dev,
595                                    struct scatterlist *sglist, int nelems,
596                                    enum dma_data_direction direction)
597 {
598         /* Nothing to do... */
599 }
600
601 const struct dma_ops sun4v_dma_ops = {
602         .alloc_coherent                 = dma_4v_alloc_coherent,
603         .free_coherent                  = dma_4v_free_coherent,
604         .map_single                     = dma_4v_map_single,
605         .unmap_single                   = dma_4v_unmap_single,
606         .map_sg                         = dma_4v_map_sg,
607         .unmap_sg                       = dma_4v_unmap_sg,
608         .sync_single_for_cpu            = dma_4v_sync_single_for_cpu,
609         .sync_sg_for_cpu                = dma_4v_sync_sg_for_cpu,
610 };
611
612 static void pci_sun4v_scan_bus(struct pci_pbm_info *pbm)
613 {
614         struct property *prop;
615         struct device_node *dp;
616
617         dp = pbm->prom_node;
618         prop = of_find_property(dp, "66mhz-capable", NULL);
619         pbm->is_66mhz_capable = (prop != NULL);
620         pbm->pci_bus = pci_scan_one_pbm(pbm);
621
622         /* XXX register error interrupt handlers XXX */
623 }
624
625 static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
626                                             struct iommu *iommu)
627 {
628         struct iommu_arena *arena = &iommu->arena;
629         unsigned long i, cnt = 0;
630         u32 devhandle;
631
632         devhandle = pbm->devhandle;
633         for (i = 0; i < arena->limit; i++) {
634                 unsigned long ret, io_attrs, ra;
635
636                 ret = pci_sun4v_iommu_getmap(devhandle,
637                                              HV_PCI_TSBID(0, i),
638                                              &io_attrs, &ra);
639                 if (ret == HV_EOK) {
640                         if (page_in_phys_avail(ra)) {
641                                 pci_sun4v_iommu_demap(devhandle,
642                                                       HV_PCI_TSBID(0, i), 1);
643                         } else {
644                                 cnt++;
645                                 __set_bit(i, arena->map);
646                         }
647                 }
648         }
649
650         return cnt;
651 }
652
653 static void pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
654 {
655         struct iommu *iommu = pbm->iommu;
656         struct property *prop;
657         unsigned long num_tsb_entries, sz, tsbsize;
658         u32 vdma[2], dma_mask, dma_offset;
659
660         prop = of_find_property(pbm->prom_node, "virtual-dma", NULL);
661         if (prop) {
662                 u32 *val = prop->value;
663
664                 vdma[0] = val[0];
665                 vdma[1] = val[1];
666         } else {
667                 /* No property, use default values. */
668                 vdma[0] = 0x80000000;
669                 vdma[1] = 0x80000000;
670         }
671
672         if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) {
673                 prom_printf("PCI-SUN4V: strange virtual-dma[%08x:%08x].\n",
674                             vdma[0], vdma[1]);
675                 prom_halt();
676         };
677
678         dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL);
679         num_tsb_entries = vdma[1] / IO_PAGE_SIZE;
680         tsbsize = num_tsb_entries * sizeof(iopte_t);
681
682         dma_offset = vdma[0];
683
684         /* Setup initial software IOMMU state. */
685         spin_lock_init(&iommu->lock);
686         iommu->ctx_lowest_free = 1;
687         iommu->page_table_map_base = dma_offset;
688         iommu->dma_addr_mask = dma_mask;
689
690         /* Allocate and initialize the free area map.  */
691         sz = (num_tsb_entries + 7) / 8;
692         sz = (sz + 7UL) & ~7UL;
693         iommu->arena.map = kzalloc(sz, GFP_KERNEL);
694         if (!iommu->arena.map) {
695                 prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n");
696                 prom_halt();
697         }
698         iommu->arena.limit = num_tsb_entries;
699
700         sz = probe_existing_entries(pbm, iommu);
701         if (sz)
702                 printk("%s: Imported %lu TSB entries from OBP\n",
703                        pbm->name, sz);
704 }
705
706 #ifdef CONFIG_PCI_MSI
707 struct pci_sun4v_msiq_entry {
708         u64             version_type;
709 #define MSIQ_VERSION_MASK               0xffffffff00000000UL
710 #define MSIQ_VERSION_SHIFT              32
711 #define MSIQ_TYPE_MASK                  0x00000000000000ffUL
712 #define MSIQ_TYPE_SHIFT                 0
713 #define MSIQ_TYPE_NONE                  0x00
714 #define MSIQ_TYPE_MSG                   0x01
715 #define MSIQ_TYPE_MSI32                 0x02
716 #define MSIQ_TYPE_MSI64                 0x03
717 #define MSIQ_TYPE_INTX                  0x08
718 #define MSIQ_TYPE_NONE2                 0xff
719
720         u64             intx_sysino;
721         u64             reserved1;
722         u64             stick;
723         u64             req_id;  /* bus/device/func */
724 #define MSIQ_REQID_BUS_MASK             0xff00UL
725 #define MSIQ_REQID_BUS_SHIFT            8
726 #define MSIQ_REQID_DEVICE_MASK          0x00f8UL
727 #define MSIQ_REQID_DEVICE_SHIFT         3
728 #define MSIQ_REQID_FUNC_MASK            0x0007UL
729 #define MSIQ_REQID_FUNC_SHIFT           0
730
731         u64             msi_address;
732
733         /* The format of this value is message type dependent.
734          * For MSI bits 15:0 are the data from the MSI packet.
735          * For MSI-X bits 31:0 are the data from the MSI packet.
736          * For MSG, the message code and message routing code where:
737          *      bits 39:32 is the bus/device/fn of the msg target-id
738          *      bits 18:16 is the message routing code
739          *      bits 7:0 is the message code
740          * For INTx the low order 2-bits are:
741          *      00 - INTA
742          *      01 - INTB
743          *      10 - INTC
744          *      11 - INTD
745          */
746         u64             msi_data;
747
748         u64             reserved2;
749 };
750
751 /* For now this just runs as a pre-handler for the real interrupt handler.
752  * So we just walk through the queue and ACK all the entries, update the
753  * head pointer, and return.
754  *
755  * In the longer term it would be nice to do something more integrated
756  * wherein we can pass in some of this MSI info to the drivers.  This
757  * would be most useful for PCIe fabric error messages, although we could
758  * invoke those directly from the loop here in order to pass the info around.
759  */
760 static void pci_sun4v_msi_prehandler(unsigned int ino, void *data1, void *data2)
761 {
762         struct pci_pbm_info *pbm = data1;
763         struct pci_sun4v_msiq_entry *base, *ep;
764         unsigned long msiqid, orig_head, head, type, err;
765
766         msiqid = (unsigned long) data2;
767
768         head = 0xdeadbeef;
769         err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, &head);
770         if (unlikely(err))
771                 goto hv_error_get;
772
773         if (unlikely(head >= (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry))))
774                 goto bad_offset;
775
776         head /= sizeof(struct pci_sun4v_msiq_entry);
777         orig_head = head;
778         base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) *
779                                    (pbm->msiq_ent_count *
780                                     sizeof(struct pci_sun4v_msiq_entry))));
781         ep = &base[head];
782         while ((ep->version_type & MSIQ_TYPE_MASK) != 0) {
783                 type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT;
784                 if (unlikely(type != MSIQ_TYPE_MSI32 &&
785                              type != MSIQ_TYPE_MSI64))
786                         goto bad_type;
787
788                 pci_sun4v_msi_setstate(pbm->devhandle,
789                                        ep->msi_data /* msi_num */,
790                                        HV_MSISTATE_IDLE);
791
792                 /* Clear the entry.  */
793                 ep->version_type &= ~MSIQ_TYPE_MASK;
794
795                 /* Go to next entry in ring.  */
796                 head++;
797                 if (head >= pbm->msiq_ent_count)
798                         head = 0;
799                 ep = &base[head];
800         }
801
802         if (likely(head != orig_head)) {
803                 /* ACK entries by updating head pointer.  */
804                 head *= sizeof(struct pci_sun4v_msiq_entry);
805                 err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head);
806                 if (unlikely(err))
807                         goto hv_error_set;
808         }
809         return;
810
811 hv_error_set:
812         printk(KERN_EMERG "MSI: Hypervisor set head gives error %lu\n", err);
813         goto hv_error_cont;
814
815 hv_error_get:
816         printk(KERN_EMERG "MSI: Hypervisor get head gives error %lu\n", err);
817
818 hv_error_cont:
819         printk(KERN_EMERG "MSI: devhandle[%x] msiqid[%lx] head[%lu]\n",
820                pbm->devhandle, msiqid, head);
821         return;
822
823 bad_offset:
824         printk(KERN_EMERG "MSI: Hypervisor gives bad offset %lx max(%lx)\n",
825                head, pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry));
826         return;
827
828 bad_type:
829         printk(KERN_EMERG "MSI: Entry has bad type %lx\n", type);
830         return;
831 }
832
833 static int msi_bitmap_alloc(struct pci_pbm_info *pbm)
834 {
835         unsigned long size, bits_per_ulong;
836
837         bits_per_ulong = sizeof(unsigned long) * 8;
838         size = (pbm->msi_num + (bits_per_ulong - 1)) & ~(bits_per_ulong - 1);
839         size /= 8;
840         BUG_ON(size % sizeof(unsigned long));
841
842         pbm->msi_bitmap = kzalloc(size, GFP_KERNEL);
843         if (!pbm->msi_bitmap)
844                 return -ENOMEM;
845
846         return 0;
847 }
848
849 static void msi_bitmap_free(struct pci_pbm_info *pbm)
850 {
851         kfree(pbm->msi_bitmap);
852         pbm->msi_bitmap = NULL;
853 }
854
855 static int msi_queue_alloc(struct pci_pbm_info *pbm)
856 {
857         unsigned long q_size, alloc_size, pages, order;
858         int i;
859
860         q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
861         alloc_size = (pbm->msiq_num * q_size);
862         order = get_order(alloc_size);
863         pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
864         if (pages == 0UL) {
865                 printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
866                        order);
867                 return -ENOMEM;
868         }
869         memset((char *)pages, 0, PAGE_SIZE << order);
870         pbm->msi_queues = (void *) pages;
871
872         for (i = 0; i < pbm->msiq_num; i++) {
873                 unsigned long err, base = __pa(pages + (i * q_size));
874                 unsigned long ret1, ret2;
875
876                 err = pci_sun4v_msiq_conf(pbm->devhandle,
877                                           pbm->msiq_first + i,
878                                           base, pbm->msiq_ent_count);
879                 if (err) {
880                         printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n",
881                                err);
882                         goto h_error;
883                 }
884
885                 err = pci_sun4v_msiq_info(pbm->devhandle,
886                                           pbm->msiq_first + i,
887                                           &ret1, &ret2);
888                 if (err) {
889                         printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n",
890                                err);
891                         goto h_error;
892                 }
893                 if (ret1 != base || ret2 != pbm->msiq_ent_count) {
894                         printk(KERN_ERR "MSI: Bogus qconf "
895                                "expected[%lx:%x] got[%lx:%lx]\n",
896                                base, pbm->msiq_ent_count,
897                                ret1, ret2);
898                         goto h_error;
899                 }
900         }
901
902         return 0;
903
904 h_error:
905         free_pages(pages, order);
906         return -EINVAL;
907 }
908
909
910 static int alloc_msi(struct pci_pbm_info *pbm)
911 {
912         int i;
913
914         for (i = 0; i < pbm->msi_num; i++) {
915                 if (!test_and_set_bit(i, pbm->msi_bitmap))
916                         return i + pbm->msi_first;
917         }
918
919         return -ENOENT;
920 }
921
922 static void free_msi(struct pci_pbm_info *pbm, int msi_num)
923 {
924         msi_num -= pbm->msi_first;
925         clear_bit(msi_num, pbm->msi_bitmap);
926 }
927
928 static int pci_sun4v_setup_msi_irq(unsigned int *virt_irq_p,
929                                    struct pci_dev *pdev,
930                                    struct msi_desc *entry)
931 {
932         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
933         unsigned long devino, msiqid;
934         struct msi_msg msg;
935         int msi_num, err;
936
937         *virt_irq_p = 0;
938
939         msi_num = alloc_msi(pbm);
940         if (msi_num < 0)
941                 return msi_num;
942
943         devino = sun4v_build_msi(pbm->devhandle, virt_irq_p,
944                                  pbm->msiq_first_devino,
945                                  (pbm->msiq_first_devino +
946                                   pbm->msiq_num));
947         err = -ENOMEM;
948         if (!devino)
949                 goto out_err;
950
951         msiqid = ((devino - pbm->msiq_first_devino) +
952                   pbm->msiq_first);
953
954         err = -EINVAL;
955         if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
956         if (err)
957                 goto out_err;
958
959         if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
960                 goto out_err;
961
962         if (pci_sun4v_msi_setmsiq(pbm->devhandle,
963                                   msi_num, msiqid,
964                                   (entry->msi_attrib.is_64 ?
965                                    HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32)))
966                 goto out_err;
967
968         if (pci_sun4v_msi_setstate(pbm->devhandle, msi_num, HV_MSISTATE_IDLE))
969                 goto out_err;
970
971         if (pci_sun4v_msi_setvalid(pbm->devhandle, msi_num, HV_MSIVALID_VALID))
972                 goto out_err;
973
974         pdev->dev.archdata.msi_num = msi_num;
975
976         if (entry->msi_attrib.is_64) {
977                 msg.address_hi = pbm->msi64_start >> 32;
978                 msg.address_lo = pbm->msi64_start & 0xffffffff;
979         } else {
980                 msg.address_hi = 0;
981                 msg.address_lo = pbm->msi32_start;
982         }
983         msg.data = msi_num;
984
985         set_irq_msi(*virt_irq_p, entry);
986         write_msi_msg(*virt_irq_p, &msg);
987
988         irq_install_pre_handler(*virt_irq_p,
989                                 pci_sun4v_msi_prehandler,
990                                 pbm, (void *) msiqid);
991
992         return 0;
993
994 out_err:
995         free_msi(pbm, msi_num);
996         sun4v_destroy_msi(*virt_irq_p);
997         *virt_irq_p = 0;
998         return err;
999
1000 }
1001
1002 static void pci_sun4v_teardown_msi_irq(unsigned int virt_irq,
1003                                        struct pci_dev *pdev)
1004 {
1005         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1006         unsigned long msiqid, err;
1007         unsigned int msi_num;
1008
1009         msi_num = pdev->dev.archdata.msi_num;
1010         err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi_num, &msiqid);
1011         if (err) {
1012                 printk(KERN_ERR "%s: getmsiq gives error %lu\n",
1013                        pbm->name, err);
1014                 return;
1015         }
1016
1017         pci_sun4v_msi_setvalid(pbm->devhandle, msi_num, HV_MSIVALID_INVALID);
1018         pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_INVALID);
1019
1020         free_msi(pbm, msi_num);
1021
1022         /* The sun4v_destroy_msi() will liberate the devino and thus the MSIQ
1023          * allocation.
1024          */
1025         sun4v_destroy_msi(virt_irq);
1026 }
1027
1028 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1029 {
1030         const u32 *val;
1031         int len;
1032
1033         val = of_get_property(pbm->prom_node, "#msi-eqs", &len);
1034         if (!val || len != 4)
1035                 goto no_msi;
1036         pbm->msiq_num = *val;
1037         if (pbm->msiq_num) {
1038                 const struct msiq_prop {
1039                         u32 first_msiq;
1040                         u32 num_msiq;
1041                         u32 first_devino;
1042                 } *mqp;
1043                 const struct msi_range_prop {
1044                         u32 first_msi;
1045                         u32 num_msi;
1046                 } *mrng;
1047                 const struct addr_range_prop {
1048                         u32 msi32_high;
1049                         u32 msi32_low;
1050                         u32 msi32_len;
1051                         u32 msi64_high;
1052                         u32 msi64_low;
1053                         u32 msi64_len;
1054                 } *arng;
1055
1056                 val = of_get_property(pbm->prom_node, "msi-eq-size", &len);
1057                 if (!val || len != 4)
1058                         goto no_msi;
1059
1060                 pbm->msiq_ent_count = *val;
1061
1062                 mqp = of_get_property(pbm->prom_node,
1063                                       "msi-eq-to-devino", &len);
1064                 if (!mqp || len != sizeof(struct msiq_prop))
1065                         goto no_msi;
1066
1067                 pbm->msiq_first = mqp->first_msiq;
1068                 pbm->msiq_first_devino = mqp->first_devino;
1069
1070                 val = of_get_property(pbm->prom_node, "#msi", &len);
1071                 if (!val || len != 4)
1072                         goto no_msi;
1073                 pbm->msi_num = *val;
1074
1075                 mrng = of_get_property(pbm->prom_node, "msi-ranges", &len);
1076                 if (!mrng || len != sizeof(struct msi_range_prop))
1077                         goto no_msi;
1078                 pbm->msi_first = mrng->first_msi;
1079
1080                 val = of_get_property(pbm->prom_node, "msi-data-mask", &len);
1081                 if (!val || len != 4)
1082                         goto no_msi;
1083                 pbm->msi_data_mask = *val;
1084
1085                 val = of_get_property(pbm->prom_node, "msix-data-width", &len);
1086                 if (!val || len != 4)
1087                         goto no_msi;
1088                 pbm->msix_data_width = *val;
1089
1090                 arng = of_get_property(pbm->prom_node, "msi-address-ranges",
1091                                        &len);
1092                 if (!arng || len != sizeof(struct addr_range_prop))
1093                         goto no_msi;
1094                 pbm->msi32_start = ((u64)arng->msi32_high << 32) |
1095                         (u64) arng->msi32_low;
1096                 pbm->msi64_start = ((u64)arng->msi64_high << 32) |
1097                         (u64) arng->msi64_low;
1098                 pbm->msi32_len = arng->msi32_len;
1099                 pbm->msi64_len = arng->msi64_len;
1100
1101                 if (msi_bitmap_alloc(pbm))
1102                         goto no_msi;
1103
1104                 if (msi_queue_alloc(pbm)) {
1105                         msi_bitmap_free(pbm);
1106                         goto no_msi;
1107                 }
1108
1109                 printk(KERN_INFO "%s: MSI Queue first[%u] num[%u] count[%u] "
1110                        "devino[0x%x]\n",
1111                        pbm->name,
1112                        pbm->msiq_first, pbm->msiq_num,
1113                        pbm->msiq_ent_count,
1114                        pbm->msiq_first_devino);
1115                 printk(KERN_INFO "%s: MSI first[%u] num[%u] mask[0x%x] "
1116                        "width[%u]\n",
1117                        pbm->name,
1118                        pbm->msi_first, pbm->msi_num, pbm->msi_data_mask,
1119                        pbm->msix_data_width);
1120                 printk(KERN_INFO "%s: MSI addr32[0x%lx:0x%x] "
1121                        "addr64[0x%lx:0x%x]\n",
1122                        pbm->name,
1123                        pbm->msi32_start, pbm->msi32_len,
1124                        pbm->msi64_start, pbm->msi64_len);
1125                 printk(KERN_INFO "%s: MSI queues at RA [%p]\n",
1126                        pbm->name,
1127                        pbm->msi_queues);
1128         }
1129         pbm->setup_msi_irq = pci_sun4v_setup_msi_irq;
1130         pbm->teardown_msi_irq = pci_sun4v_teardown_msi_irq;
1131
1132         return;
1133
1134 no_msi:
1135         pbm->msiq_num = 0;
1136         printk(KERN_INFO "%s: No MSI support.\n", pbm->name);
1137 }
1138 #else /* CONFIG_PCI_MSI */
1139 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1140 {
1141 }
1142 #endif /* !(CONFIG_PCI_MSI) */
1143
1144 static void __init pci_sun4v_pbm_init(struct pci_controller_info *p, struct device_node *dp, u32 devhandle)
1145 {
1146         struct pci_pbm_info *pbm;
1147
1148         if (devhandle & 0x40)
1149                 pbm = &p->pbm_B;
1150         else
1151                 pbm = &p->pbm_A;
1152
1153         pbm->next = pci_pbm_root;
1154         pci_pbm_root = pbm;
1155
1156         pbm->scan_bus = pci_sun4v_scan_bus;
1157         pbm->pci_ops = &sun4v_pci_ops;
1158         pbm->config_space_reg_bits = 12;
1159
1160         pbm->index = pci_num_pbms++;
1161
1162         pbm->parent = p;
1163         pbm->prom_node = dp;
1164
1165         pbm->devhandle = devhandle;
1166
1167         pbm->name = dp->full_name;
1168
1169         printk("%s: SUN4V PCI Bus Module\n", pbm->name);
1170
1171         pci_determine_mem_io_space(pbm);
1172
1173         pci_get_pbm_props(pbm);
1174         pci_sun4v_iommu_init(pbm);
1175         pci_sun4v_msi_init(pbm);
1176 }
1177
1178 void __init sun4v_pci_init(struct device_node *dp, char *model_name)
1179 {
1180         static int hvapi_negotiated = 0;
1181         struct pci_controller_info *p;
1182         struct pci_pbm_info *pbm;
1183         struct iommu *iommu;
1184         struct property *prop;
1185         struct linux_prom64_registers *regs;
1186         u32 devhandle;
1187         int i;
1188
1189         if (!hvapi_negotiated++) {
1190                 int err = sun4v_hvapi_register(HV_GRP_PCI,
1191                                                vpci_major,
1192                                                &vpci_minor);
1193
1194                 if (err) {
1195                         prom_printf("SUN4V_PCI: Could not register hvapi, "
1196                                     "err=%d\n", err);
1197                         prom_halt();
1198                 }
1199                 printk("SUN4V_PCI: Registered hvapi major[%lu] minor[%lu]\n",
1200                        vpci_major, vpci_minor);
1201
1202                 dma_ops = &sun4v_dma_ops;
1203         }
1204
1205         prop = of_find_property(dp, "reg", NULL);
1206         regs = prop->value;
1207
1208         devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1209
1210         for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1211                 if (pbm->devhandle == (devhandle ^ 0x40)) {
1212                         pci_sun4v_pbm_init(pbm->parent, dp, devhandle);
1213                         return;
1214                 }
1215         }
1216
1217         for_each_possible_cpu(i) {
1218                 unsigned long page = get_zeroed_page(GFP_ATOMIC);
1219
1220                 if (!page)
1221                         goto fatal_memory_error;
1222
1223                 per_cpu(iommu_batch, i).pglist = (u64 *) page;
1224         }
1225
1226         p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1227         if (!p)
1228                 goto fatal_memory_error;
1229
1230         iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1231         if (!iommu)
1232                 goto fatal_memory_error;
1233
1234         p->pbm_A.iommu = iommu;
1235
1236         iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1237         if (!iommu)
1238                 goto fatal_memory_error;
1239
1240         p->pbm_B.iommu = iommu;
1241
1242         /* Like PSYCHO and SCHIZO we have a 2GB aligned area
1243          * for memory space.
1244          */
1245         pci_memspace_mask = 0x7fffffffUL;
1246
1247         pci_sun4v_pbm_init(p, dp, devhandle);
1248         return;
1249
1250 fatal_memory_error:
1251         prom_printf("SUN4V_PCI: Fatal memory allocation error.\n");
1252         prom_halt();
1253 }