2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
16 config RWSEM_GENERIC_SPINLOCK
20 config RWSEM_XCHGADD_ALGORITHM
34 config GENERIC_FIND_NEXT_BIT
38 config GENERIC_HWEIGHT
42 config GENERIC_HARDIRQS
46 config GENERIC_IRQ_PROBE
54 config FORCE_MAX_ZONEORDER
58 config GENERIC_CALIBRATE_DELAY
67 source "kernel/Kconfig.preempt"
69 menu "Blackfin Processor Options"
71 comment "Processor and Board Settings"
80 BF522 Processor Support.
85 BF523 Processor Support.
90 BF524 Processor Support.
95 BF525 Processor Support.
100 BF526 Processor Support.
105 BF527 Processor Support.
110 BF531 Processor Support.
115 BF532 Processor Support.
120 BF533 Processor Support.
125 BF534 Processor Support.
130 BF536 Processor Support.
135 BF537 Processor Support.
140 BF542 Processor Support.
145 BF544 Processor Support.
150 BF547 Processor Support.
155 BF548 Processor Support.
160 BF549 Processor Support.
165 Not Supported Yet - Work in progress - BF561 Processor Support.
171 default BF_REV_0_1 if BF527
172 default BF_REV_0_2 if BF537
173 default BF_REV_0_3 if BF533
174 default BF_REV_0_0 if BF549
178 depends on (BF52x || BF54x)
182 depends on (BF52x || BF54x)
186 depends on (BF537 || BF536 || BF534)
190 depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
194 depends on (BF561 || BF533 || BF532 || BF531)
198 depends on (BF561 || BF533 || BF532 || BF531)
210 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
215 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
220 depends on (BF542 || BF544 || BF547 || BF548 || BF549)
223 config MEM_GENERIC_BOARD
225 depends on GENERIC_BOARD
228 config MEM_MT48LC64M4A2FB_7E
230 depends on (BFIN533_STAMP)
233 config MEM_MT48LC16M16A2TG_75
235 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
236 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
240 config MEM_MT48LC32M8A2_75
242 depends on (BFIN537_STAMP || PNAV10)
245 config MEM_MT48LC8M32B2B5_7
247 depends on (BFIN561_BLUETECHNIX_CM)
250 config MEM_MT48LC32M16A2TG_75
252 depends on (BFIN527_EZKIT || BFIN532_IP0X)
255 source "arch/blackfin/mach-bf527/Kconfig"
256 source "arch/blackfin/mach-bf533/Kconfig"
257 source "arch/blackfin/mach-bf561/Kconfig"
258 source "arch/blackfin/mach-bf537/Kconfig"
259 source "arch/blackfin/mach-bf548/Kconfig"
261 menu "Board customizations"
264 bool "Default bootloader kernel arguments"
267 string "Initial kernel command string"
268 depends on CMDLINE_BOOL
269 default "console=ttyBF0,57600"
271 If you don't have a boot loader capable of passing a command line string
272 to the kernel, you may specify one here. As a minimum, you should specify
273 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
276 hex "Kernel load address for booting"
278 range 0x1000 0x20000000
280 This option allows you to set the load address of the kernel.
281 This can be useful if you are on a board which has a small amount
282 of memory or you wish to reserve some memory at the beginning of
285 Note that you need to keep this value above 4k (0x1000) as this
286 memory region is used to capture NULL pointer references as well
287 as some core kernel functions.
289 comment "Clock/PLL Setup"
292 int "Frequency of the crystal on the board in Hz"
293 default "11059200" if BFIN533_STAMP
294 default "27000000" if BFIN533_EZKIT
295 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
296 default "30000000" if BFIN561_EZKIT
297 default "24576000" if PNAV10
298 default "10000000" if BFIN532_IP0X
300 The frequency of CLKIN crystal oscillator on the board in Hz.
301 Warning: This value should match the crystal on the board. Otherwise,
302 peripherals won't work properly.
304 config BFIN_KERNEL_CLOCK
305 bool "Re-program Clocks while Kernel boots?"
308 This option decides if kernel clocks are re-programed from the
309 bootloader settings. If the clocks are not set, the SDRAM settings
310 are also not changed, and the Bootloader does 100% of the hardware
314 int "SDRAM Memory Size in MBytes"
315 depends on BFIN_KERNEL_CLOCK
320 depends on BFIN_KERNEL_CLOCK
325 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
328 If this is set the clock will be divided by 2, before it goes to the PLL.
332 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
334 default "22" if BFIN533_EZKIT
335 default "45" if BFIN533_STAMP
336 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
337 default "22" if BFIN533_BLUETECHNIX_CM
338 default "20" if BFIN537_BLUETECHNIX_CM
339 default "20" if BFIN561_BLUETECHNIX_CM
340 default "20" if BFIN561_EZKIT
341 default "16" if H8606_HVSISTEMAS
343 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
344 PLL Frequency = (Crystal Frequency) * (this setting)
347 prompt "Core Clock Divider"
348 depends on BFIN_KERNEL_CLOCK
351 This sets the frequency of the core. It can be 1, 2, 4 or 8
352 Core Frequency = (PLL frequency) / (this setting)
368 int "System Clock Divider"
369 depends on BFIN_KERNEL_CLOCK
373 This sets the frequency of the system clock (including SDRAM or DDR).
374 This can be between 1 and 15
375 System Clock = (PLL frequency) / (this setting)
378 int "Max SDRAM Memory Size in MBytes"
379 depends on !BFIN_KERNEL_CLOCK && !MPU
382 This is the max memory size that the kernel will create CPLB
383 tables for. Your system will not be able to handle any more.
386 prompt "DDR SDRAM Chip Type"
387 depends on BFIN_KERNEL_CLOCK
389 default MEM_MT46V32M16_5B
391 config MEM_MT46V32M16_6T
394 config MEM_MT46V32M16_5B
399 # Max & Min Speeds for various Chips
403 default 600000000 if BF522
404 default 400000000 if BF523
405 default 400000000 if BF524
406 default 600000000 if BF525
407 default 400000000 if BF526
408 default 600000000 if BF527
409 default 400000000 if BF531
410 default 400000000 if BF532
411 default 750000000 if BF533
412 default 500000000 if BF534
413 default 400000000 if BF536
414 default 600000000 if BF537
415 default 533333333 if BF538
416 default 533333333 if BF539
417 default 600000000 if BF542
418 default 533333333 if BF544
419 default 600000000 if BF547
420 default 600000000 if BF548
421 default 533333333 if BF549
422 default 600000000 if BF561
436 comment "Kernel Timer/Scheduler"
438 source kernel/Kconfig.hz
444 config GENERIC_CLOCKEVENTS
445 bool "Generic clock events"
446 depends on GENERIC_TIME
449 config CYCLES_CLOCKSOURCE
450 bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
451 depends on EXPERIMENTAL
452 depends on GENERIC_CLOCKEVENTS
453 depends on !BFIN_SCRATCH_REG_CYCLES
456 If you say Y here, you will enable support for using the 'cycles'
457 registers as a clock source. Doing so means you will be unable to
458 safely write to the 'cycles' register during runtime. You will
459 still be able to read it (such as for performance monitoring), but
460 writing the registers will most likely crash the kernel.
462 source kernel/time/Kconfig
464 comment "Memory Setup"
469 prompt "Blackfin Exception Scratch Register"
470 default BFIN_SCRATCH_REG_RETN
472 Select the resource to reserve for the Exception handler:
473 - RETN: Non-Maskable Interrupt (NMI)
474 - RETE: Exception Return (JTAG/ICE)
475 - CYCLES: Performance counter
477 If you are unsure, please select "RETN".
479 config BFIN_SCRATCH_REG_RETN
482 Use the RETN register in the Blackfin exception handler
483 as a stack scratch register. This means you cannot
484 safely use NMI on the Blackfin while running Linux, but
485 you can debug the system with a JTAG ICE and use the
486 CYCLES performance registers.
488 If you are unsure, please select "RETN".
490 config BFIN_SCRATCH_REG_RETE
493 Use the RETE register in the Blackfin exception handler
494 as a stack scratch register. This means you cannot
495 safely use a JTAG ICE while debugging a Blackfin board,
496 but you can safely use the CYCLES performance registers
499 If you are unsure, please select "RETN".
501 config BFIN_SCRATCH_REG_CYCLES
504 Use the CYCLES register in the Blackfin exception handler
505 as a stack scratch register. This means you cannot
506 safely use the CYCLES performance registers on a Blackfin
507 board at anytime, but you can debug the system with a JTAG
510 If you are unsure, please select "RETN".
517 menu "Blackfin Kernel Optimizations"
519 comment "Memory Optimizations"
522 bool "Locate interrupt entry code in L1 Memory"
525 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
526 into L1 instruction memory. (less latency)
528 config EXCPT_IRQ_SYSC_L1
529 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
532 If enabled, the entire ASM lowlevel exception and interrupt entry code
533 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
537 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
540 If enabled, the frequently called do_irq dispatcher function is linked
541 into L1 instruction memory. (less latency)
543 config CORE_TIMER_IRQ_L1
544 bool "Locate frequently called timer_interrupt() function in L1 Memory"
547 If enabled, the frequently called timer_interrupt() function is linked
548 into L1 instruction memory. (less latency)
551 bool "Locate frequently idle function in L1 Memory"
554 If enabled, the frequently called idle function is linked
555 into L1 instruction memory. (less latency)
558 bool "Locate kernel schedule function in L1 Memory"
561 If enabled, the frequently called kernel schedule is linked
562 into L1 instruction memory. (less latency)
564 config ARITHMETIC_OPS_L1
565 bool "Locate kernel owned arithmetic functions in L1 Memory"
568 If enabled, arithmetic functions are linked
569 into L1 instruction memory. (less latency)
572 bool "Locate access_ok function in L1 Memory"
575 If enabled, the access_ok function is linked
576 into L1 instruction memory. (less latency)
579 bool "Locate memset function in L1 Memory"
582 If enabled, the memset function is linked
583 into L1 instruction memory. (less latency)
586 bool "Locate memcpy function in L1 Memory"
589 If enabled, the memcpy function is linked
590 into L1 instruction memory. (less latency)
592 config SYS_BFIN_SPINLOCK_L1
593 bool "Locate sys_bfin_spinlock function in L1 Memory"
596 If enabled, sys_bfin_spinlock function is linked
597 into L1 instruction memory. (less latency)
599 config IP_CHECKSUM_L1
600 bool "Locate IP Checksum function in L1 Memory"
603 If enabled, the IP Checksum function is linked
604 into L1 instruction memory. (less latency)
606 config CACHELINE_ALIGNED_L1
607 bool "Locate cacheline_aligned data to L1 Data Memory"
612 If enabled, cacheline_anligned data is linked
613 into L1 data memory. (less latency)
615 config SYSCALL_TAB_L1
616 bool "Locate Syscall Table L1 Data Memory"
620 If enabled, the Syscall LUT is linked
621 into L1 data memory. (less latency)
623 config CPLB_SWITCH_TAB_L1
624 bool "Locate CPLB Switch Tables L1 Data Memory"
628 If enabled, the CPLB Switch Tables are linked
629 into L1 data memory. (less latency)
635 prompt "Kernel executes from"
637 Choose the memory type that the kernel will be running in.
642 The kernel will be resident in RAM when running.
647 The kernel will be resident in FLASH/ROM when running.
654 tristate "Enable Blackfin General Purpose Timers API"
657 Enable support for the General Purpose Timers API. If you
660 To compile this driver as a module, choose M here: the module
661 will be called gptimers.ko.
664 bool "Enable DMA Support"
665 depends on (BF52x || BF53x || BF561 || BF54x)
668 DMA driver for BF5xx.
671 prompt "Uncached SDRAM region"
672 default DMA_UNCACHED_1M
673 depends on BFIN_DMA_5XX
674 config DMA_UNCACHED_4M
675 bool "Enable 4M DMA region"
676 config DMA_UNCACHED_2M
677 bool "Enable 2M DMA region"
678 config DMA_UNCACHED_1M
679 bool "Enable 1M DMA region"
680 config DMA_UNCACHED_NONE
681 bool "Disable DMA region"
685 comment "Cache Support"
690 config BFIN_DCACHE_BANKA
691 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
692 depends on BFIN_DCACHE && !BF531
694 config BFIN_ICACHE_LOCK
695 bool "Enable Instruction Cache Locking"
699 depends on BFIN_DCACHE
705 Cached data will be written back to SDRAM only when needed.
706 This can give a nice increase in performance, but beware of
707 broken drivers that do not properly invalidate/flush their
710 Write Through Policy:
711 Cached data will always be written back to SDRAM when the
712 cache is updated. This is a completely safe setting, but
713 performance is worse than Write Back.
715 If you are unsure of the options and you want to be safe,
716 then go with Write Through.
722 Cached data will be written back to SDRAM only when needed.
723 This can give a nice increase in performance, but beware of
724 broken drivers that do not properly invalidate/flush their
727 Write Through Policy:
728 Cached data will always be written back to SDRAM when the
729 cache is updated. This is a completely safe setting, but
730 performance is worse than Write Back.
732 If you are unsure of the options and you want to be safe,
733 then go with Write Through.
738 int "Set the max L1 SRAM pieces"
741 Set the max memory pieces for the L1 SRAM allocation algorithm.
742 Min value is 16. Max value is 1024.
746 bool "Enable the memory protection unit (EXPERIMENTAL)"
749 Use the processor's MPU to protect applications from accessing
750 memory they do not own. This comes at a performance penalty
751 and is recommended only for debugging.
753 comment "Asynchonous Memory Configuration"
755 menu "EBIU_AMGCTL Global Control"
761 bool "DMA has priority over core for ext. accesses"
766 bool "Bank 0 16 bit packing enable"
771 bool "Bank 1 16 bit packing enable"
776 bool "Bank 2 16 bit packing enable"
781 bool "Bank 3 16 bit packing enable"
785 prompt"Enable Asynchonous Memory Banks"
789 bool "Disable All Banks"
795 bool "Enable Bank 0 & 1"
797 config C_AMBEN_B0_B1_B2
798 bool "Enable Bank 0 & 1 & 2"
801 bool "Enable All Banks"
805 menu "EBIU_AMBCTL Control"
813 default 0x5558 if BF54x
824 config EBIU_MBSCTLVAL
825 hex "EBIU Bank Select Control Register"
830 hex "Flash Memory Mode Control Register"
835 hex "Flash Memory Bank Control Register"
840 #############################################################################
841 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
848 source "drivers/pci/Kconfig"
851 bool "Support for hot-pluggable device"
853 Say Y here if you want to plug devices into your computer while
854 the system is running, and be able to use them quickly. In many
855 cases, the devices can likewise be unplugged at any time too.
857 One well known example of this is PCMCIA- or PC-cards, credit-card
858 size devices such as network cards, modems or hard drives which are
859 plugged into slots found on all modern laptop computers. Another
860 example, used on modern desktops as well as laptops, is USB.
862 Enable HOTPLUG and KMOD, and build a modular kernel. Get agent
863 software (at <http://linux-hotplug.sourceforge.net/>) and install it.
864 Then your kernel will automatically call out to a user mode "policy
865 agent" (/sbin/hotplug) to load modules and set up software needed
866 to use devices as you hotplug them.
868 source "drivers/pcmcia/Kconfig"
870 source "drivers/pci/hotplug/Kconfig"
874 menu "Executable file formats"
876 source "fs/Kconfig.binfmt"
880 menu "Power management options"
881 source "kernel/power/Kconfig"
883 config ARCH_SUSPEND_POSSIBLE
888 prompt "Default Power Saving Mode"
890 default PM_BFIN_SLEEP_DEEPER
891 config PM_BFIN_SLEEP_DEEPER
894 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
895 power dissipation by disabling the clock to the processor core (CCLK).
896 Furthermore, Standby sets the internal power supply voltage (VDDINT)
897 to 0.85 V to provide the greatest power savings, while preserving the
899 The PLL and system clock (SCLK) continue to operate at a very low
900 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
901 the SDRAM is put into Self Refresh Mode. Typically an external event
902 such as GPIO interrupt or RTC activity wakes up the processor.
903 Various Peripherals such as UART, SPORT, PPI may not function as
904 normal during Sleep Deeper, due to the reduced SCLK frequency.
905 When in the sleep mode, system DMA access to L1 memory is not supported.
910 Sleep Mode (High Power Savings) - The sleep mode reduces power
911 dissipation by disabling the clock to the processor core (CCLK).
912 The PLL and system clock (SCLK), however, continue to operate in
913 this mode. Typically an external event or RTC activity will wake
914 up the processor. When in the sleep mode,
915 system DMA access to L1 memory is not supported.
918 config PM_WAKEUP_BY_GPIO
919 bool "Cause Wakeup Event by GPIO"
921 config PM_WAKEUP_GPIO_NUMBER
922 int "Wakeup GPIO number"
924 depends on PM_WAKEUP_BY_GPIO
925 default 2 if BFIN537_STAMP
928 prompt "GPIO Polarity"
929 depends on PM_WAKEUP_BY_GPIO
930 default PM_WAKEUP_GPIO_POLAR_H
931 config PM_WAKEUP_GPIO_POLAR_H
933 config PM_WAKEUP_GPIO_POLAR_L
935 config PM_WAKEUP_GPIO_POLAR_EDGE_F
937 config PM_WAKEUP_GPIO_POLAR_EDGE_R
939 config PM_WAKEUP_GPIO_POLAR_EDGE_B
945 menu "CPU Frequency scaling"
947 source "drivers/cpufreq/Kconfig"
950 bool "CPU Voltage scaling"
951 depends on EXPERIMENTAL
955 Say Y here if you want CPU voltage scaling according to the CPU frequency.
956 This option violates the PLL BYPASS recommendation in the Blackfin Processor
957 manuals. There is a theoretical risk that during VDDINT transitions
964 source "drivers/Kconfig"
968 source "arch/blackfin/Kconfig.debug"
970 source "security/Kconfig"
972 source "crypto/Kconfig"