[POWERPC] 85xx: Fix 8548CDS reset bug
[linux-2.6] / arch / powerpc / boot / dts / mpc832x_mds.dts
1 /*
2  * MPC8323E EMDS Device Tree Source
3  *
4  * Copyright 2006 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12 / {
13         model = "MPC8323EMDS";
14         compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
15         #address-cells = <1>;
16         #size-cells = <1>;
17
18         cpus {
19                 #address-cells = <1>;
20                 #size-cells = <0>;
21
22                 PowerPC,8323@0 {
23                         device_type = "cpu";
24                         reg = <0>;
25                         d-cache-line-size = <20>;       // 32 bytes
26                         i-cache-line-size = <20>;       // 32 bytes
27                         d-cache-size = <4000>;          // L1, 16K
28                         i-cache-size = <4000>;          // L1, 16K
29                         timebase-frequency = <0>;
30                         bus-frequency = <0>;
31                         clock-frequency = <0>;
32                         32-bit;
33                 };
34         };
35
36         memory {
37                 device_type = "memory";
38                 reg = <00000000 08000000>;
39         };
40
41         bcsr@f8000000 {
42                 device_type = "board-control";
43                 reg = <f8000000 8000>;
44         };
45
46         soc8323@e0000000 {
47                 #address-cells = <1>;
48                 #size-cells = <1>;
49                 #interrupt-cells = <2>;
50                 device_type = "soc";
51                 ranges = <0 e0000000 00100000>;
52                 reg = <e0000000 00000200>;
53                 bus-frequency = <7DE2900>;
54
55                 wdt@200 {
56                         device_type = "watchdog";
57                         compatible = "mpc83xx_wdt";
58                         reg = <200 100>;
59                 };
60
61                 i2c@3000 {
62                         device_type = "i2c";
63                         compatible = "fsl-i2c";
64                         reg = <3000 100>;
65                         interrupts = <e 8>;
66                         interrupt-parent = < &ipic >;
67                         dfsrr;
68                 };
69
70                 serial@4500 {
71                         device_type = "serial";
72                         compatible = "ns16550";
73                         reg = <4500 100>;
74                         clock-frequency = <0>;
75                         interrupts = <9 8>;
76                         interrupt-parent = < &ipic >;
77                 };
78
79                 serial@4600 {
80                         device_type = "serial";
81                         compatible = "ns16550";
82                         reg = <4600 100>;
83                         clock-frequency = <0>;
84                         interrupts = <a 8>;
85                         interrupt-parent = < &ipic >;
86                 };
87
88                 crypto@30000 {
89                         device_type = "crypto";
90                         model = "SEC2";
91                         compatible = "talitos";
92                         reg = <30000 7000>;
93                         interrupts = <b 8>;
94                         interrupt-parent = < &ipic >;
95                         /* Rev. 2.2 */
96                         num-channels = <1>;
97                         channel-fifo-len = <18>;
98                         exec-units-mask = <0000004c>;
99                         descriptor-types-mask = <0122003f>;
100                 };
101
102                 pci@8500 {
103                         interrupt-map-mask = <f800 0 0 7>;
104                         interrupt-map = <
105                                         /* IDSEL 0x11 AD17 */
106                                          8800 0 0 1 &ipic 14 8
107                                          8800 0 0 2 &ipic 15 8
108                                          8800 0 0 3 &ipic 16 8
109                                          8800 0 0 4 &ipic 17 8
110
111                                         /* IDSEL 0x12 AD18 */
112                                          9000 0 0 1 &ipic 16 8
113                                          9000 0 0 2 &ipic 17 8
114                                          9000 0 0 3 &ipic 14 8
115                                          9000 0 0 4 &ipic 15 8
116
117                                         /* IDSEL 0x13 AD19 */
118                                          9800 0 0 1 &ipic 17 8
119                                          9800 0 0 2 &ipic 14 8
120                                          9800 0 0 3 &ipic 15 8
121                                          9800 0 0 4 &ipic 16 8
122
123                                         /* IDSEL 0x15 AD21*/
124                                          a800 0 0 1 &ipic 14 8
125                                          a800 0 0 2 &ipic 15 8
126                                          a800 0 0 3 &ipic 16 8
127                                          a800 0 0 4 &ipic 17 8
128
129                                         /* IDSEL 0x16 AD22*/
130                                          b000 0 0 1 &ipic 17 8
131                                          b000 0 0 2 &ipic 14 8
132                                          b000 0 0 3 &ipic 15 8
133                                          b000 0 0 4 &ipic 16 8
134
135                                         /* IDSEL 0x17 AD23*/
136                                          b800 0 0 1 &ipic 16 8
137                                          b800 0 0 2 &ipic 17 8
138                                          b800 0 0 3 &ipic 14 8
139                                          b800 0 0 4 &ipic 15 8
140
141                                         /* IDSEL 0x18 AD24*/
142                                          c000 0 0 1 &ipic 15 8
143                                          c000 0 0 2 &ipic 16 8
144                                          c000 0 0 3 &ipic 17 8
145                                          c000 0 0 4 &ipic 14 8>;
146                         interrupt-parent = < &ipic >;
147                         interrupts = <42 8>;
148                         bus-range = <0 0>;
149                         ranges = <02000000 0 90000000 90000000 0 10000000
150                                   42000000 0 80000000 80000000 0 10000000
151                                   01000000 0 00000000 d0000000 0 00100000>;
152                         clock-frequency = <0>;
153                         #interrupt-cells = <1>;
154                         #size-cells = <2>;
155                         #address-cells = <3>;
156                         reg = <8500 100>;
157                         compatible = "83xx";
158                         device_type = "pci";
159                 };
160
161                 ipic: pic@700 {
162                         interrupt-controller;
163                         #address-cells = <0>;
164                         #interrupt-cells = <2>;
165                         reg = <700 100>;
166                         built-in;
167                         device_type = "ipic";
168                 };
169                 
170                 par_io@1400 {
171                         reg = <1400 100>;
172                         device_type = "par_io";
173                         num-ports = <7>;
174
175                         pio3: ucc_pin@03 {
176                                 pio-map = <
177                         /* port  pin  dir  open_drain  assignment  has_irq */
178                                         3  4  3  0  2  0  /* MDIO */
179                                         3  5  1  0  2  0  /* MDC */
180                                         0  d  2  0  1  0        /* RX_CLK (CLK9) */
181                                         3 18  2  0  1  0        /* TX_CLK (CLK10) */
182                                         1  1  1  0  1  0        /* TxD1 */
183                                         1  0  1  0  1  0        /* TxD0 */
184                                         1  1  1  0  1  0        /* TxD1 */
185                                         1  2  1  0  1  0        /* TxD2 */
186                                         1  3  1  0  1  0        /* TxD3 */
187                                         1  4  2  0  1  0        /* RxD0 */
188                                         1  5  2  0  1  0        /* RxD1 */
189                                         1  6  2  0  1  0        /* RxD2 */
190                                         1  7  2  0  1  0        /* RxD3 */
191                                         1  8  2  0  1  0        /* RX_ER */
192                                         1  9  1  0  1  0        /* TX_ER */
193                                         1  a  2  0  1  0        /* RX_DV */
194                                         1  b  2  0  1  0        /* COL */
195                                         1  c  1  0  1  0        /* TX_EN */
196                                         1  d  2  0  1  0>;/* CRS */
197                         };
198                         pio4: ucc_pin@04 {
199                                 pio-map = <
200                         /* port  pin  dir  open_drain  assignment  has_irq */
201                                         3 1f  2  0  1  0        /* RX_CLK (CLK7) */
202                                         3  6  2  0  1  0        /* TX_CLK (CLK8) */
203                                         1 12  1  0  1  0        /* TxD0 */
204                                         1 13  1  0  1  0        /* TxD1 */
205                                         1 14  1  0  1  0        /* TxD2 */
206                                         1 15  1  0  1  0        /* TxD3 */
207                                         1 16  2  0  1  0        /* RxD0 */
208                                         1 17  2  0  1  0        /* RxD1 */
209                                         1 18  2  0  1  0        /* RxD2 */
210                                         1 19  2  0  1  0        /* RxD3 */
211                                         1 1a  2  0  1  0        /* RX_ER */
212                                         1 1b  1  0  1  0        /* TX_ER */
213                                         1 1c  2  0  1  0        /* RX_DV */
214                                         1 1d  2  0  1  0        /* COL */
215                                         1 1e  1  0  1  0        /* TX_EN */
216                                         1 1f  2  0  1  0>;/* CRS */
217                         };
218                 };
219         };
220
221         qe@e0100000 {
222                 #address-cells = <1>;
223                 #size-cells = <1>;
224                 device_type = "qe";
225                 model = "QE";
226                 ranges = <0 e0100000 00100000>;
227                 reg = <e0100000 480>;
228                 brg-frequency = <0>;
229                 bus-frequency = <BCD3D80>;
230                 
231                 muram@10000 {
232                         device_type = "muram";
233                         ranges = <0 00010000 00004000>;
234         
235                         data-only@0 {
236                                 reg = <0 4000>;
237                         };
238                 };
239
240                 spi@4c0 {
241                         device_type = "spi";
242                         compatible = "fsl_spi";
243                         reg = <4c0 40>;
244                         interrupts = <2>;
245                         interrupt-parent = < &qeic >;
246                         mode = "cpu";
247                 };
248
249                 spi@500 {
250                         device_type = "spi";
251                         compatible = "fsl_spi";
252                         reg = <500 40>;
253                         interrupts = <1>;
254                         interrupt-parent = < &qeic >;
255                         mode = "cpu";
256                 };
257
258                 usb@6c0 {
259                         device_type = "usb";
260                         compatible = "qe_udc";
261                         reg = <6c0 40 8B00 100>;
262                         interrupts = <b>;
263                         interrupt-parent = < &qeic >;
264                         mode = "slave";
265                 };
266
267                 ucc@2200 {
268                         device_type = "network";
269                         compatible = "ucc_geth";
270                         model = "UCC";
271                         device-id = <3>;
272                         reg = <2200 200>;
273                         interrupts = <22>;
274                         interrupt-parent = < &qeic >;
275                         mac-address = [ 00 04 9f 00 23 23 ];
276                         rx-clock = <19>;
277                         tx-clock = <1a>;
278                         phy-handle = < &phy3 >;
279                         pio-handle = < &pio3 >;
280                 };
281
282                 ucc@3200 {
283                         device_type = "network";
284                         compatible = "ucc_geth";
285                         model = "UCC";
286                         device-id = <4>;
287                         reg = <3000 200>;
288                         interrupts = <23>;
289                         interrupt-parent = < &qeic >;
290                         mac-address = [ 00 11 22 33 44 55 ];
291                         rx-clock = <17>;
292                         tx-clock = <18>;
293                         phy-handle = < &phy4 >;
294                         pio-handle = < &pio4 >;
295                 };
296
297                 mdio@2320 {
298                         #address-cells = <1>;
299                         #size-cells = <0>;
300                         reg = <2320 18>;
301                         device_type = "mdio";
302                         compatible = "ucc_geth_phy";
303
304                         phy3: ethernet-phy@03 {
305                                 interrupt-parent = < &ipic >;
306                                 interrupts = <11 8>;
307                                 reg = <3>;
308                                 device_type = "ethernet-phy";
309                         };
310                         phy4: ethernet-phy@04 {
311                                 interrupt-parent = < &ipic >;
312                                 interrupts = <12 8>;
313                                 reg = <4>;
314                                 device_type = "ethernet-phy";
315                         };
316                 };
317
318                 qeic: qeic@80 {
319                         interrupt-controller;
320                         device_type = "qeic";
321                         #address-cells = <0>;
322                         #interrupt-cells = <1>;
323                         reg = <80 80>;
324                         built-in;
325                         big-endian;
326                         interrupts = <20 8 21 8>; //high:32 low:33
327                         interrupt-parent = < &ipic >;
328                 };
329         };
330 };