2 * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
3 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #include <linux/platform_device.h>
21 #include <linux/mtd/physmap.h>
22 #include <linux/mtd/plat-ram.h>
23 #include <asm/mach/arch.h>
24 #include <asm/mach-types.h>
25 #include <mach/common.h>
26 #include <mach/hardware.h>
27 #include <mach/iomux-mx1-mx2.h>
28 #include <asm/mach/time.h>
29 #include <mach/imx-uart.h>
30 #include <mach/board-pcm038.h>
31 #include <mach/mxc_nand.h>
36 * Phytec's PCM038 comes with 2MiB battery buffered SRAM,
40 static struct platdata_mtd_ram pcm038_sram_data = {
44 static struct resource pcm038_sram_resource = {
45 .start = CS1_BASE_ADDR,
46 .end = CS1_BASE_ADDR + 512 * 1024 - 1,
47 .flags = IORESOURCE_MEM,
50 static struct platform_device pcm038_sram_mtd_device = {
54 .platform_data = &pcm038_sram_data,
57 .resource = &pcm038_sram_resource,
61 * Phytec's phyCORE-i.MX27 comes with 32MiB flash,
64 static struct physmap_flash_data pcm038_flash_data = {
68 static struct resource pcm038_flash_resource = {
71 .flags = IORESOURCE_MEM,
74 static struct platform_device pcm038_nor_mtd_device = {
75 .name = "physmap-flash",
78 .platform_data = &pcm038_flash_data,
81 .resource = &pcm038_flash_resource,
84 static int mxc_uart0_pins[] = {
91 static int uart_mxc_port0_init(struct platform_device *pdev)
93 return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
94 ARRAY_SIZE(mxc_uart0_pins), "UART0");
97 static int uart_mxc_port0_exit(struct platform_device *pdev)
99 mxc_gpio_release_multiple_pins(mxc_uart0_pins,
100 ARRAY_SIZE(mxc_uart0_pins));
104 static int mxc_uart1_pins[] = {
111 static int uart_mxc_port1_init(struct platform_device *pdev)
113 return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
114 ARRAY_SIZE(mxc_uart1_pins), "UART1");
117 static int uart_mxc_port1_exit(struct platform_device *pdev)
119 mxc_gpio_release_multiple_pins(mxc_uart1_pins,
120 ARRAY_SIZE(mxc_uart1_pins));
124 static int mxc_uart2_pins[] = { PE10_PF_UART3_CTS,
129 static int uart_mxc_port2_init(struct platform_device *pdev)
131 return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
132 ARRAY_SIZE(mxc_uart2_pins), "UART2");
135 static int uart_mxc_port2_exit(struct platform_device *pdev)
137 mxc_gpio_release_multiple_pins(mxc_uart2_pins,
138 ARRAY_SIZE(mxc_uart2_pins));
142 static struct imxuart_platform_data uart_pdata[] = {
144 .init = uart_mxc_port0_init,
145 .exit = uart_mxc_port0_exit,
146 .flags = IMXUART_HAVE_RTSCTS,
148 .init = uart_mxc_port1_init,
149 .exit = uart_mxc_port1_exit,
150 .flags = IMXUART_HAVE_RTSCTS,
152 .init = uart_mxc_port2_init,
153 .exit = uart_mxc_port2_exit,
154 .flags = IMXUART_HAVE_RTSCTS,
158 static int mxc_fec_pins[] = {
170 PD11_AOUT_FEC_TX_CLK,
179 static void gpio_fec_active(void)
181 mxc_gpio_setup_multiple_pins(mxc_fec_pins,
182 ARRAY_SIZE(mxc_fec_pins), "FEC");
185 static void gpio_fec_inactive(void)
187 mxc_gpio_release_multiple_pins(mxc_fec_pins,
188 ARRAY_SIZE(mxc_fec_pins));
191 static struct mxc_nand_platform_data pcm038_nand_board_info = {
196 static struct platform_device *platform_devices[] __initdata = {
197 &pcm038_nor_mtd_device,
198 &mxc_w1_master_device,
199 &pcm038_sram_mtd_device,
202 /* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
203 * setup other stuffs to access the sram. */
204 static void __init pcm038_init_sram(void)
206 __raw_writel(0x0000d843, CSCR_U(1));
207 __raw_writel(0x22252521, CSCR_L(1));
208 __raw_writel(0x22220a00, CSCR_A(1));
211 static void __init pcm038_init(void)
216 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
217 mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
218 mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
220 mxc_gpio_mode(PE16_AF_RTCK); /* OWIRE */
221 mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info);
223 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
225 #ifdef CONFIG_MACH_PCM970_BASEBOARD
226 pcm970_baseboard_init();
230 static void __init pcm038_timer_init(void)
232 mxc_clocks_init(26000000);
233 mxc_timer_init("gpt_clk.0");
236 struct sys_timer pcm038_timer = {
237 .init = pcm038_timer_init,
240 MACHINE_START(PCM038, "phyCORE-i.MX27")
241 .phys_io = AIPI_BASE_ADDR,
242 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
243 .boot_params = PHYS_OFFSET + 0x100,
244 .map_io = mxc_map_io,
245 .init_irq = mxc_init_irq,
246 .init_machine = pcm038_init,
247 .timer = &pcm038_timer,