git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/bcm43xx/bcm43xx_main.c

   1 /*
   2
   3   Broadcom BCM43xx wireless driver
   4
   5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
   6                      Stefano Brivio <st3@riseup.net>
   7                      Michael Buesch <mbuesch@freenet.de>
   8                      Danny van Dyk <kugelfang@gentoo.org>
   9                      Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10
  11   Some parts of the code in this file are derived from the ipw2200
  12   driver  Copyright(c) 2003 - 2004 Intel Corporation.
  13
  14   This program is free software; you can redistribute it and/or modify
  15   it under the terms of the GNU General Public License as published by
  16   the Free Software Foundation; either version 2 of the License, or
  17   (at your option) any later version.
  18
  19   This program is distributed in the hope that it will be useful,
  20   but WITHOUT ANY WARRANTY; without even the implied warranty of
  21   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22   GNU General Public License for more details.
  23
  24   You should have received a copy of the GNU General Public License
  25   along with this program; see the file COPYING.  If not, write to
  26   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  27   Boston, MA 02110-1301, USA.
  28
  29 */
  30
  31 #include <linux/delay.h>
  32 #include <linux/init.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/if_arp.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/version.h>
  37 #include <linux/firmware.h>
  38 #include <linux/wireless.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/dma-mapping.h>
  42 #include <net/iw_handler.h>
  43
  44 #include "bcm43xx.h"
  45 #include "bcm43xx_main.h"
  46 #include "bcm43xx_debugfs.h"
  47 #include "bcm43xx_radio.h"
  48 #include "bcm43xx_phy.h"
  49 #include "bcm43xx_dma.h"
  50 #include "bcm43xx_pio.h"
  51 #include "bcm43xx_power.h"
  52 #include "bcm43xx_wx.h"
  53 #include "bcm43xx_ethtool.h"
  54 #include "bcm43xx_xmit.h"
  55 #include "bcm43xx_sysfs.h"
  56
  57
  58 MODULE_DESCRIPTION("Broadcom BCM43xx wireless driver");
  59 MODULE_AUTHOR("Martin Langer");
  60 MODULE_AUTHOR("Stefano Brivio");
  61 MODULE_AUTHOR("Michael Buesch");
  62 MODULE_LICENSE("GPL");
  63
  64 #ifdef CONFIG_BCM947XX
  65 extern char *nvram_get(char *name);
  66 #endif
  67
  68 #if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO)
  69 static int modparam_pio;
  70 module_param_named(pio, modparam_pio, int, 0444);
  71 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
  72 #elif defined(CONFIG_BCM43XX_DMA)
  73 # define modparam_pio   0
  74 #elif defined(CONFIG_BCM43XX_PIO)
  75 # define modparam_pio   1
  76 #endif
  77
  78 static int modparam_bad_frames_preempt;
  79 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  80 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames Preemption");
  81
  82 static int modparam_short_retry = BCM43xx_DEFAULT_SHORT_RETRY_LIMIT;
  83 module_param_named(short_retry, modparam_short_retry, int, 0444);
  84 MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
  85
  86 static int modparam_long_retry = BCM43xx_DEFAULT_LONG_RETRY_LIMIT;
  87 module_param_named(long_retry, modparam_long_retry, int, 0444);
  88 MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
  89
  90 static int modparam_locale = -1;
  91 module_param_named(locale, modparam_locale, int, 0444);
  92 MODULE_PARM_DESC(country, "Select LocaleCode 0-11 (For travelers)");
  93
  94 static int modparam_noleds;
  95 module_param_named(noleds, modparam_noleds, int, 0444);
  96 MODULE_PARM_DESC(noleds, "Turn off all LED activity");
  97
  98 #ifdef CONFIG_BCM43XX_DEBUG
  99 static char modparam_fwpostfix[64];
 100 module_param_string(fwpostfix, modparam_fwpostfix, 64, 0444);
 101 MODULE_PARM_DESC(fwpostfix, "Postfix for .fw files. Useful for debugging.");
 102 #else
 103 # define modparam_fwpostfix  ""
 104 #endif /* CONFIG_BCM43XX_DEBUG*/
 105
 106
 107 /* If you want to debug with just a single device, enable this,
 108  * where the string is the pci device ID (as given by the kernel's
 109  * pci_name function) of the device to be used.
 110  */
 111 //#define DEBUG_SINGLE_DEVICE_ONLY      "0001:11:00.0"
 112
 113 /* If you want to enable printing of each MMIO access, enable this. */
 114 //#define DEBUG_ENABLE_MMIO_PRINT
 115
 116 /* If you want to enable printing of MMIO access within
 117  * ucode/pcm upload, initvals write, enable this.
 118  */
 119 //#define DEBUG_ENABLE_UCODE_MMIO_PRINT
 120
 121 /* If you want to enable printing of PCI Config Space access, enable this */
 122 //#define DEBUG_ENABLE_PCILOG
 123
 124
 125 /* Detailed list maintained at:
 126  * http://openfacts.berlios.de/index-en.phtml?title=Bcm43xxDevices
 127  */
 128         static struct pci_device_id bcm43xx_pci_tbl[] = {
 129         /* Broadcom 4303 802.11b */
 130         { PCI_VENDOR_ID_BROADCOM, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 131                 /* Broadcom 4307 802.11b */
 132         { PCI_VENDOR_ID_BROADCOM, 0x4307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 133                 /* Broadcom 4318 802.11b/g */
 134         { PCI_VENDOR_ID_BROADCOM, 0x4318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 135         /* Broadcom 4306 802.11b/g */
 136         { PCI_VENDOR_ID_BROADCOM, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 137                 /* Broadcom 4306 802.11a */
 138 //      { PCI_VENDOR_ID_BROADCOM, 0x4321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 139         /* Broadcom 4309 802.11a/b/g */
 140         { PCI_VENDOR_ID_BROADCOM, 0x4324, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 141         /* Broadcom 43XG 802.11b/g */
 142         { PCI_VENDOR_ID_BROADCOM, 0x4325, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 143 #ifdef CONFIG_BCM947XX
 144         /* SB bus on BCM947xx */
 145         { PCI_VENDOR_ID_BROADCOM, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 146 #endif
 147         { 0 },
 148 };
 149 MODULE_DEVICE_TABLE(pci, bcm43xx_pci_tbl);
 150
 151 static void bcm43xx_ram_write(struct bcm43xx_private *bcm, u16 offset, u32 val)
 152 {
 153         u32 status;
 154
 155         status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
 156         if (!(status & BCM43xx_SBF_XFER_REG_BYTESWAP))
 157                 val = swab32(val);
 158
 159         bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_CONTROL, offset);
 160         mmiowb();
 161         bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_DATA, val);
 162 }
 163
 164 static inline
 165 void bcm43xx_shm_control_word(struct bcm43xx_private *bcm,
 166                               u16 routing, u16 offset)
 167 {
 168         u32 control;
 169
 170         /* "offset" is the WORD offset. */
 171
 172         control = routing;
 173         control <<= 16;
 174         control |= offset;
 175         bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_CONTROL, control);
 176 }
 177
 178 u32 bcm43xx_shm_read32(struct bcm43xx_private *bcm,
 179                        u16 routing, u16 offset)
 180 {
 181         u32 ret;
 182
 183         if (routing == BCM43xx_SHM_SHARED) {
 184                 if (offset & 0x0003) {
 185                         /* Unaligned access */
 186                         bcm43xx_shm_control_word(bcm, routing, offset >> 2);
 187                         ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
 188                         ret <<= 16;
 189                         bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
 190                         ret |= bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
 191
 192                         return ret;
 193                 }
 194                 offset >>= 2;
 195         }
 196         bcm43xx_shm_control_word(bcm, routing, offset);
 197         ret = bcm43xx_read32(bcm, BCM43xx_MMIO_SHM_DATA);
 198
 199         return ret;
 200 }
 201
 202 u16 bcm43xx_shm_read16(struct bcm43xx_private *bcm,
 203                        u16 routing, u16 offset)
 204 {
 205         u16 ret;
 206
 207         if (routing == BCM43xx_SHM_SHARED) {
 208                 if (offset & 0x0003) {
 209                         /* Unaligned access */
 210                         bcm43xx_shm_control_word(bcm, routing, offset >> 2);
 211                         ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
 212
 213                         return ret;
 214                 }
 215                 offset >>= 2;
 216         }
 217         bcm43xx_shm_control_word(bcm, routing, offset);
 218         ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
 219
 220         return ret;
 221 }
 222
 223 void bcm43xx_shm_write32(struct bcm43xx_private *bcm,
 224                          u16 routing, u16 offset,
 225                          u32 value)
 226 {
 227         if (routing == BCM43xx_SHM_SHARED) {
 228                 if (offset & 0x0003) {
 229                         /* Unaligned access */
 230                         bcm43xx_shm_control_word(bcm, routing, offset >> 2);
 231                         mmiowb();
 232                         bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
 233                                         (value >> 16) & 0xffff);
 234                         mmiowb();
 235                         bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
 236                         mmiowb();
 237                         bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA,
 238                                         value & 0xffff);
 239                         return;
 240                 }
 241                 offset >>= 2;
 242         }
 243         bcm43xx_shm_control_word(bcm, routing, offset);
 244         mmiowb();
 245         bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, value);
 246 }
 247
 248 void bcm43xx_shm_write16(struct bcm43xx_private *bcm,
 249                          u16 routing, u16 offset,
 250                          u16 value)
 251 {
 252         if (routing == BCM43xx_SHM_SHARED) {
 253                 if (offset & 0x0003) {
 254                         /* Unaligned access */
 255                         bcm43xx_shm_control_word(bcm, routing, offset >> 2);
 256                         mmiowb();
 257                         bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
 258                                         value);
 259                         return;
 260                 }
 261                 offset >>= 2;
 262         }
 263         bcm43xx_shm_control_word(bcm, routing, offset);
 264         mmiowb();
 265         bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA, value);
 266 }
 267
 268 void bcm43xx_tsf_read(struct bcm43xx_private *bcm, u64 *tsf)
 269 {
 270         /* We need to be careful. As we read the TSF from multiple
 271          * registers, we should take care of register overflows.
 272          * In theory, the whole tsf read process should be atomic.
 273          * We try to be atomic here, by restaring the read process,
 274          * if any of the high registers changed (overflew).
 275          */
 276         if (bcm->current_core->rev >= 3) {
 277                 u32 low, high, high2;
 278
 279                 do {
 280                         high = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
 281                         low = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW);
 282                         high2 = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
 283                 } while (unlikely(high != high2));
 284
 285                 *tsf = high;
 286                 *tsf <<= 32;
 287                 *tsf |= low;
 288         } else {
 289                 u64 tmp;
 290                 u16 v0, v1, v2, v3;
 291                 u16 test1, test2, test3;
 292
 293                 do {
 294                         v3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
 295                         v2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
 296                         v1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
 297                         v0 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_0);
 298
 299                         test3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
 300                         test2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
 301                         test1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
 302                 } while (v3 != test3 || v2 != test2 || v1 != test1);
 303
 304                 *tsf = v3;
 305                 *tsf <<= 48;
 306                 tmp = v2;
 307                 tmp <<= 32;
 308                 *tsf |= tmp;
 309                 tmp = v1;
 310                 tmp <<= 16;
 311                 *tsf |= tmp;
 312                 *tsf |= v0;
 313         }
 314 }
 315
 316 void bcm43xx_tsf_write(struct bcm43xx_private *bcm, u64 tsf)
 317 {
 318         u32 status;
 319
 320         status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
 321         status |= BCM43xx_SBF_TIME_UPDATE;
 322         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
 323         mmiowb();
 324
 325         /* Be careful with the in-progress timer.
 326          * First zero out the low register, so we have a full
 327          * register-overflow duration to complete the operation.
 328          */
 329         if (bcm->current_core->rev >= 3) {
 330                 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
 331                 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
 332
 333                 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, 0);
 334                 mmiowb();
 335                 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH, hi);
 336                 mmiowb();
 337                 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, lo);
 338         } else {
 339                 u16 v0 = (tsf & 0x000000000000FFFFULL);
 340                 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
 341                 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
 342                 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
 343
 344                 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, 0);
 345                 mmiowb();
 346                 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_3, v3);
 347                 mmiowb();
 348                 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_2, v2);
 349                 mmiowb();
 350                 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_1, v1);
 351                 mmiowb();
 352                 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, v0);
 353         }
 354
 355         status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
 356         status &= ~BCM43xx_SBF_TIME_UPDATE;
 357         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
 358 }
 359
 360 static
 361 void bcm43xx_macfilter_set(struct bcm43xx_private *bcm,
 362                            u16 offset,
 363                            const u8 *mac)
 364 {
 365         u16 data;
 366
 367         offset |= 0x0020;
 368         bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_CONTROL, offset);
 369
 370         data = mac[0];
 371         data |= mac[1] << 8;
 372         bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
 373         data = mac[2];
 374         data |= mac[3] << 8;
 375         bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
 376         data = mac[4];
 377         data |= mac[5] << 8;
 378         bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
 379 }
 380
 381 static void bcm43xx_macfilter_clear(struct bcm43xx_private *bcm,
 382                                     u16 offset)
 383 {
 384         const u8 zero_addr[ETH_ALEN] = { 0 };
 385
 386         bcm43xx_macfilter_set(bcm, offset, zero_addr);
 387 }
 388
 389 static void bcm43xx_write_mac_bssid_templates(struct bcm43xx_private *bcm)
 390 {
 391         const u8 *mac = (const u8 *)(bcm->net_dev->dev_addr);
 392         const u8 *bssid = (const u8 *)(bcm->ieee->bssid);
 393         u8 mac_bssid[ETH_ALEN * 2];
 394         int i;
 395
 396         memcpy(mac_bssid, mac, ETH_ALEN);
 397         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
 398
 399         /* Write our MAC address and BSSID to template ram */
 400         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
 401                 bcm43xx_ram_write(bcm, 0x20 + i, *((u32 *)(mac_bssid + i)));
 402         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
 403                 bcm43xx_ram_write(bcm, 0x78 + i, *((u32 *)(mac_bssid + i)));
 404         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
 405                 bcm43xx_ram_write(bcm, 0x478 + i, *((u32 *)(mac_bssid + i)));
 406 }
 407
 408 //FIXME: Well, we should probably call them from somewhere.
 409 #if 0
 410 static void bcm43xx_set_slot_time(struct bcm43xx_private *bcm, u16 slot_time)
 411 {
 412         /* slot_time is in usec. */
 413         if (bcm43xx_current_phy(bcm)->type != BCM43xx_PHYTYPE_G)
 414                 return;
 415         bcm43xx_write16(bcm, 0x684, 510 + slot_time);
 416         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0010, slot_time);
 417 }
 418
 419 static void bcm43xx_short_slot_timing_enable(struct bcm43xx_private *bcm)
 420 {
 421         bcm43xx_set_slot_time(bcm, 9);
 422 }
 423
 424 static void bcm43xx_short_slot_timing_disable(struct bcm43xx_private *bcm)
 425 {
 426         bcm43xx_set_slot_time(bcm, 20);
 427 }
 428 #endif
 429
 430 /* FIXME: To get the MAC-filter working, we need to implement the
 431  *        following functions (and rename them :)
 432  */
 433 #if 0
 434 static void bcm43xx_disassociate(struct bcm43xx_private *bcm)
 435 {
 436         bcm43xx_mac_suspend(bcm);
 437         bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
 438
 439         bcm43xx_ram_write(bcm, 0x0026, 0x0000);
 440         bcm43xx_ram_write(bcm, 0x0028, 0x0000);
 441         bcm43xx_ram_write(bcm, 0x007E, 0x0000);
 442         bcm43xx_ram_write(bcm, 0x0080, 0x0000);
 443         bcm43xx_ram_write(bcm, 0x047E, 0x0000);
 444         bcm43xx_ram_write(bcm, 0x0480, 0x0000);
 445
 446         if (bcm->current_core->rev < 3) {
 447                 bcm43xx_write16(bcm, 0x0610, 0x8000);
 448                 bcm43xx_write16(bcm, 0x060E, 0x0000);
 449         } else
 450                 bcm43xx_write32(bcm, 0x0188, 0x80000000);
 451
 452         bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
 453
 454         if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G &&
 455             ieee80211_is_ofdm_rate(bcm->softmac->txrates.default_rate))
 456                 bcm43xx_short_slot_timing_enable(bcm);
 457
 458         bcm43xx_mac_enable(bcm);
 459 }
 460
 461 static void bcm43xx_associate(struct bcm43xx_private *bcm,
 462                               const u8 *mac)
 463 {
 464         memcpy(bcm->ieee->bssid, mac, ETH_ALEN);
 465
 466         bcm43xx_mac_suspend(bcm);
 467         bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_ASSOC, mac);
 468         bcm43xx_write_mac_bssid_templates(bcm);
 469         bcm43xx_mac_enable(bcm);
 470 }
 471 #endif
 472
 473 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
 474  * Returns the _previously_ enabled IRQ mask.
 475  */
 476 static inline u32 bcm43xx_interrupt_enable(struct bcm43xx_private *bcm, u32 mask)
 477 {
 478         u32 old_mask;
 479
 480         old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
 481         bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask | mask);
 482
 483         return old_mask;
 484 }
 485
 486 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
 487  * Returns the _previously_ enabled IRQ mask.
 488  */
 489 static inline u32 bcm43xx_interrupt_disable(struct bcm43xx_private *bcm, u32 mask)
 490 {
 491         u32 old_mask;
 492
 493         old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
 494         bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
 495
 496         return old_mask;
 497 }
 498
 499 /* Make sure we don't receive more data from the device. */
 500 static int bcm43xx_disable_interrupts_sync(struct bcm43xx_private *bcm, u32 *oldstate)
 501 {
 502         u32 old;
 503         unsigned long flags;
 504
 505         bcm43xx_lock_mmio(bcm, flags);
 506         if (bcm43xx_is_initializing(bcm) || bcm->shutting_down) {
 507                 bcm43xx_unlock_mmio(bcm, flags);
 508                 return -EBUSY;
 509         }
 510         old = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
 511         tasklet_disable(&bcm->isr_tasklet);
 512         bcm43xx_unlock_mmio(bcm, flags);
 513         if (oldstate)
 514                 *oldstate = old;
 515
 516         return 0;
 517 }
 518
 519 static int bcm43xx_read_radioinfo(struct bcm43xx_private *bcm)
 520 {
 521         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
 522         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
 523         u32 radio_id;
 524         u16 manufact;
 525         u16 version;
 526         u8 revision;
 527         s8 i;
 528
 529         if (bcm->chip_id == 0x4317) {
 530                 if (bcm->chip_rev == 0x00)
 531                         radio_id = 0x3205017F;
 532                 else if (bcm->chip_rev == 0x01)
 533                         radio_id = 0x4205017F;
 534                 else
 535                         radio_id = 0x5205017F;
 536         } else {
 537                 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
 538                 radio_id = bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_HIGH);
 539                 radio_id <<= 16;
 540                 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
 541                 radio_id |= bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_LOW);
 542         }
 543
 544         manufact = (radio_id & 0x00000FFF);
 545         version = (radio_id & 0x0FFFF000) >> 12;
 546         revision = (radio_id & 0xF0000000) >> 28;
 547
 548         dprintk(KERN_INFO PFX "Detected Radio: ID: %x (Manuf: %x Ver: %x Rev: %x)\n",
 549                 radio_id, manufact, version, revision);
 550
 551         switch (phy->type) {
 552         case BCM43xx_PHYTYPE_A:
 553                 if ((version != 0x2060) || (revision != 1) || (manufact != 0x17f))
 554                         goto err_unsupported_radio;
 555                 break;
 556         case BCM43xx_PHYTYPE_B:
 557                 if ((version & 0xFFF0) != 0x2050)
 558                         goto err_unsupported_radio;
 559                 break;
 560         case BCM43xx_PHYTYPE_G:
 561                 if (version != 0x2050)
 562                         goto err_unsupported_radio;
 563                 break;
 564         }
 565
 566         radio->manufact = manufact;
 567         radio->version = version;
 568         radio->revision = revision;
 569
 570         /* Set default attenuation values. */
 571         radio->baseband_atten = bcm43xx_default_baseband_attenuation(bcm);
 572         radio->radio_atten = bcm43xx_default_radio_attenuation(bcm);
 573         radio->txctl1 = bcm43xx_default_txctl1(bcm);
 574         radio->txctl2 = 0xFFFF;
 575         if (phy->type == BCM43xx_PHYTYPE_A)
 576                 radio->txpower_desired = bcm->sprom.maxpower_aphy;
 577         else
 578                 radio->txpower_desired = bcm->sprom.maxpower_bgphy;
 579
 580         /* Initialize the in-memory nrssi Lookup Table. */
 581         for (i = 0; i < 64; i++)
 582                 radio->nrssi_lt[i] = i;
 583
 584         return 0;
 585
 586 err_unsupported_radio:
 587         printk(KERN_ERR PFX "Unsupported Radio connected to the PHY!\n");
 588         return -ENODEV;
 589 }
 590
 591 static const char * bcm43xx_locale_iso(u8 locale)
 592 {
 593         /* ISO 3166-1 country codes.
 594          * Note that there aren't ISO 3166-1 codes for
 595          * all or locales. (Not all locales are countries)
 596          */
 597         switch (locale) {
 598         case BCM43xx_LOCALE_WORLD:
 599         case BCM43xx_LOCALE_ALL:
 600                 return "XX";
 601         case BCM43xx_LOCALE_THAILAND:
 602                 return "TH";
 603         case BCM43xx_LOCALE_ISRAEL:
 604                 return "IL";
 605         case BCM43xx_LOCALE_JORDAN:
 606                 return "JO";
 607         case BCM43xx_LOCALE_CHINA:
 608                 return "CN";
 609         case BCM43xx_LOCALE_JAPAN:
 610         case BCM43xx_LOCALE_JAPAN_HIGH:
 611                 return "JP";
 612         case BCM43xx_LOCALE_USA_CANADA_ANZ:
 613         case BCM43xx_LOCALE_USA_LOW:
 614                 return "US";
 615         case BCM43xx_LOCALE_EUROPE:
 616                 return "EU";
 617         case BCM43xx_LOCALE_NONE:
 618                 return "  ";
 619         }
 620         assert(0);
 621         return "  ";
 622 }
 623
 624 static const char * bcm43xx_locale_string(u8 locale)
 625 {
 626         switch (locale) {
 627         case BCM43xx_LOCALE_WORLD:
 628                 return "World";
 629         case BCM43xx_LOCALE_THAILAND:
 630                 return "Thailand";
 631         case BCM43xx_LOCALE_ISRAEL:
 632                 return "Israel";
 633         case BCM43xx_LOCALE_JORDAN:
 634                 return "Jordan";
 635         case BCM43xx_LOCALE_CHINA:
 636                 return "China";
 637         case BCM43xx_LOCALE_JAPAN:
 638                 return "Japan";
 639         case BCM43xx_LOCALE_USA_CANADA_ANZ:
 640                 return "USA/Canada/ANZ";
 641         case BCM43xx_LOCALE_EUROPE:
 642                 return "Europe";
 643         case BCM43xx_LOCALE_USA_LOW:
 644                 return "USAlow";
 645         case BCM43xx_LOCALE_JAPAN_HIGH:
 646                 return "JapanHigh";
 647         case BCM43xx_LOCALE_ALL:
 648                 return "All";
 649         case BCM43xx_LOCALE_NONE:
 650                 return "None";
 651         }
 652         assert(0);
 653         return "";
 654 }
 655
 656 static inline u8 bcm43xx_crc8(u8 crc, u8 data)
 657 {
 658         static const u8 t[] = {
 659                 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
 660                 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
 661                 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
 662                 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
 663                 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
 664                 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
 665                 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
 666                 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
 667                 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
 668                 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
 669                 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
 670                 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
 671                 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
 672                 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
 673                 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
 674                 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
 675                 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
 676                 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
 677                 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
 678                 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
 679                 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
 680                 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
 681                 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
 682                 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
 683                 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
 684                 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
 685                 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
 686                 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
 687                 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
 688                 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
 689                 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
 690                 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
 691         };
 692         return t[crc ^ data];
 693 }
 694
 695 static u8 bcm43xx_sprom_crc(const u16 *sprom)
 696 {
 697         int word;
 698         u8 crc = 0xFF;
 699
 700         for (word = 0; word < BCM43xx_SPROM_SIZE - 1; word++) {
 701                 crc = bcm43xx_crc8(crc, sprom[word] & 0x00FF);
 702                 crc = bcm43xx_crc8(crc, (sprom[word] & 0xFF00) >> 8);
 703         }
 704         crc = bcm43xx_crc8(crc, sprom[BCM43xx_SPROM_VERSION] & 0x00FF);
 705         crc ^= 0xFF;
 706
 707         return crc;
 708 }
 709
 710 int bcm43xx_sprom_read(struct bcm43xx_private *bcm, u16 *sprom)
 711 {
 712         int i;
 713         u8 crc, expected_crc;
 714
 715         for (i = 0; i < BCM43xx_SPROM_SIZE; i++)
 716                 sprom[i] = bcm43xx_read16(bcm, BCM43xx_SPROM_BASE + (i * 2));
 717         /* CRC-8 check. */
 718         crc = bcm43xx_sprom_crc(sprom);
 719         expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
 720         if (crc != expected_crc) {
 721                 printk(KERN_WARNING PFX "WARNING: Invalid SPROM checksum "
 722                                         "(0x%02X, expected: 0x%02X)\n",
 723                        crc, expected_crc);
 724                 return -EINVAL;
 725         }
 726
 727         return 0;
 728 }
 729
 730 int bcm43xx_sprom_write(struct bcm43xx_private *bcm, const u16 *sprom)
 731 {
 732         int i, err;
 733         u8 crc, expected_crc;
 734         u32 spromctl;
 735
 736         /* CRC-8 validation of the input data. */
 737         crc = bcm43xx_sprom_crc(sprom);
 738         expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
 739         if (crc != expected_crc) {
 740                 printk(KERN_ERR PFX "SPROM input data: Invalid CRC\n");
 741                 return -EINVAL;
 742         }
 743
 744         printk(KERN_INFO PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
 745         err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_SPROMCTL, &spromctl);
 746         if (err)
 747                 goto err_ctlreg;
 748         spromctl |= 0x10; /* SPROM WRITE enable. */
 749         bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
 750         if (err)
 751                 goto err_ctlreg;
 752         /* We must burn lots of CPU cycles here, but that does not
 753          * really matter as one does not write the SPROM every other minute...
 754          */
 755         printk(KERN_INFO PFX "[ 0%%");
 756         mdelay(500);
 757         for (i = 0; i < BCM43xx_SPROM_SIZE; i++) {
 758                 if (i == 16)
 759                         printk("25%%");
 760                 else if (i == 32)
 761                         printk("50%%");
 762                 else if (i == 48)
 763                         printk("75%%");
 764                 else if (i % 2)
 765                         printk(".");
 766                 bcm43xx_write16(bcm, BCM43xx_SPROM_BASE + (i * 2), sprom[i]);
 767                 mmiowb();
 768                 mdelay(20);
 769         }
 770         spromctl &= ~0x10; /* SPROM WRITE enable. */
 771         bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
 772         if (err)
 773                 goto err_ctlreg;
 774         mdelay(500);
 775         printk("100%% ]\n");
 776         printk(KERN_INFO PFX "SPROM written.\n");
 777         bcm43xx_controller_restart(bcm, "SPROM update");
 778
 779         return 0;
 780 err_ctlreg:
 781         printk(KERN_ERR PFX "Could not access SPROM control register.\n");
 782         return -ENODEV;
 783 }
 784
 785 static int bcm43xx_sprom_extract(struct bcm43xx_private *bcm)
 786 {
 787         u16 value;
 788         u16 *sprom;
 789 #ifdef CONFIG_BCM947XX
 790         char *c;
 791 #endif
 792
 793         sprom = kzalloc(BCM43xx_SPROM_SIZE * sizeof(u16),
 794                         GFP_KERNEL);
 795         if (!sprom) {
 796                 printk(KERN_ERR PFX "sprom_extract OOM\n");
 797                 return -ENOMEM;
 798         }
 799 #ifdef CONFIG_BCM947XX
 800         sprom[BCM43xx_SPROM_BOARDFLAGS2] = atoi(nvram_get("boardflags2"));
 801         sprom[BCM43xx_SPROM_BOARDFLAGS] = atoi(nvram_get("boardflags"));
 802
 803         if ((c = nvram_get("il0macaddr")) != NULL)
 804                 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_IL0MACADDR]));
 805
 806         if ((c = nvram_get("et1macaddr")) != NULL)
 807                 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_ET1MACADDR]));
 808
 809         sprom[BCM43xx_SPROM_PA0B0] = atoi(nvram_get("pa0b0"));
 810         sprom[BCM43xx_SPROM_PA0B1] = atoi(nvram_get("pa0b1"));
 811         sprom[BCM43xx_SPROM_PA0B2] = atoi(nvram_get("pa0b2"));
 812
 813         sprom[BCM43xx_SPROM_PA1B0] = atoi(nvram_get("pa1b0"));
 814         sprom[BCM43xx_SPROM_PA1B1] = atoi(nvram_get("pa1b1"));
 815         sprom[BCM43xx_SPROM_PA1B2] = atoi(nvram_get("pa1b2"));
 816
 817         sprom[BCM43xx_SPROM_BOARDREV] = atoi(nvram_get("boardrev"));
 818 #else
 819         bcm43xx_sprom_read(bcm, sprom);
 820 #endif
 821
 822         /* boardflags2 */
 823         value = sprom[BCM43xx_SPROM_BOARDFLAGS2];
 824         bcm->sprom.boardflags2 = value;
 825
 826         /* il0macaddr */
 827         value = sprom[BCM43xx_SPROM_IL0MACADDR + 0];
 828         *(((u16 *)bcm->sprom.il0macaddr) + 0) = cpu_to_be16(value);
 829         value = sprom[BCM43xx_SPROM_IL0MACADDR + 1];
 830         *(((u16 *)bcm->sprom.il0macaddr) + 1) = cpu_to_be16(value);
 831         value = sprom[BCM43xx_SPROM_IL0MACADDR + 2];
 832         *(((u16 *)bcm->sprom.il0macaddr) + 2) = cpu_to_be16(value);
 833
 834         /* et0macaddr */
 835         value = sprom[BCM43xx_SPROM_ET0MACADDR + 0];
 836         *(((u16 *)bcm->sprom.et0macaddr) + 0) = cpu_to_be16(value);
 837         value = sprom[BCM43xx_SPROM_ET0MACADDR + 1];
 838         *(((u16 *)bcm->sprom.et0macaddr) + 1) = cpu_to_be16(value);
 839         value = sprom[BCM43xx_SPROM_ET0MACADDR + 2];
 840         *(((u16 *)bcm->sprom.et0macaddr) + 2) = cpu_to_be16(value);
 841
 842         /* et1macaddr */
 843         value = sprom[BCM43xx_SPROM_ET1MACADDR + 0];
 844         *(((u16 *)bcm->sprom.et1macaddr) + 0) = cpu_to_be16(value);
 845         value = sprom[BCM43xx_SPROM_ET1MACADDR + 1];
 846         *(((u16 *)bcm->sprom.et1macaddr) + 1) = cpu_to_be16(value);
 847         value = sprom[BCM43xx_SPROM_ET1MACADDR + 2];
 848         *(((u16 *)bcm->sprom.et1macaddr) + 2) = cpu_to_be16(value);
 849
 850         /* ethernet phy settings */
 851         value = sprom[BCM43xx_SPROM_ETHPHY];
 852         bcm->sprom.et0phyaddr = (value & 0x001F);
 853         bcm->sprom.et1phyaddr = (value & 0x03E0) >> 5;
 854         bcm->sprom.et0mdcport = (value & (1 << 14)) >> 14;
 855         bcm->sprom.et1mdcport = (value & (1 << 15)) >> 15;
 856
 857         /* boardrev, antennas, locale */
 858         value = sprom[BCM43xx_SPROM_BOARDREV];
 859         bcm->sprom.boardrev = (value & 0x00FF);
 860         bcm->sprom.locale = (value & 0x0F00) >> 8;
 861         bcm->sprom.antennas_aphy = (value & 0x3000) >> 12;
 862         bcm->sprom.antennas_bgphy = (value & 0xC000) >> 14;
 863         if (modparam_locale != -1) {
 864                 if (modparam_locale >= 0 && modparam_locale <= 11) {
 865                         bcm->sprom.locale = modparam_locale;
 866                         printk(KERN_WARNING PFX "Operating with modified "
 867                                                 "LocaleCode %u (%s)\n",
 868                                bcm->sprom.locale,
 869                                bcm43xx_locale_string(bcm->sprom.locale));
 870                 } else {
 871                         printk(KERN_WARNING PFX "Module parameter \"locale\" "
 872                                                 "invalid value. (0 - 11)\n");
 873                 }
 874         }
 875
 876         /* pa0b* */
 877         value = sprom[BCM43xx_SPROM_PA0B0];
 878         bcm->sprom.pa0b0 = value;
 879         value = sprom[BCM43xx_SPROM_PA0B1];
 880         bcm->sprom.pa0b1 = value;
 881         value = sprom[BCM43xx_SPROM_PA0B2];
 882         bcm->sprom.pa0b2 = value;
 883
 884         /* wl0gpio* */
 885         value = sprom[BCM43xx_SPROM_WL0GPIO0];
 886         if (value == 0x0000)
 887                 value = 0xFFFF;
 888         bcm->sprom.wl0gpio0 = value & 0x00FF;
 889         bcm->sprom.wl0gpio1 = (value & 0xFF00) >> 8;
 890         value = sprom[BCM43xx_SPROM_WL0GPIO2];
 891         if (value == 0x0000)
 892                 value = 0xFFFF;
 893         bcm->sprom.wl0gpio2 = value & 0x00FF;
 894         bcm->sprom.wl0gpio3 = (value & 0xFF00) >> 8;
 895
 896         /* maxpower */
 897         value = sprom[BCM43xx_SPROM_MAXPWR];
 898         bcm->sprom.maxpower_aphy = (value & 0xFF00) >> 8;
 899         bcm->sprom.maxpower_bgphy = value & 0x00FF;
 900
 901         /* pa1b* */
 902         value = sprom[BCM43xx_SPROM_PA1B0];
 903         bcm->sprom.pa1b0 = value;
 904         value = sprom[BCM43xx_SPROM_PA1B1];
 905         bcm->sprom.pa1b1 = value;
 906         value = sprom[BCM43xx_SPROM_PA1B2];
 907         bcm->sprom.pa1b2 = value;
 908
 909         /* idle tssi target */
 910         value = sprom[BCM43xx_SPROM_IDL_TSSI_TGT];
 911         bcm->sprom.idle_tssi_tgt_aphy = value & 0x00FF;
 912         bcm->sprom.idle_tssi_tgt_bgphy = (value & 0xFF00) >> 8;
 913
 914         /* boardflags */
 915         value = sprom[BCM43xx_SPROM_BOARDFLAGS];
 916         if (value == 0xFFFF)
 917                 value = 0x0000;
 918         bcm->sprom.boardflags = value;
 919         /* boardflags workarounds */
 920         if (bcm->board_vendor == PCI_VENDOR_ID_DELL &&
 921             bcm->chip_id == 0x4301 &&
 922             bcm->board_revision == 0x74)
 923                 bcm->sprom.boardflags |= BCM43xx_BFL_BTCOEXIST;
 924         if (bcm->board_vendor == PCI_VENDOR_ID_APPLE &&
 925             bcm->board_type == 0x4E &&
 926             bcm->board_revision > 0x40)
 927                 bcm->sprom.boardflags |= BCM43xx_BFL_PACTRL;
 928
 929         /* antenna gain */
 930         value = sprom[BCM43xx_SPROM_ANTENNA_GAIN];
 931         if (value == 0x0000 || value == 0xFFFF)
 932                 value = 0x0202;
 933         /* convert values to Q5.2 */
 934         bcm->sprom.antennagain_aphy = ((value & 0xFF00) >> 8) * 4;
 935         bcm->sprom.antennagain_bgphy = (value & 0x00FF) * 4;
 936
 937         kfree(sprom);
 938
 939         return 0;
 940 }
 941
 942 static int bcm43xx_geo_init(struct bcm43xx_private *bcm)
 943 {
 944         struct ieee80211_geo *geo;
 945         struct ieee80211_channel *chan;
 946         int have_a = 0, have_bg = 0;
 947         int i;
 948         u8 channel;
 949         struct bcm43xx_phyinfo *phy;
 950         const char *iso_country;
 951
 952         geo = kzalloc(sizeof(*geo), GFP_KERNEL);
 953         if (!geo)
 954                 return -ENOMEM;
 955
 956         for (i = 0; i < bcm->nr_80211_available; i++) {
 957                 phy = &(bcm->core_80211_ext[i].phy);
 958                 switch (phy->type) {
 959                 case BCM43xx_PHYTYPE_B:
 960                 case BCM43xx_PHYTYPE_G:
 961                         have_bg = 1;
 962                         break;
 963                 case BCM43xx_PHYTYPE_A:
 964                         have_a = 1;
 965                         break;
 966                 default:
 967                         assert(0);
 968                 }
 969         }
 970         iso_country = bcm43xx_locale_iso(bcm->sprom.locale);
 971
 972         if (have_a) {
 973                 for (i = 0, channel = IEEE80211_52GHZ_MIN_CHANNEL;
 974                       channel <= IEEE80211_52GHZ_MAX_CHANNEL; channel++) {
 975                         chan = &geo->a[i++];
 976                         chan->freq = bcm43xx_channel_to_freq_a(channel);
 977                         chan->channel = channel;
 978                 }
 979                 geo->a_channels = i;
 980         }
 981         if (have_bg) {
 982                 for (i = 0, channel = IEEE80211_24GHZ_MIN_CHANNEL;
 983                       channel <= IEEE80211_24GHZ_MAX_CHANNEL; channel++) {
 984                         chan = &geo->bg[i++];
 985                         chan->freq = bcm43xx_channel_to_freq_bg(channel);
 986                         chan->channel = channel;
 987                 }
 988                 geo->bg_channels = i;
 989         }
 990         memcpy(geo->name, iso_country, 2);
 991         if (0 /*TODO: Outdoor use only */)
 992                 geo->name[2] = 'O';
 993         else if (0 /*TODO: Indoor use only */)
 994                 geo->name[2] = 'I';
 995         else
 996                 geo->name[2] = ' ';
 997         geo->name[3] = '\0';
 998
 999         ieee80211_set_geo(bcm->ieee, geo);
1000         kfree(geo);
1001
1002         return 0;
1003 }
1004
1005 /* DummyTransmission function, as documented on
1006  * http://bcm-specs.sipsolutions.net/DummyTransmission
1007  */
1008 void bcm43xx_dummy_transmission(struct bcm43xx_private *bcm)
1009 {
1010         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1011         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1012         unsigned int i, max_loop;
1013         u16 value = 0;
1014         u32 buffer[5] = {
1015                 0x00000000,
1016                 0x0000D400,
1017                 0x00000000,
1018                 0x00000001,
1019                 0x00000000,
1020         };
1021
1022         switch (phy->type) {
1023         case BCM43xx_PHYTYPE_A:
1024                 max_loop = 0x1E;
1025                 buffer[0] = 0xCC010200;
1026                 break;
1027         case BCM43xx_PHYTYPE_B:
1028         case BCM43xx_PHYTYPE_G:
1029                 max_loop = 0xFA;
1030                 buffer[0] = 0x6E840B00;
1031                 break;
1032         default:
1033                 assert(0);
1034                 return;
1035         }
1036
1037         for (i = 0; i < 5; i++)
1038                 bcm43xx_ram_write(bcm, i * 4, buffer[i]);
1039
1040         bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
1041
1042         bcm43xx_write16(bcm, 0x0568, 0x0000);
1043         bcm43xx_write16(bcm, 0x07C0, 0x0000);
1044         bcm43xx_write16(bcm, 0x050C, ((phy->type == BCM43xx_PHYTYPE_A) ? 1 : 0));
1045         bcm43xx_write16(bcm, 0x0508, 0x0000);
1046         bcm43xx_write16(bcm, 0x050A, 0x0000);
1047         bcm43xx_write16(bcm, 0x054C, 0x0000);
1048         bcm43xx_write16(bcm, 0x056A, 0x0014);
1049         bcm43xx_write16(bcm, 0x0568, 0x0826);
1050         bcm43xx_write16(bcm, 0x0500, 0x0000);
1051         bcm43xx_write16(bcm, 0x0502, 0x0030);
1052
1053         if (radio->version == 0x2050 && radio->revision <= 0x5)
1054                 bcm43xx_radio_write16(bcm, 0x0051, 0x0017);
1055         for (i = 0x00; i < max_loop; i++) {
1056                 value = bcm43xx_read16(bcm, 0x050E);
1057                 if (value & 0x0080)
1058                         break;
1059                 udelay(10);
1060         }
1061         for (i = 0x00; i < 0x0A; i++) {
1062                 value = bcm43xx_read16(bcm, 0x050E);
1063                 if (value & 0x0400)
1064                         break;
1065                 udelay(10);
1066         }
1067         for (i = 0x00; i < 0x0A; i++) {
1068                 value = bcm43xx_read16(bcm, 0x0690);
1069                 if (!(value & 0x0100))
1070                         break;
1071                 udelay(10);
1072         }
1073         if (radio->version == 0x2050 && radio->revision <= 0x5)
1074                 bcm43xx_radio_write16(bcm, 0x0051, 0x0037);
1075 }
1076
1077 static void key_write(struct bcm43xx_private *bcm,
1078                       u8 index, u8 algorithm, const u16 *key)
1079 {
1080         unsigned int i, basic_wep = 0;
1081         u32 offset;
1082         u16 value;
1083
1084         /* Write associated key information */
1085         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x100 + (index * 2),
1086                             ((index << 4) | (algorithm & 0x0F)));
1087
1088         /* The first 4 WEP keys need extra love */
1089         if (((algorithm == BCM43xx_SEC_ALGO_WEP) ||
1090             (algorithm == BCM43xx_SEC_ALGO_WEP104)) && (index < 4))
1091                 basic_wep = 1;
1092
1093         /* Write key payload, 8 little endian words */
1094         offset = bcm->security_offset + (index * BCM43xx_SEC_KEYSIZE);
1095         for (i = 0; i < (BCM43xx_SEC_KEYSIZE / sizeof(u16)); i++) {
1096                 value = cpu_to_le16(key[i]);
1097                 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1098                                     offset + (i * 2), value);
1099
1100                 if (!basic_wep)
1101                         continue;
1102
1103                 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1104                                     offset + (i * 2) + 4 * BCM43xx_SEC_KEYSIZE,
1105                                     value);
1106         }
1107 }
1108
1109 static void keymac_write(struct bcm43xx_private *bcm,
1110                          u8 index, const u32 *addr)
1111 {
1112         /* for keys 0-3 there is no associated mac address */
1113         if (index < 4)
1114                 return;
1115
1116         index -= 4;
1117         if (bcm->current_core->rev >= 5) {
1118                 bcm43xx_shm_write32(bcm,
1119                                     BCM43xx_SHM_HWMAC,
1120                                     index * 2,
1121                                     cpu_to_be32(*addr));
1122                 bcm43xx_shm_write16(bcm,
1123                                     BCM43xx_SHM_HWMAC,
1124                                     (index * 2) + 1,
1125                                     cpu_to_be16(*((u16 *)(addr + 1))));
1126         } else {
1127                 if (index < 8) {
1128                         TODO(); /* Put them in the macaddress filter */
1129                 } else {
1130                         TODO();
1131                         /* Put them BCM43xx_SHM_SHARED, stating index 0x0120.
1132                            Keep in mind to update the count of keymacs in 0x003E as well! */
1133                 }
1134         }
1135 }
1136
1137 static int bcm43xx_key_write(struct bcm43xx_private *bcm,
1138                              u8 index, u8 algorithm,
1139                              const u8 *_key, int key_len,
1140                              const u8 *mac_addr)
1141 {
1142         u8 key[BCM43xx_SEC_KEYSIZE] = { 0 };
1143
1144         if (index >= ARRAY_SIZE(bcm->key))
1145                 return -EINVAL;
1146         if (key_len > ARRAY_SIZE(key))
1147                 return -EINVAL;
1148         if (algorithm < 1 || algorithm > 5)
1149                 return -EINVAL;
1150
1151         memcpy(key, _key, key_len);
1152         key_write(bcm, index, algorithm, (const u16 *)key);
1153         keymac_write(bcm, index, (const u32 *)mac_addr);
1154
1155         bcm->key[index].algorithm = algorithm;
1156
1157         return 0;
1158 }
1159
1160 static void bcm43xx_clear_keys(struct bcm43xx_private *bcm)
1161 {
1162         static const u32 zero_mac[2] = { 0 };
1163         unsigned int i,j, nr_keys = 54;
1164         u16 offset;
1165
1166         if (bcm->current_core->rev < 5)
1167                 nr_keys = 16;
1168         assert(nr_keys <= ARRAY_SIZE(bcm->key));
1169
1170         for (i = 0; i < nr_keys; i++) {
1171                 bcm->key[i].enabled = 0;
1172                 /* returns for i < 4 immediately */
1173                 keymac_write(bcm, i, zero_mac);
1174                 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1175                                     0x100 + (i * 2), 0x0000);
1176                 for (j = 0; j < 8; j++) {
1177                         offset = bcm->security_offset + (j * 4) + (i * BCM43xx_SEC_KEYSIZE);
1178                         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1179                                             offset, 0x0000);
1180                 }
1181         }
1182         dprintk(KERN_INFO PFX "Keys cleared\n");
1183 }
1184
1185 /* Lowlevel core-switch function. This is only to be used in
1186  * bcm43xx_switch_core() and bcm43xx_probe_cores()
1187  */
1188 static int _switch_core(struct bcm43xx_private *bcm, int core)
1189 {
1190         int err;
1191         int attempts = 0;
1192         u32 current_core;
1193
1194         assert(core >= 0);
1195         while (1) {
1196                 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1197                                                  (core * 0x1000) + 0x18000000);
1198                 if (unlikely(err))
1199                         goto error;
1200                 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1201                                                 &current_core);
1202                 if (unlikely(err))
1203                         goto error;
1204                 current_core = (current_core - 0x18000000) / 0x1000;
1205                 if (current_core == core)
1206                         break;
1207
1208                 if (unlikely(attempts++ > BCM43xx_SWITCH_CORE_MAX_RETRIES))
1209                         goto error;
1210                 udelay(10);
1211         }
1212 #ifdef CONFIG_BCM947XX
1213         if (bcm->pci_dev->bus->number == 0)
1214                 bcm->current_core_offset = 0x1000 * core;
1215         else
1216                 bcm->current_core_offset = 0;
1217 #endif
1218
1219         return 0;
1220 error:
1221         printk(KERN_ERR PFX "Failed to switch to core %d\n", core);
1222         return -ENODEV;
1223 }
1224
1225 int bcm43xx_switch_core(struct bcm43xx_private *bcm, struct bcm43xx_coreinfo *new_core)
1226 {
1227         int err;
1228
1229         if (unlikely(!new_core))
1230                 return 0;
1231         if (!new_core->available)
1232                 return -ENODEV;
1233         if (bcm->current_core == new_core)
1234                 return 0;
1235         err = _switch_core(bcm, new_core->index);
1236         if (unlikely(err))
1237                 goto out;
1238
1239         bcm->current_core = new_core;
1240         bcm->current_80211_core_idx = -1;
1241         if (new_core->id == BCM43xx_COREID_80211)
1242                 bcm->current_80211_core_idx = (int)(new_core - &(bcm->core_80211[0]));
1243
1244 out:
1245         return err;
1246 }
1247
1248 static int bcm43xx_core_enabled(struct bcm43xx_private *bcm)
1249 {
1250         u32 value;
1251
1252         value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1253         value &= BCM43xx_SBTMSTATELOW_CLOCK | BCM43xx_SBTMSTATELOW_RESET
1254                  | BCM43xx_SBTMSTATELOW_REJECT;
1255
1256         return (value == BCM43xx_SBTMSTATELOW_CLOCK);
1257 }
1258
1259 /* disable current core */
1260 static int bcm43xx_core_disable(struct bcm43xx_private *bcm, u32 core_flags)
1261 {
1262         u32 sbtmstatelow;
1263         u32 sbtmstatehigh;
1264         int i;
1265
1266         /* fetch sbtmstatelow from core information registers */
1267         sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1268
1269         /* core is already in reset */
1270         if (sbtmstatelow & BCM43xx_SBTMSTATELOW_RESET)
1271                 goto out;
1272
1273         if (sbtmstatelow & BCM43xx_SBTMSTATELOW_CLOCK) {
1274                 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1275                                BCM43xx_SBTMSTATELOW_REJECT;
1276                 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1277
1278                 for (i = 0; i < 1000; i++) {
1279                         sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1280                         if (sbtmstatelow & BCM43xx_SBTMSTATELOW_REJECT) {
1281                                 i = -1;
1282                                 break;
1283                         }
1284                         udelay(10);
1285                 }
1286                 if (i != -1) {
1287                         printk(KERN_ERR PFX "Error: core_disable() REJECT timeout!\n");
1288                         return -EBUSY;
1289                 }
1290
1291                 for (i = 0; i < 1000; i++) {
1292                         sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1293                         if (!(sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_BUSY)) {
1294                                 i = -1;
1295                                 break;
1296                         }
1297                         udelay(10);
1298                 }
1299                 if (i != -1) {
1300                         printk(KERN_ERR PFX "Error: core_disable() BUSY timeout!\n");
1301                         return -EBUSY;
1302                 }
1303
1304                 sbtmstatelow = BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1305                                BCM43xx_SBTMSTATELOW_REJECT |
1306                                BCM43xx_SBTMSTATELOW_RESET |
1307                                BCM43xx_SBTMSTATELOW_CLOCK |
1308                                core_flags;
1309                 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1310                 udelay(10);
1311         }
1312
1313         sbtmstatelow = BCM43xx_SBTMSTATELOW_RESET |
1314                        BCM43xx_SBTMSTATELOW_REJECT |
1315                        core_flags;
1316         bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1317
1318 out:
1319         bcm->current_core->enabled = 0;
1320
1321         return 0;
1322 }
1323
1324 /* enable (reset) current core */
1325 static int bcm43xx_core_enable(struct bcm43xx_private *bcm, u32 core_flags)
1326 {
1327         u32 sbtmstatelow;
1328         u32 sbtmstatehigh;
1329         u32 sbimstate;
1330         int err;
1331
1332         err = bcm43xx_core_disable(bcm, core_flags);
1333         if (err)
1334                 goto out;
1335
1336         sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1337                        BCM43xx_SBTMSTATELOW_RESET |
1338                        BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1339                        core_flags;
1340         bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1341         udelay(1);
1342
1343         sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1344         if (sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_SERROR) {
1345                 sbtmstatehigh = 0x00000000;
1346                 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATEHIGH, sbtmstatehigh);
1347         }
1348
1349         sbimstate = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMSTATE);
1350         if (sbimstate & (BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT)) {
1351                 sbimstate &= ~(BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT);
1352                 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMSTATE, sbimstate);
1353         }
1354
1355         sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1356                        BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1357                        core_flags;
1358         bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1359         udelay(1);
1360
1361         sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK | core_flags;
1362         bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1363         udelay(1);
1364
1365         bcm->current_core->enabled = 1;
1366         assert(err == 0);
1367 out:
1368         return err;
1369 }
1370
1371 /* http://bcm-specs.sipsolutions.net/80211CoreReset */
1372 void bcm43xx_wireless_core_reset(struct bcm43xx_private *bcm, int connect_phy)
1373 {
1374         u32 flags = 0x00040000;
1375
1376         if ((bcm43xx_core_enabled(bcm)) &&
1377             !bcm43xx_using_pio(bcm)) {
1378 //FIXME: Do we _really_ want #ifndef CONFIG_BCM947XX here?
1379 #ifndef CONFIG_BCM947XX
1380                 /* reset all used DMA controllers. */
1381                 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1382                 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA2_BASE);
1383                 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA3_BASE);
1384                 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1385                 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1386                 if (bcm->current_core->rev < 5)
1387                         bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1388 #endif
1389         }
1390         if (bcm->shutting_down) {
1391                 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1392                                 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1393                                 & ~(BCM43xx_SBF_MAC_ENABLED | 0x00000002));
1394         } else {
1395                 if (connect_phy)
1396                         flags |= 0x20000000;
1397                 bcm43xx_phy_connect(bcm, connect_phy);
1398                 bcm43xx_core_enable(bcm, flags);
1399                 bcm43xx_write16(bcm, 0x03E6, 0x0000);
1400                 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1401                                 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1402                                 | BCM43xx_SBF_400);
1403         }
1404 }
1405
1406 static void bcm43xx_wireless_core_disable(struct bcm43xx_private *bcm)
1407 {
1408         bcm43xx_radio_turn_off(bcm);
1409         bcm43xx_write16(bcm, 0x03E6, 0x00F4);
1410         bcm43xx_core_disable(bcm, 0);
1411 }
1412
1413 /* Mark the current 80211 core inactive.
1414  * "active_80211_core" is the other 80211 core, which is used.
1415  */
1416 static int bcm43xx_wireless_core_mark_inactive(struct bcm43xx_private *bcm,
1417                                                struct bcm43xx_coreinfo *active_80211_core)
1418 {
1419         u32 sbtmstatelow;
1420         struct bcm43xx_coreinfo *old_core;
1421         int err = 0;
1422
1423         bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1424         bcm43xx_radio_turn_off(bcm);
1425         sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1426         sbtmstatelow &= ~0x200a0000;
1427         sbtmstatelow |= 0xa0000;
1428         bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1429         udelay(1);
1430         sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1431         sbtmstatelow &= ~0xa0000;
1432         sbtmstatelow |= 0x80000;
1433         bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1434         udelay(1);
1435
1436         if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G) {
1437                 old_core = bcm->current_core;
1438                 err = bcm43xx_switch_core(bcm, active_80211_core);
1439                 if (err)
1440                         goto out;
1441                 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1442                 sbtmstatelow &= ~0x20000000;
1443                 sbtmstatelow |= 0x20000000;
1444                 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1445                 err = bcm43xx_switch_core(bcm, old_core);
1446         }
1447
1448 out:
1449         return err;
1450 }
1451
1452 static void handle_irq_transmit_status(struct bcm43xx_private *bcm)
1453 {
1454         u32 v0, v1;
1455         u16 tmp;
1456         struct bcm43xx_xmitstatus stat;
1457
1458         while (1) {
1459                 v0 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_0);
1460                 if (!v0)
1461                         break;
1462                 v1 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_1);
1463
1464                 stat.cookie = (v0 >> 16) & 0x0000FFFF;
1465                 tmp = (u16)((v0 & 0xFFF0) | ((v0 & 0xF) >> 1));
1466                 stat.flags = tmp & 0xFF;
1467                 stat.cnt1 = (tmp & 0x0F00) >> 8;
1468                 stat.cnt2 = (tmp & 0xF000) >> 12;
1469                 stat.seq = (u16)(v1 & 0xFFFF);
1470                 stat.unknown = (u16)((v1 >> 16) & 0xFF);
1471
1472                 bcm43xx_debugfs_log_txstat(bcm, &stat);
1473
1474                 if (stat.flags & BCM43xx_TXSTAT_FLAG_IGNORE)
1475                         continue;
1476                 if (!(stat.flags & BCM43xx_TXSTAT_FLAG_ACK)) {
1477                         //TODO: packet was not acked (was lost)
1478                 }
1479                 //TODO: There are more (unknown) flags to test. see bcm43xx_main.h
1480
1481                 if (bcm43xx_using_pio(bcm))
1482                         bcm43xx_pio_handle_xmitstatus(bcm, &stat);
1483                 else
1484                         bcm43xx_dma_handle_xmitstatus(bcm, &stat);
1485         }
1486 }
1487
1488 static void bcm43xx_generate_noise_sample(struct bcm43xx_private *bcm)
1489 {
1490         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x408, 0x7F7F);
1491         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x40A, 0x7F7F);
1492         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1493                         bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD) | (1 << 4));
1494         assert(bcm->noisecalc.core_at_start == bcm->current_core);
1495         assert(bcm->noisecalc.channel_at_start == bcm43xx_current_radio(bcm)->channel);
1496 }
1497
1498 static void bcm43xx_calculate_link_quality(struct bcm43xx_private *bcm)
1499 {
1500         /* Top half of Link Quality calculation. */
1501
1502         if (bcm->noisecalc.calculation_running)
1503                 return;
1504         bcm->noisecalc.core_at_start = bcm->current_core;
1505         bcm->noisecalc.channel_at_start = bcm43xx_current_radio(bcm)->channel;
1506         bcm->noisecalc.calculation_running = 1;
1507         bcm->noisecalc.nr_samples = 0;
1508
1509         bcm43xx_generate_noise_sample(bcm);
1510 }
1511
1512 static void handle_irq_noise(struct bcm43xx_private *bcm)
1513 {
1514         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1515         u16 tmp;
1516         u8 noise[4];
1517         u8 i, j;
1518         s32 average;
1519
1520         /* Bottom half of Link Quality calculation. */
1521
1522         assert(bcm->noisecalc.calculation_running);
1523         if (bcm->noisecalc.core_at_start != bcm->current_core ||
1524             bcm->noisecalc.channel_at_start != radio->channel)
1525                 goto drop_calculation;
1526         tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x408);
1527         noise[0] = (tmp & 0x00FF);
1528         noise[1] = (tmp & 0xFF00) >> 8;
1529         tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40A);
1530         noise[2] = (tmp & 0x00FF);
1531         noise[3] = (tmp & 0xFF00) >> 8;
1532         if (noise[0] == 0x7F || noise[1] == 0x7F ||
1533             noise[2] == 0x7F || noise[3] == 0x7F)
1534                 goto generate_new;
1535
1536         /* Get the noise samples. */
1537         assert(bcm->noisecalc.nr_samples <= 8);
1538         i = bcm->noisecalc.nr_samples;
1539         noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1540         noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1541         noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1542         noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1543         bcm->noisecalc.samples[i][0] = radio->nrssi_lt[noise[0]];
1544         bcm->noisecalc.samples[i][1] = radio->nrssi_lt[noise[1]];
1545         bcm->noisecalc.samples[i][2] = radio->nrssi_lt[noise[2]];
1546         bcm->noisecalc.samples[i][3] = radio->nrssi_lt[noise[3]];
1547         bcm->noisecalc.nr_samples++;
1548         if (bcm->noisecalc.nr_samples == 8) {
1549                 /* Calculate the Link Quality by the noise samples. */
1550                 average = 0;
1551                 for (i = 0; i < 8; i++) {
1552                         for (j = 0; j < 4; j++)
1553                                 average += bcm->noisecalc.samples[i][j];
1554                 }
1555                 average /= (8 * 4);
1556                 average *= 125;
1557                 average += 64;
1558                 average /= 128;
1559
1560                 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40C);
1561                 tmp = (tmp / 128) & 0x1F;
1562                 if (tmp >= 8)
1563                         average += 2;
1564                 else
1565                         average -= 25;
1566                 if (tmp == 8)
1567                         average -= 72;
1568                 else
1569                         average -= 48;
1570
1571 /* FIXME: This is wrong, but people want fancy stats. well... */
1572 bcm->stats.noise = average;
1573                 if (average > -65)
1574                         bcm->stats.link_quality = 0;
1575                 else if (average > -75)
1576                         bcm->stats.link_quality = 1;
1577                 else if (average > -85)
1578                         bcm->stats.link_quality = 2;
1579                 else
1580                         bcm->stats.link_quality = 3;
1581 //              dprintk(KERN_INFO PFX "Link Quality: %u (avg was %d)\n", bcm->stats.link_quality, average);
1582 drop_calculation:
1583                 bcm->noisecalc.calculation_running = 0;
1584                 return;
1585         }
1586 generate_new:
1587         bcm43xx_generate_noise_sample(bcm);
1588 }
1589
1590 static void handle_irq_ps(struct bcm43xx_private *bcm)
1591 {
1592         if (bcm->ieee->iw_mode == IW_MODE_MASTER) {
1593                 ///TODO: PS TBTT
1594         } else {
1595                 if (1/*FIXME: the last PSpoll frame was sent successfully */)
1596                         bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
1597         }
1598         if (bcm->ieee->iw_mode == IW_MODE_ADHOC)
1599                 bcm->reg124_set_0x4 = 1;
1600         //FIXME else set to false?
1601 }
1602
1603 static void handle_irq_reg124(struct bcm43xx_private *bcm)
1604 {
1605         if (!bcm->reg124_set_0x4)
1606                 return;
1607         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1608                         bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD)
1609                         | 0x4);
1610         //FIXME: reset reg124_set_0x4 to false?
1611 }
1612
1613 static void handle_irq_pmq(struct bcm43xx_private *bcm)
1614 {
1615         u32 tmp;
1616
1617         //TODO: AP mode.
1618
1619         while (1) {
1620                 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_PS_STATUS);
1621                 if (!(tmp & 0x00000008))
1622                         break;
1623         }
1624         /* 16bit write is odd, but correct. */
1625         bcm43xx_write16(bcm, BCM43xx_MMIO_PS_STATUS, 0x0002);
1626 }
1627
1628 static void bcm43xx_generate_beacon_template(struct bcm43xx_private *bcm,
1629                                              u16 ram_offset, u16 shm_size_offset)
1630 {
1631         u32 value;
1632         u16 size = 0;
1633
1634         /* Timestamp. */
1635         //FIXME: assumption: The chip sets the timestamp
1636         value = 0;
1637         bcm43xx_ram_write(bcm, ram_offset++, value);
1638         bcm43xx_ram_write(bcm, ram_offset++, value);
1639         size += 8;
1640
1641         /* Beacon Interval / Capability Information */
1642         value = 0x0000;//FIXME: Which interval?
1643         value |= (1 << 0) << 16; /* ESS */
1644         value |= (1 << 2) << 16; /* CF Pollable */      //FIXME?
1645         value |= (1 << 3) << 16; /* CF Poll Request */  //FIXME?
1646         if (!bcm->ieee->open_wep)
1647                 value |= (1 << 4) << 16; /* Privacy */
1648         bcm43xx_ram_write(bcm, ram_offset++, value);
1649         size += 4;
1650
1651         /* SSID */
1652         //TODO
1653
1654         /* FH Parameter Set */
1655         //TODO
1656
1657         /* DS Parameter Set */
1658         //TODO
1659
1660         /* CF Parameter Set */
1661         //TODO
1662
1663         /* TIM */
1664         //TODO
1665
1666         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, shm_size_offset, size);
1667 }
1668
1669 static void handle_irq_beacon(struct bcm43xx_private *bcm)
1670 {
1671         u32 status;
1672
1673         bcm->irq_savedstate &= ~BCM43xx_IRQ_BEACON;
1674         status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD);
1675
1676         if ((status & 0x1) && (status & 0x2)) {
1677                 /* ACK beacon IRQ. */
1678                 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON,
1679                                 BCM43xx_IRQ_BEACON);
1680                 bcm->irq_savedstate |= BCM43xx_IRQ_BEACON;
1681                 return;
1682         }
1683         if (!(status & 0x1)) {
1684                 bcm43xx_generate_beacon_template(bcm, 0x68, 0x18);
1685                 status |= 0x1;
1686                 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1687         }
1688         if (!(status & 0x2)) {
1689                 bcm43xx_generate_beacon_template(bcm, 0x468, 0x1A);
1690                 status |= 0x2;
1691                 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1692         }
1693 }
1694
1695 /* Interrupt handler bottom-half */
1696 static void bcm43xx_interrupt_tasklet(struct bcm43xx_private *bcm)
1697 {
1698         u32 reason;
1699         u32 dma_reason[4];
1700         int activity = 0;
1701         unsigned long flags;
1702
1703 #ifdef CONFIG_BCM43XX_DEBUG
1704         u32 _handled = 0x00000000;
1705 # define bcmirq_handled(irq)    do { _handled |= (irq); } while (0)
1706 #else
1707 # define bcmirq_handled(irq)    do { /* nothing */ } while (0)
1708 #endif /* CONFIG_BCM43XX_DEBUG*/
1709
1710         bcm43xx_lock_mmio(bcm, flags);
1711         reason = bcm->irq_reason;
1712         dma_reason[0] = bcm->dma_reason[0];
1713         dma_reason[1] = bcm->dma_reason[1];
1714         dma_reason[2] = bcm->dma_reason[2];
1715         dma_reason[3] = bcm->dma_reason[3];
1716
1717         if (unlikely(reason & BCM43xx_IRQ_XMIT_ERROR)) {
1718                 /* TX error. We get this when Template Ram is written in wrong endianess
1719                  * in dummy_tx(). We also get this if something is wrong with the TX header
1720                  * on DMA or PIO queues.
1721                  * Maybe we get this in other error conditions, too.
1722                  */
1723                 printkl(KERN_ERR PFX "FATAL ERROR: BCM43xx_IRQ_XMIT_ERROR\n");
1724                 bcmirq_handled(BCM43xx_IRQ_XMIT_ERROR);
1725         }
1726         if (unlikely((dma_reason[0] & BCM43xx_DMAIRQ_FATALMASK) |
1727                      (dma_reason[1] & BCM43xx_DMAIRQ_FATALMASK) |
1728                      (dma_reason[2] & BCM43xx_DMAIRQ_FATALMASK) |
1729                      (dma_reason[3] & BCM43xx_DMAIRQ_FATALMASK))) {
1730                 printkl(KERN_ERR PFX "FATAL ERROR: Fatal DMA error: "
1731                                      "0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1732                         dma_reason[0], dma_reason[1],
1733                         dma_reason[2], dma_reason[3]);
1734                 bcm43xx_controller_restart(bcm, "DMA error");
1735                 bcm43xx_unlock_mmio(bcm, flags);
1736                 return;
1737         }
1738         if (unlikely((dma_reason[0] & BCM43xx_DMAIRQ_NONFATALMASK) |
1739                      (dma_reason[1] & BCM43xx_DMAIRQ_NONFATALMASK) |
1740                      (dma_reason[2] & BCM43xx_DMAIRQ_NONFATALMASK) |
1741                      (dma_reason[3] & BCM43xx_DMAIRQ_NONFATALMASK))) {
1742                 printkl(KERN_ERR PFX "DMA error: "
1743                                      "0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1744                         dma_reason[0], dma_reason[1],
1745                         dma_reason[2], dma_reason[3]);
1746         }
1747
1748         if (reason & BCM43xx_IRQ_PS) {
1749                 handle_irq_ps(bcm);
1750                 bcmirq_handled(BCM43xx_IRQ_PS);
1751         }
1752
1753         if (reason & BCM43xx_IRQ_REG124) {
1754                 handle_irq_reg124(bcm);
1755                 bcmirq_handled(BCM43xx_IRQ_REG124);
1756         }
1757
1758         if (reason & BCM43xx_IRQ_BEACON) {
1759                 if (bcm->ieee->iw_mode == IW_MODE_MASTER)
1760                         handle_irq_beacon(bcm);
1761                 bcmirq_handled(BCM43xx_IRQ_BEACON);
1762         }
1763
1764         if (reason & BCM43xx_IRQ_PMQ) {
1765                 handle_irq_pmq(bcm);
1766                 bcmirq_handled(BCM43xx_IRQ_PMQ);
1767         }
1768
1769         if (reason & BCM43xx_IRQ_SCAN) {
1770                 /*TODO*/
1771                 //bcmirq_handled(BCM43xx_IRQ_SCAN);
1772         }
1773
1774         if (reason & BCM43xx_IRQ_NOISE) {
1775                 handle_irq_noise(bcm);
1776                 bcmirq_handled(BCM43xx_IRQ_NOISE);
1777         }
1778
1779         /* Check the DMA reason registers for received data. */
1780         assert(!(dma_reason[1] & BCM43xx_DMAIRQ_RX_DONE));
1781         assert(!(dma_reason[2] & BCM43xx_DMAIRQ_RX_DONE));
1782         if (dma_reason[0] & BCM43xx_DMAIRQ_RX_DONE) {
1783                 if (bcm43xx_using_pio(bcm))
1784                         bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue0);
1785                 else
1786                         bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring0);
1787                 /* We intentionally don't set "activity" to 1, here. */
1788         }
1789         if (dma_reason[3] & BCM43xx_DMAIRQ_RX_DONE) {
1790                 if (bcm43xx_using_pio(bcm))
1791                         bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue3);
1792                 else
1793                         bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring1);
1794                 activity = 1;
1795         }
1796         bcmirq_handled(BCM43xx_IRQ_RX);
1797
1798         if (reason & BCM43xx_IRQ_XMIT_STATUS) {
1799                 handle_irq_transmit_status(bcm);
1800                 activity = 1;
1801                 //TODO: In AP mode, this also causes sending of powersave responses.
1802                 bcmirq_handled(BCM43xx_IRQ_XMIT_STATUS);
1803         }
1804
1805         /* IRQ_PIO_WORKAROUND is handled in the top-half. */
1806         bcmirq_handled(BCM43xx_IRQ_PIO_WORKAROUND);
1807 #ifdef CONFIG_BCM43XX_DEBUG
1808         if (unlikely(reason & ~_handled)) {
1809                 printkl(KERN_WARNING PFX
1810                         "Unhandled IRQ! Reason: 0x%08x,  Unhandled: 0x%08x,  "
1811                         "DMA: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
1812                         reason, (reason & ~_handled),
1813                         dma_reason[0], dma_reason[1],
1814                         dma_reason[2], dma_reason[3]);
1815         }
1816 #endif
1817 #undef bcmirq_handled
1818
1819         if (!modparam_noleds)
1820                 bcm43xx_leds_update(bcm, activity);
1821         bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
1822         bcm43xx_unlock_mmio(bcm, flags);
1823 }
1824
1825 static void pio_irq_workaround(struct bcm43xx_private *bcm,
1826                                u16 base, int queueidx)
1827 {
1828         u16 rxctl;
1829
1830         rxctl = bcm43xx_read16(bcm, base + BCM43xx_PIO_RXCTL);
1831         if (rxctl & BCM43xx_PIO_RXCTL_DATAAVAILABLE)
1832                 bcm->dma_reason[queueidx] |= BCM43xx_DMAIRQ_RX_DONE;
1833         else
1834                 bcm->dma_reason[queueidx] &= ~BCM43xx_DMAIRQ_RX_DONE;
1835 }
1836
1837 static void bcm43xx_interrupt_ack(struct bcm43xx_private *bcm, u32 reason)
1838 {
1839         if (bcm43xx_using_pio(bcm) &&
1840             (bcm->current_core->rev < 3) &&
1841             (!(reason & BCM43xx_IRQ_PIO_WORKAROUND))) {
1842                 /* Apply a PIO specific workaround to the dma_reasons */
1843                 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO1_BASE, 0);
1844                 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO2_BASE, 1);
1845                 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO3_BASE, 2);
1846                 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO4_BASE, 3);
1847         }
1848
1849         bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, reason);
1850
1851         bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_REASON,
1852                         bcm->dma_reason[0]);
1853         bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_REASON,
1854                         bcm->dma_reason[1]);
1855         bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_REASON,
1856                         bcm->dma_reason[2]);
1857         bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_REASON,
1858                         bcm->dma_reason[3]);
1859 }
1860
1861 /* Interrupt handler top-half */
1862 static irqreturn_t bcm43xx_interrupt_handler(int irq, void *dev_id, struct pt_regs *regs)
1863 {
1864         irqreturn_t ret = IRQ_HANDLED;
1865         struct bcm43xx_private *bcm = dev_id;
1866         u32 reason;
1867
1868         if (!bcm)
1869                 return IRQ_NONE;
1870
1871         spin_lock(&bcm->_lock);
1872
1873         reason = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
1874         if (reason == 0xffffffff) {
1875                 /* irq not for us (shared irq) */
1876                 ret = IRQ_NONE;
1877                 goto out;
1878         }
1879         reason &= bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
1880         if (!reason)
1881                 goto out;
1882
1883         bcm->dma_reason[0] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA1_REASON)
1884                              & 0x0001dc00;
1885         bcm->dma_reason[1] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA2_REASON)
1886                              & 0x0000dc00;
1887         bcm->dma_reason[2] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA3_REASON)
1888                              & 0x0000dc00;
1889         bcm->dma_reason[3] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA4_REASON)
1890                              & 0x0001dc00;
1891
1892         bcm43xx_interrupt_ack(bcm, reason);
1893
1894         /* Only accept IRQs, if we are initialized properly.
1895          * This avoids an RX race while initializing.
1896          * We should probably not enable IRQs before we are initialized
1897          * completely, but some careful work is needed to fix this. I think it
1898          * is best to stay with this cheap workaround for now... .
1899          */
1900         if (likely(bcm->initialized)) {
1901                 /* disable all IRQs. They are enabled again in the bottom half. */
1902                 bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1903                 /* save the reason code and call our bottom half. */
1904                 bcm->irq_reason = reason;
1905                 tasklet_schedule(&bcm->isr_tasklet);
1906         }
1907
1908 out:
1909         mmiowb();
1910         spin_unlock(&bcm->_lock);
1911
1912         return ret;
1913 }
1914
1915 static void bcm43xx_release_firmware(struct bcm43xx_private *bcm, int force)
1916 {
1917         if (bcm->firmware_norelease && !force)
1918                 return; /* Suspending or controller reset. */
1919         release_firmware(bcm->ucode);
1920         bcm->ucode = NULL;
1921         release_firmware(bcm->pcm);
1922         bcm->pcm = NULL;
1923         release_firmware(bcm->initvals0);
1924         bcm->initvals0 = NULL;
1925         release_firmware(bcm->initvals1);
1926         bcm->initvals1 = NULL;
1927 }
1928
1929 static int bcm43xx_request_firmware(struct bcm43xx_private *bcm)
1930 {
1931         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1932         u8 rev = bcm->current_core->rev;
1933         int err = 0;
1934         int nr;
1935         char buf[22 + sizeof(modparam_fwpostfix) - 1] = { 0 };
1936
1937         if (!bcm->ucode) {
1938                 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_microcode%d%s.fw",
1939                          (rev >= 5 ? 5 : rev),
1940                          modparam_fwpostfix);
1941                 err = request_firmware(&bcm->ucode, buf, &bcm->pci_dev->dev);
1942                 if (err) {
1943                         printk(KERN_ERR PFX
1944                                "Error: Microcode \"%s\" not available or load failed.\n",
1945                                 buf);
1946                         goto error;
1947                 }
1948         }
1949
1950         if (!bcm->pcm) {
1951                 snprintf(buf, ARRAY_SIZE(buf),
1952                          "bcm43xx_pcm%d%s.fw",
1953                          (rev < 5 ? 4 : 5),
1954                          modparam_fwpostfix);
1955                 err = request_firmware(&bcm->pcm, buf, &bcm->pci_dev->dev);
1956                 if (err) {
1957                         printk(KERN_ERR PFX
1958                                "Error: PCM \"%s\" not available or load failed.\n",
1959                                buf);
1960                         goto error;
1961                 }
1962         }
1963
1964         if (!bcm->initvals0) {
1965                 if (rev == 2 || rev == 4) {
1966                         switch (phy->type) {
1967                         case BCM43xx_PHYTYPE_A:
1968                                 nr = 3;
1969                                 break;
1970                         case BCM43xx_PHYTYPE_B:
1971                         case BCM43xx_PHYTYPE_G:
1972                                 nr = 1;
1973                                 break;
1974                         default:
1975                                 goto err_noinitval;
1976                         }
1977
1978                 } else if (rev >= 5) {
1979                         switch (phy->type) {
1980                         case BCM43xx_PHYTYPE_A:
1981                                 nr = 7;
1982                                 break;
1983                         case BCM43xx_PHYTYPE_B:
1984                         case BCM43xx_PHYTYPE_G:
1985                                 nr = 5;
1986                                 break;
1987                         default:
1988                                 goto err_noinitval;
1989                         }
1990                 } else
1991                         goto err_noinitval;
1992                 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
1993                          nr, modparam_fwpostfix);
1994
1995                 err = request_firmware(&bcm->initvals0, buf, &bcm->pci_dev->dev);
1996                 if (err) {
1997                         printk(KERN_ERR PFX
1998                                "Error: InitVals \"%s\" not available or load failed.\n",
1999                                 buf);
2000                         goto error;
2001                 }
2002                 if (bcm->initvals0->size % sizeof(struct bcm43xx_initval)) {
2003                         printk(KERN_ERR PFX "InitVals fileformat error.\n");
2004                         goto error;
2005                 }
2006         }
2007
2008         if (!bcm->initvals1) {
2009                 if (rev >= 5) {
2010                         u32 sbtmstatehigh;
2011
2012                         switch (phy->type) {
2013                         case BCM43xx_PHYTYPE_A:
2014                                 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
2015                                 if (sbtmstatehigh & 0x00010000)
2016                                         nr = 9;
2017                                 else
2018                                         nr = 10;
2019                                 break;
2020                         case BCM43xx_PHYTYPE_B:
2021                         case BCM43xx_PHYTYPE_G:
2022                                         nr = 6;
2023                                 break;
2024                         default:
2025                                 goto err_noinitval;
2026                         }
2027                         snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
2028                                  nr, modparam_fwpostfix);
2029
2030                         err = request_firmware(&bcm->initvals1, buf, &bcm->pci_dev->dev);
2031                         if (err) {
2032                                 printk(KERN_ERR PFX
2033                                        "Error: InitVals \"%s\" not available or load failed.\n",
2034                                         buf);
2035                                 goto error;
2036                         }
2037                         if (bcm->initvals1->size % sizeof(struct bcm43xx_initval)) {
2038                                 printk(KERN_ERR PFX "InitVals fileformat error.\n");
2039                                 goto error;
2040                         }
2041                 }
2042         }
2043
2044 out:
2045         return err;
2046 error:
2047         bcm43xx_release_firmware(bcm, 1);
2048         goto out;
2049 err_noinitval:
2050         printk(KERN_ERR PFX "Error: No InitVals available!\n");
2051         err = -ENOENT;
2052         goto error;
2053 }
2054
2055 static void bcm43xx_upload_microcode(struct bcm43xx_private *bcm)
2056 {
2057         const u32 *data;
2058         unsigned int i, len;
2059
2060         /* Upload Microcode. */
2061         data = (u32 *)(bcm->ucode->data);
2062         len = bcm->ucode->size / sizeof(u32);
2063         bcm43xx_shm_control_word(bcm, BCM43xx_SHM_UCODE, 0x0000);
2064         for (i = 0; i < len; i++) {
2065                 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2066                                 be32_to_cpu(data[i]));
2067                 udelay(10);
2068         }
2069
2070         /* Upload PCM data. */
2071         data = (u32 *)(bcm->pcm->data);
2072         len = bcm->pcm->size / sizeof(u32);
2073         bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01ea);
2074         bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, 0x00004000);
2075         bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01eb);
2076         for (i = 0; i < len; i++) {
2077                 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2078                                 be32_to_cpu(data[i]));
2079                 udelay(10);
2080         }
2081 }
2082
2083 static int bcm43xx_write_initvals(struct bcm43xx_private *bcm,
2084                                   const struct bcm43xx_initval *data,
2085                                   const unsigned int len)
2086 {
2087         u16 offset, size;
2088         u32 value;
2089         unsigned int i;
2090
2091         for (i = 0; i < len; i++) {
2092                 offset = be16_to_cpu(data[i].offset);
2093                 size = be16_to_cpu(data[i].size);
2094                 value = be32_to_cpu(data[i].value);
2095
2096                 if (unlikely(offset >= 0x1000))
2097                         goto err_format;
2098                 if (size == 2) {
2099                         if (unlikely(value & 0xFFFF0000))
2100                                 goto err_format;
2101                         bcm43xx_write16(bcm, offset, (u16)value);
2102                 } else if (size == 4) {
2103                         bcm43xx_write32(bcm, offset, value);
2104                 } else
2105                         goto err_format;
2106         }
2107
2108         return 0;
2109
2110 err_format:
2111         printk(KERN_ERR PFX "InitVals (bcm43xx_initvalXX.fw) file-format error. "
2112                             "Please fix your bcm43xx firmware files.\n");
2113         return -EPROTO;
2114 }
2115
2116 static int bcm43xx_upload_initvals(struct bcm43xx_private *bcm)
2117 {
2118         int err;
2119
2120         err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)bcm->initvals0->data,
2121                                      bcm->initvals0->size / sizeof(struct bcm43xx_initval));
2122         if (err)
2123                 goto out;
2124         if (bcm->initvals1) {
2125                 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)bcm->initvals1->data,
2126                                              bcm->initvals1->size / sizeof(struct bcm43xx_initval));
2127                 if (err)
2128                         goto out;
2129         }
2130 out:
2131         return err;
2132 }
2133
2134 static int bcm43xx_initialize_irq(struct bcm43xx_private *bcm)
2135 {
2136         int res;
2137         unsigned int i;
2138         u32 data;
2139
2140         bcm->irq = bcm->pci_dev->irq;
2141 #ifdef CONFIG_BCM947XX
2142         if (bcm->pci_dev->bus->number == 0) {
2143                 struct pci_dev *d = NULL;
2144                 /* FIXME: we will probably need more device IDs here... */
2145                 d = pci_find_device(PCI_VENDOR_ID_BROADCOM, 0x4324, NULL);
2146                 if (d != NULL) {
2147                         bcm->irq = d->irq;
2148                 }
2149         }
2150 #endif
2151         res = request_irq(bcm->irq, bcm43xx_interrupt_handler,
2152                           SA_SHIRQ, KBUILD_MODNAME, bcm);
2153         if (res) {
2154                 printk(KERN_ERR PFX "Cannot register IRQ%d\n", bcm->irq);
2155                 return -ENODEV;
2156         }
2157         bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0xffffffff);
2158         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, 0x00020402);
2159         i = 0;
2160         while (1) {
2161                 data = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2162                 if (data == BCM43xx_IRQ_READY)
2163                         break;
2164                 i++;
2165                 if (i >= BCM43xx_IRQWAIT_MAX_RETRIES) {
2166                         printk(KERN_ERR PFX "Card IRQ register not responding. "
2167                                             "Giving up.\n");
2168                         free_irq(bcm->irq, bcm);
2169                         return -ENODEV;
2170                 }
2171                 udelay(10);
2172         }
2173         // dummy read
2174         bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2175
2176         return 0;
2177 }
2178
2179 /* Switch to the core used to write the GPIO register.
2180  * This is either the ChipCommon, or the PCI core.
2181  */
2182 static int switch_to_gpio_core(struct bcm43xx_private *bcm)
2183 {
2184         int err;
2185
2186         /* Where to find the GPIO register depends on the chipset.
2187          * If it has a ChipCommon, its register at offset 0x6c is the GPIO
2188          * control register. Otherwise the register at offset 0x6c in the
2189          * PCI core is the GPIO control register.
2190          */
2191         err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
2192         if (err == -ENODEV) {
2193                 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2194                 if (unlikely(err == -ENODEV)) {
2195                         printk(KERN_ERR PFX "gpio error: "
2196                                "Neither ChipCommon nor PCI core available!\n");
2197                 }
2198         }
2199
2200         return err;
2201 }
2202
2203 /* Initialize the GPIOs
2204  * http://bcm-specs.sipsolutions.net/GPIO
2205  */
2206 static int bcm43xx_gpio_init(struct bcm43xx_private *bcm)
2207 {
2208         struct bcm43xx_coreinfo *old_core;
2209         int err;
2210         u32 mask, set;
2211
2212         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2213                         bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2214                         & 0xFFFF3FFF);
2215
2216         bcm43xx_leds_switch_all(bcm, 0);
2217         bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2218                         bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK) | 0x000F);
2219
2220         mask = 0x0000001F;
2221         set = 0x0000000F;
2222         if (bcm->chip_id == 0x4301) {
2223                 mask |= 0x0060;
2224                 set |= 0x0060;
2225         }
2226         if (0 /* FIXME: conditional unknown */) {
2227                 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2228                                 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2229                                 | 0x0100);
2230                 mask |= 0x0180;
2231                 set |= 0x0180;
2232         }
2233         if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL) {
2234                 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2235                                 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2236                                 | 0x0200);
2237                 mask |= 0x0200;
2238                 set |= 0x0200;
2239         }
2240         if (bcm->current_core->rev >= 2)
2241                 mask  |= 0x0010; /* FIXME: This is redundant. */
2242
2243         old_core = bcm->current_core;
2244         err = switch_to_gpio_core(bcm);
2245         if (err)
2246                 goto out;
2247         bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL,
2248                         (bcm43xx_read32(bcm, BCM43xx_GPIO_CONTROL) & mask) | set);
2249         err = bcm43xx_switch_core(bcm, old_core);
2250 out:
2251         return err;
2252 }
2253
2254 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2255 static int bcm43xx_gpio_cleanup(struct bcm43xx_private *bcm)
2256 {
2257         struct bcm43xx_coreinfo *old_core;
2258         int err;
2259
2260         old_core = bcm->current_core;
2261         err = switch_to_gpio_core(bcm);
2262         if (err)
2263                 return err;
2264         bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL, 0x00000000);
2265         err = bcm43xx_switch_core(bcm, old_core);
2266         assert(err == 0);
2267
2268         return 0;
2269 }
2270
2271 /* http://bcm-specs.sipsolutions.net/EnableMac */
2272 void bcm43xx_mac_enable(struct bcm43xx_private *bcm)
2273 {
2274         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2275                         bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2276                         | BCM43xx_SBF_MAC_ENABLED);
2277         bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, BCM43xx_IRQ_READY);
2278         bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
2279         bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2280         bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
2281 }
2282
2283 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2284 void bcm43xx_mac_suspend(struct bcm43xx_private *bcm)
2285 {
2286         int i;
2287         u32 tmp;
2288
2289         bcm43xx_power_saving_ctl_bits(bcm, -1, 1);
2290         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2291                         bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2292                         & ~BCM43xx_SBF_MAC_ENABLED);
2293         bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2294         for (i = 100000; i; i--) {
2295                 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2296                 if (tmp & BCM43xx_IRQ_READY)
2297                         return;
2298                 udelay(10);
2299         }
2300         printkl(KERN_ERR PFX "MAC suspend failed\n");
2301 }
2302
2303 void bcm43xx_set_iwmode(struct bcm43xx_private *bcm,
2304                         int iw_mode)
2305 {
2306         unsigned long flags;
2307         struct net_device *net_dev = bcm->net_dev;
2308         u32 status;
2309         u16 value;
2310
2311         spin_lock_irqsave(&bcm->ieee->lock, flags);
2312         bcm->ieee->iw_mode = iw_mode;
2313         spin_unlock_irqrestore(&bcm->ieee->lock, flags);
2314         if (iw_mode == IW_MODE_MONITOR)
2315                 net_dev->type = ARPHRD_IEEE80211;
2316         else
2317                 net_dev->type = ARPHRD_ETHER;
2318
2319         status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2320         /* Reset status to infrastructured mode */
2321         status &= ~(BCM43xx_SBF_MODE_AP | BCM43xx_SBF_MODE_MONITOR);
2322         status &= ~BCM43xx_SBF_MODE_PROMISC;
2323         status |= BCM43xx_SBF_MODE_NOTADHOC;
2324
2325 /* FIXME: Always enable promisc mode, until we get the MAC filters working correctly. */
2326 status |= BCM43xx_SBF_MODE_PROMISC;
2327
2328         switch (iw_mode) {
2329         case IW_MODE_MONITOR:
2330                 status |= BCM43xx_SBF_MODE_MONITOR;
2331                 status |= BCM43xx_SBF_MODE_PROMISC;
2332                 break;
2333         case IW_MODE_ADHOC:
2334                 status &= ~BCM43xx_SBF_MODE_NOTADHOC;
2335                 break;
2336         case IW_MODE_MASTER:
2337                 status |= BCM43xx_SBF_MODE_AP;
2338                 break;
2339         case IW_MODE_SECOND:
2340         case IW_MODE_REPEAT:
2341                 TODO(); /* TODO */
2342                 break;
2343         case IW_MODE_INFRA:
2344                 /* nothing to be done here... */
2345                 break;
2346         default:
2347                 dprintk(KERN_ERR PFX "Unknown mode in set_iwmode: %d\n", iw_mode);
2348         }
2349         if (net_dev->flags & IFF_PROMISC)
2350                 status |= BCM43xx_SBF_MODE_PROMISC;
2351         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
2352
2353         value = 0x0002;
2354         if (iw_mode != IW_MODE_ADHOC && iw_mode != IW_MODE_MASTER) {
2355                 if (bcm->chip_id == 0x4306 && bcm->chip_rev == 3)
2356                         value = 0x0064;
2357                 else
2358                         value = 0x0032;
2359         }
2360         bcm43xx_write16(bcm, 0x0612, value);
2361 }
2362
2363 /* This is the opposite of bcm43xx_chip_init() */
2364 static void bcm43xx_chip_cleanup(struct bcm43xx_private *bcm)
2365 {
2366         bcm43xx_radio_turn_off(bcm);
2367         if (!modparam_noleds)
2368                 bcm43xx_leds_exit(bcm);
2369         bcm43xx_gpio_cleanup(bcm);
2370         free_irq(bcm->irq, bcm);
2371         bcm43xx_release_firmware(bcm, 0);
2372 }
2373
2374 /* Initialize the chip
2375  * http://bcm-specs.sipsolutions.net/ChipInit
2376  */
2377 static int bcm43xx_chip_init(struct bcm43xx_private *bcm)
2378 {
2379         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2380         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2381         int err;
2382         int tmp;
2383         u32 value32;
2384         u16 value16;
2385
2386         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2387                         BCM43xx_SBF_CORE_READY
2388                         | BCM43xx_SBF_400);
2389
2390         err = bcm43xx_request_firmware(bcm);
2391         if (err)
2392                 goto out;
2393         bcm43xx_upload_microcode(bcm);
2394
2395         err = bcm43xx_initialize_irq(bcm);
2396         if (err)
2397                 goto err_release_fw;
2398
2399         err = bcm43xx_gpio_init(bcm);
2400         if (err)
2401                 goto err_free_irq;
2402
2403         err = bcm43xx_upload_initvals(bcm);
2404         if (err)
2405                 goto err_gpio_cleanup;
2406         bcm43xx_radio_turn_on(bcm);
2407
2408         bcm43xx_write16(bcm, 0x03E6, 0x0000);
2409         err = bcm43xx_phy_init(bcm);
2410         if (err)
2411                 goto err_radio_off;
2412
2413         /* Select initial Interference Mitigation. */
2414         tmp = radio->interfmode;
2415         radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2416         bcm43xx_radio_set_interference_mitigation(bcm, tmp);
2417
2418         bcm43xx_phy_set_antenna_diversity(bcm);
2419         bcm43xx_radio_set_txantenna(bcm, BCM43xx_RADIO_TXANTENNA_DEFAULT);
2420         if (phy->type == BCM43xx_PHYTYPE_B) {
2421                 value16 = bcm43xx_read16(bcm, 0x005E);
2422                 value16 |= 0x0004;
2423                 bcm43xx_write16(bcm, 0x005E, value16);
2424         }
2425         bcm43xx_write32(bcm, 0x0100, 0x01000000);
2426         if (bcm->current_core->rev < 5)
2427                 bcm43xx_write32(bcm, 0x010C, 0x01000000);
2428
2429         value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2430         value32 &= ~ BCM43xx_SBF_MODE_NOTADHOC;
2431         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2432         value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2433         value32 |= BCM43xx_SBF_MODE_NOTADHOC;
2434         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2435
2436         value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2437         value32 |= 0x100000;
2438         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2439
2440         if (bcm43xx_using_pio(bcm)) {
2441                 bcm43xx_write32(bcm, 0x0210, 0x00000100);
2442                 bcm43xx_write32(bcm, 0x0230, 0x00000100);
2443                 bcm43xx_write32(bcm, 0x0250, 0x00000100);
2444                 bcm43xx_write32(bcm, 0x0270, 0x00000100);
2445                 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0034, 0x0000);
2446         }
2447
2448         /* Probe Response Timeout value */
2449         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2450         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0074, 0x0000);
2451
2452         /* Initially set the wireless operation mode. */
2453         bcm43xx_set_iwmode(bcm, bcm->ieee->iw_mode);
2454
2455         if (bcm->current_core->rev < 3) {
2456                 bcm43xx_write16(bcm, 0x060E, 0x0000);
2457                 bcm43xx_write16(bcm, 0x0610, 0x8000);
2458                 bcm43xx_write16(bcm, 0x0604, 0x0000);
2459                 bcm43xx_write16(bcm, 0x0606, 0x0200);
2460         } else {
2461                 bcm43xx_write32(bcm, 0x0188, 0x80000000);
2462                 bcm43xx_write32(bcm, 0x018C, 0x02000000);
2463         }
2464         bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0x00004000);
2465         bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_IRQ_MASK, 0x0001DC00);
2466         bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2467         bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_IRQ_MASK, 0x0000DC00);
2468         bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_IRQ_MASK, 0x0001DC00);
2469
2470         value32 = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
2471         value32 |= 0x00100000;
2472         bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, value32);
2473
2474         bcm43xx_write16(bcm, BCM43xx_MMIO_POWERUP_DELAY, bcm43xx_pctl_powerup_delay(bcm));
2475
2476         assert(err == 0);
2477         dprintk(KERN_INFO PFX "Chip initialized\n");
2478 out:
2479         return err;
2480
2481 err_radio_off:
2482         bcm43xx_radio_turn_off(bcm);
2483 err_gpio_cleanup:
2484         bcm43xx_gpio_cleanup(bcm);
2485 err_free_irq:
2486         free_irq(bcm->irq, bcm);
2487 err_release_fw:
2488         bcm43xx_release_firmware(bcm, 1);
2489         goto out;
2490 }
2491
2492 /* Validate chip access
2493  * http://bcm-specs.sipsolutions.net/ValidateChipAccess */
2494 static int bcm43xx_validate_chip(struct bcm43xx_private *bcm)
2495 {
2496         u32 value;
2497         u32 shm_backup;
2498
2499         shm_backup = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000);
2500         bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0xAA5555AA);
2501         if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0xAA5555AA)
2502                 goto error;
2503         bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0x55AAAA55);
2504         if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0x55AAAA55)
2505                 goto error;
2506         bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, shm_backup);
2507
2508         value = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2509         if ((value | 0x80000000) != 0x80000400)
2510                 goto error;
2511
2512         value = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2513         if (value != 0x00000000)
2514                 goto error;
2515
2516         return 0;
2517 error:
2518         printk(KERN_ERR PFX "Failed to validate the chipaccess\n");
2519         return -ENODEV;
2520 }
2521
2522 static void bcm43xx_init_struct_phyinfo(struct bcm43xx_phyinfo *phy)
2523 {
2524         /* Initialize a "phyinfo" structure. The structure is already
2525          * zeroed out.
2526          */
2527         phy->antenna_diversity = 0xFFFF;
2528         phy->savedpctlreg = 0xFFFF;
2529         phy->minlowsig[0] = 0xFFFF;
2530         phy->minlowsig[1] = 0xFFFF;
2531         spin_lock_init(&phy->lock);
2532 }
2533
2534 static void bcm43xx_init_struct_radioinfo(struct bcm43xx_radioinfo *radio)
2535 {
2536         /* Initialize a "radioinfo" structure. The structure is already
2537          * zeroed out.
2538          */
2539         radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2540         radio->channel = 0xFF;
2541         radio->initial_channel = 0xFF;
2542         radio->lofcal = 0xFFFF;
2543         radio->initval = 0xFFFF;
2544         radio->nrssi[0] = -1000;
2545         radio->nrssi[1] = -1000;
2546 }
2547
2548 static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
2549 {
2550         int err, i;
2551         int current_core;
2552         u32 core_vendor, core_id, core_rev;
2553         u32 sb_id_hi, chip_id_32 = 0;
2554         u16 pci_device, chip_id_16;
2555         u8 core_count;
2556
2557         memset(&bcm->core_chipcommon, 0, sizeof(struct bcm43xx_coreinfo));
2558         memset(&bcm->core_pci, 0, sizeof(struct bcm43xx_coreinfo));
2559         memset(&bcm->core_80211, 0, sizeof(struct bcm43xx_coreinfo)
2560                                     * BCM43xx_MAX_80211_CORES);
2561         memset(&bcm->core_80211_ext, 0, sizeof(struct bcm43xx_coreinfo_80211)
2562                                         * BCM43xx_MAX_80211_CORES);
2563         bcm->current_80211_core_idx = -1;
2564         bcm->nr_80211_available = 0;
2565         bcm->current_core = NULL;
2566         bcm->active_80211_core = NULL;
2567
2568         /* map core 0 */
2569         err = _switch_core(bcm, 0);
2570         if (err)
2571                 goto out;
2572
2573         /* fetch sb_id_hi from core information registers */
2574         sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2575
2576         core_id = (sb_id_hi & 0xFFF0) >> 4;
2577         core_rev = (sb_id_hi & 0xF);
2578         core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2579
2580         /* if present, chipcommon is always core 0; read the chipid from it */
2581         if (core_id == BCM43xx_COREID_CHIPCOMMON) {
2582                 chip_id_32 = bcm43xx_read32(bcm, 0);
2583                 chip_id_16 = chip_id_32 & 0xFFFF;
2584                 bcm->core_chipcommon.available = 1;
2585                 bcm->core_chipcommon.id = core_id;
2586                 bcm->core_chipcommon.rev = core_rev;
2587                 bcm->core_chipcommon.index = 0;
2588                 /* While we are at it, also read the capabilities. */
2589                 bcm->chipcommon_capabilities = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_CAPABILITIES);
2590         } else {
2591                 /* without a chipCommon, use a hard coded table. */
2592                 pci_device = bcm->pci_dev->device;
2593                 if (pci_device == 0x4301)
2594                         chip_id_16 = 0x4301;
2595                 else if ((pci_device >= 0x4305) && (pci_device <= 0x4307))
2596                         chip_id_16 = 0x4307;
2597                 else if ((pci_device >= 0x4402) && (pci_device <= 0x4403))
2598                         chip_id_16 = 0x4402;
2599                 else if ((pci_device >= 0x4610) && (pci_device <= 0x4615))
2600                         chip_id_16 = 0x4610;
2601                 else if ((pci_device >= 0x4710) && (pci_device <= 0x4715))
2602                         chip_id_16 = 0x4710;
2603 #ifdef CONFIG_BCM947XX
2604                 else if ((pci_device >= 0x4320) && (pci_device <= 0x4325))
2605                         chip_id_16 = 0x4309;
2606 #endif
2607                 else {
2608                         printk(KERN_ERR PFX "Could not determine Chip ID\n");
2609                         return -ENODEV;
2610                 }
2611         }
2612
2613         /* ChipCommon with Core Rev >=4 encodes number of cores,
2614          * otherwise consult hardcoded table */
2615         if ((core_id == BCM43xx_COREID_CHIPCOMMON) && (core_rev >= 4)) {
2616                 core_count = (chip_id_32 & 0x0F000000) >> 24;
2617         } else {
2618                 switch (chip_id_16) {
2619                         case 0x4610:
2620                         case 0x4704:
2621                         case 0x4710:
2622                                 core_count = 9;
2623                                 break;
2624                         case 0x4310:
2625                                 core_count = 8;
2626                                 break;
2627                         case 0x5365:
2628                                 core_count = 7;
2629                                 break;
2630                         case 0x4306:
2631                                 core_count = 6;
2632                                 break;
2633                         case 0x4301:
2634                         case 0x4307:
2635                                 core_count = 5;
2636                                 break;
2637                         case 0x4402:
2638                                 core_count = 3;
2639                                 break;
2640                         default:
2641                                 /* SOL if we get here */
2642                                 assert(0);
2643                                 core_count = 1;
2644                 }
2645         }
2646
2647         bcm->chip_id = chip_id_16;
2648         bcm->chip_rev = (chip_id_32 & 0x000F0000) >> 16;
2649         bcm->chip_package = (chip_id_32 & 0x00F00000) >> 20;
2650
2651         dprintk(KERN_INFO PFX "Chip ID 0x%x, rev 0x%x\n",
2652                 bcm->chip_id, bcm->chip_rev);
2653         dprintk(KERN_INFO PFX "Number of cores: %d\n", core_count);
2654         if (bcm->core_chipcommon.available) {
2655                 dprintk(KERN_INFO PFX "Core 0: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
2656                         core_id, core_rev, core_vendor,
2657                         bcm43xx_core_enabled(bcm) ? "enabled" : "disabled");
2658         }
2659
2660         if (bcm->core_chipcommon.available)
2661                 current_core = 1;
2662         else
2663                 current_core = 0;
2664         for ( ; current_core < core_count; current_core++) {
2665                 struct bcm43xx_coreinfo *core;
2666                 struct bcm43xx_coreinfo_80211 *ext_80211;
2667
2668                 err = _switch_core(bcm, current_core);
2669                 if (err)
2670                         goto out;
2671                 /* Gather information */
2672                 /* fetch sb_id_hi from core information registers */
2673                 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2674
2675                 /* extract core_id, core_rev, core_vendor */
2676                 core_id = (sb_id_hi & 0xFFF0) >> 4;
2677                 core_rev = (sb_id_hi & 0xF);
2678                 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2679
2680                 dprintk(KERN_INFO PFX "Core %d: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
2681                         current_core, core_id, core_rev, core_vendor,
2682                         bcm43xx_core_enabled(bcm) ? "enabled" : "disabled" );
2683
2684                 core = NULL;
2685                 switch (core_id) {
2686                 case BCM43xx_COREID_PCI:
2687                         core = &bcm->core_pci;
2688                         if (core->available) {
2689                                 printk(KERN_WARNING PFX "Multiple PCI cores found.\n");
2690                                 continue;
2691                         }
2692                         break;
2693                 case BCM43xx_COREID_80211:
2694                         for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
2695                                 core = &(bcm->core_80211[i]);
2696                                 ext_80211 = &(bcm->core_80211_ext[i]);
2697                                 if (!core->available)
2698                                         break;
2699                                 core = NULL;
2700                         }
2701                         if (!core) {
2702                                 printk(KERN_WARNING PFX "More than %d cores of type 802.11 found.\n",
2703                                        BCM43xx_MAX_80211_CORES);
2704                                 continue;
2705                         }
2706                         if (i != 0) {
2707                                 /* More than one 80211 core is only supported
2708                                  * by special chips.
2709                                  * There are chips with two 80211 cores, but with
2710                                  * dangling pins on the second core. Be careful
2711                                  * and ignore these cores here.
2712                                  */
2713                                 if (bcm->pci_dev->device != 0x4324) {
2714                                         dprintk(KERN_INFO PFX "Ignoring additional 802.11 core.\n");
2715                                         continue;
2716                                 }
2717                         }
2718                         switch (core_rev) {
2719                         case 2:
2720                         case 4:
2721                         case 5:
2722                         case 6:
2723                         case 7:
2724                         case 9:
2725                                 break;
2726                         default:
2727                                 printk(KERN_ERR PFX "Error: Unsupported 80211 core revision %u\n",
2728                                        core_rev);
2729                                 err = -ENODEV;
2730                                 goto out;
2731                         }
2732                         bcm->nr_80211_available++;
2733                         bcm43xx_init_struct_phyinfo(&ext_80211->phy);
2734                         bcm43xx_init_struct_radioinfo(&ext_80211->radio);
2735                         break;
2736                 case BCM43xx_COREID_CHIPCOMMON:
2737                         printk(KERN_WARNING PFX "Multiple CHIPCOMMON cores found.\n");
2738                         break;
2739                 }
2740                 if (core) {
2741                         core->available = 1;
2742                         core->id = core_id;
2743                         core->rev = core_rev;
2744                         core->index = current_core;
2745                 }
2746         }
2747
2748         if (!bcm->core_80211[0].available) {
2749                 printk(KERN_ERR PFX "Error: No 80211 core found!\n");
2750                 err = -ENODEV;
2751                 goto out;
2752         }
2753
2754         err = bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
2755
2756         assert(err == 0);
2757 out:
2758         return err;
2759 }
2760
2761 static void bcm43xx_gen_bssid(struct bcm43xx_private *bcm)
2762 {
2763         const u8 *mac = (const u8*)(bcm->net_dev->dev_addr);
2764         u8 *bssid = bcm->ieee->bssid;
2765
2766         switch (bcm->ieee->iw_mode) {
2767         case IW_MODE_ADHOC:
2768                 random_ether_addr(bssid);
2769                 break;
2770         case IW_MODE_MASTER:
2771         case IW_MODE_INFRA:
2772         case IW_MODE_REPEAT:
2773         case IW_MODE_SECOND:
2774         case IW_MODE_MONITOR:
2775                 memcpy(bssid, mac, ETH_ALEN);
2776                 break;
2777         default:
2778                 assert(0);
2779         }
2780 }
2781
2782 static void bcm43xx_rate_memory_write(struct bcm43xx_private *bcm,
2783                                       u16 rate,
2784                                       int is_ofdm)
2785 {
2786         u16 offset;
2787
2788         if (is_ofdm) {
2789                 offset = 0x480;
2790                 offset += (bcm43xx_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2791         }
2792         else {
2793                 offset = 0x4C0;
2794                 offset += (bcm43xx_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2795         }
2796         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, offset + 0x20,
2797                             bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, offset));
2798 }
2799
2800 static void bcm43xx_rate_memory_init(struct bcm43xx_private *bcm)
2801 {
2802         switch (bcm43xx_current_phy(bcm)->type) {
2803         case BCM43xx_PHYTYPE_A:
2804         case BCM43xx_PHYTYPE_G:
2805                 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_6MB, 1);
2806                 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_12MB, 1);
2807                 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_18MB, 1);
2808                 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_24MB, 1);
2809                 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_36MB, 1);
2810                 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_48MB, 1);
2811                 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_54MB, 1);
2812         case BCM43xx_PHYTYPE_B:
2813                 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_1MB, 0);
2814                 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_2MB, 0);
2815                 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_5MB, 0);
2816                 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_11MB, 0);
2817                 break;
2818         default:
2819                 assert(0);
2820         }
2821 }
2822
2823 static void bcm43xx_wireless_core_cleanup(struct bcm43xx_private *bcm)
2824 {
2825         bcm43xx_chip_cleanup(bcm);
2826         bcm43xx_pio_free(bcm);
2827         bcm43xx_dma_free(bcm);
2828
2829         bcm->current_core->initialized = 0;
2830 }
2831
2832 /* http://bcm-specs.sipsolutions.net/80211Init */
2833 static int bcm43xx_wireless_core_init(struct bcm43xx_private *bcm)
2834 {
2835         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2836         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2837         u32 ucodeflags;
2838         int err;
2839         u32 sbimconfiglow;
2840         u8 limit;
2841
2842         if (bcm->chip_rev < 5) {
2843                 sbimconfiglow = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
2844                 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
2845                 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
2846                 if (bcm->bustype == BCM43xx_BUSTYPE_PCI)
2847                         sbimconfiglow |= 0x32;
2848                 else if (bcm->bustype == BCM43xx_BUSTYPE_SB)
2849                         sbimconfiglow |= 0x53;
2850                 else
2851                         assert(0);
2852                 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, sbimconfiglow);
2853         }
2854
2855         bcm43xx_phy_calibrate(bcm);
2856         err = bcm43xx_chip_init(bcm);
2857         if (err)
2858                 goto out;
2859
2860         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0016, bcm->current_core->rev);
2861         ucodeflags = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, BCM43xx_UCODEFLAGS_OFFSET);
2862
2863         if (0 /*FIXME: which condition has to be used here? */)
2864                 ucodeflags |= 0x00000010;
2865
2866         /* HW decryption needs to be set now */
2867         ucodeflags |= 0x40000000;
2868
2869         if (phy->type == BCM43xx_PHYTYPE_G) {
2870                 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
2871                 if (phy->rev == 1)
2872                         ucodeflags |= BCM43xx_UCODEFLAG_UNKGPHY;
2873                 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL)
2874                         ucodeflags |= BCM43xx_UCODEFLAG_UNKPACTRL;
2875         } else if (phy->type == BCM43xx_PHYTYPE_B) {
2876                 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
2877                 if (phy->rev >= 2 && radio->version == 0x2050)
2878                         ucodeflags &= ~BCM43xx_UCODEFLAG_UNKGPHY;
2879         }
2880
2881         if (ucodeflags != bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
2882                                              BCM43xx_UCODEFLAGS_OFFSET)) {
2883                 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
2884                                     BCM43xx_UCODEFLAGS_OFFSET, ucodeflags);
2885         }
2886
2887         /* Short/Long Retry Limit.
2888          * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
2889          * the chip-internal counter.
2890          */
2891         limit = limit_value(modparam_short_retry, 0, 0xF);
2892         bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0006, limit);
2893         limit = limit_value(modparam_long_retry, 0, 0xF);
2894         bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0007, limit);
2895
2896         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0044, 3);
2897         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0046, 2);
2898
2899         bcm43xx_rate_memory_init(bcm);
2900
2901         /* Minimum Contention Window */
2902         if (phy->type == BCM43xx_PHYTYPE_B)
2903                 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000001f);
2904         else
2905                 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000000f);
2906         /* Maximum Contention Window */
2907         bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
2908
2909         bcm43xx_gen_bssid(bcm);
2910         bcm43xx_write_mac_bssid_templates(bcm);
2911
2912         if (bcm->current_core->rev >= 5)
2913                 bcm43xx_write16(bcm, 0x043C, 0x000C);
2914
2915         if (bcm43xx_using_pio(bcm))
2916                 err = bcm43xx_pio_init(bcm);
2917         else
2918                 err = bcm43xx_dma_init(bcm);
2919         if (err)
2920                 goto err_chip_cleanup;
2921         bcm43xx_write16(bcm, 0x0612, 0x0050);
2922         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0416, 0x0050);
2923         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0414, 0x01F4);
2924
2925         bcm43xx_mac_enable(bcm);
2926         bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
2927
2928         bcm->current_core->initialized = 1;
2929 out:
2930         return err;
2931
2932 err_chip_cleanup:
2933         bcm43xx_chip_cleanup(bcm);
2934         goto out;
2935 }
2936
2937 static int bcm43xx_chipset_attach(struct bcm43xx_private *bcm)
2938 {
2939         int err;
2940         u16 pci_status;
2941
2942         err = bcm43xx_pctl_set_crystal(bcm, 1);
2943         if (err)
2944                 goto out;
2945         bcm43xx_pci_read_config16(bcm, PCI_STATUS, &pci_status);
2946         bcm43xx_pci_write_config16(bcm, PCI_STATUS, pci_status & ~PCI_STATUS_SIG_TARGET_ABORT);
2947
2948 out:
2949         return err;
2950 }
2951
2952 static void bcm43xx_chipset_detach(struct bcm43xx_private *bcm)
2953 {
2954         bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
2955         bcm43xx_pctl_set_crystal(bcm, 0);
2956 }
2957
2958 static void bcm43xx_pcicore_broadcast_value(struct bcm43xx_private *bcm,
2959                                             u32 address,
2960                                             u32 data)
2961 {
2962         bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_ADDR, address);
2963         bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_DATA, data);
2964 }
2965
2966 static int bcm43xx_pcicore_commit_settings(struct bcm43xx_private *bcm)
2967 {
2968         int err;
2969         struct bcm43xx_coreinfo *old_core;
2970
2971         old_core = bcm->current_core;
2972         err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2973         if (err)
2974                 goto out;
2975
2976         bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
2977
2978         bcm43xx_switch_core(bcm, old_core);
2979         assert(err == 0);
2980 out:
2981         return err;
2982 }
2983
2984 /* Make an I/O Core usable. "core_mask" is the bitmask of the cores to enable.
2985  * To enable core 0, pass a core_mask of 1<<0
2986  */
2987 static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private *bcm,
2988                                                   u32 core_mask)
2989 {
2990         u32 backplane_flag_nr;
2991         u32 value;
2992         struct bcm43xx_coreinfo *old_core;
2993         int err = 0;
2994
2995         value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTPSFLAG);
2996         backplane_flag_nr = value & BCM43xx_BACKPLANE_FLAG_NR_MASK;
2997
2998         old_core = bcm->current_core;
2999         err = bcm43xx_switch_core(bcm, &bcm->core_pci);
3000         if (err)
3001                 goto out;
3002
3003         if (bcm->core_pci.rev < 6) {
3004                 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBINTVEC);
3005                 value |= (1 << backplane_flag_nr);
3006                 bcm43xx_write32(bcm, BCM43xx_CIR_SBINTVEC, value);
3007         } else {
3008                 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ICR, &value);
3009                 if (err) {
3010                         printk(KERN_ERR PFX "Error: ICR setup failure!\n");
3011                         goto out_switch_back;
3012                 }
3013                 value |= core_mask << 8;
3014                 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ICR, value);
3015                 if (err) {
3016                         printk(KERN_ERR PFX "Error: ICR setup failure!\n");
3017                         goto out_switch_back;
3018                 }
3019         }
3020
3021         value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
3022         value |= BCM43xx_SBTOPCI2_PREFETCH | BCM43xx_SBTOPCI2_BURST;
3023         bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
3024
3025         if (bcm->core_pci.rev < 5) {
3026                 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
3027                 value |= (2 << BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT)
3028                          & BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
3029                 value |= (3 << BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT)
3030                          & BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
3031                 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, value);
3032                 err = bcm43xx_pcicore_commit_settings(bcm);
3033                 assert(err == 0);
3034         }
3035
3036 out_switch_back:
3037         err = bcm43xx_switch_core(bcm, old_core);
3038 out:
3039         return err;
3040 }
3041
3042 static void bcm43xx_softmac_init(struct bcm43xx_private *bcm)
3043 {
3044         ieee80211softmac_start(bcm->net_dev);
3045 }
3046
3047 static void bcm43xx_periodic_every120sec(struct bcm43xx_private *bcm)
3048 {
3049         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3050
3051         if (phy->type != BCM43xx_PHYTYPE_G || phy->rev < 2)
3052                 return;
3053
3054         bcm43xx_mac_suspend(bcm);
3055         bcm43xx_phy_lo_g_measure(bcm);
3056         bcm43xx_mac_enable(bcm);
3057 }
3058
3059 static void bcm43xx_periodic_every60sec(struct bcm43xx_private *bcm)
3060 {
3061         bcm43xx_phy_lo_mark_all_unused(bcm);
3062         if (bcm->sprom.boardflags & BCM43xx_BFL_RSSI) {
3063                 bcm43xx_mac_suspend(bcm);
3064                 bcm43xx_calc_nrssi_slope(bcm);
3065                 bcm43xx_mac_enable(bcm);
3066         }
3067 }
3068
3069 static void bcm43xx_periodic_every30sec(struct bcm43xx_private *bcm)
3070 {
3071         /* Update device statistics. */
3072         bcm43xx_calculate_link_quality(bcm);
3073 }
3074
3075 static void bcm43xx_periodic_every15sec(struct bcm43xx_private *bcm)
3076 {
3077         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3078         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
3079
3080         if (phy->type == BCM43xx_PHYTYPE_G) {
3081                 //TODO: update_aci_moving_average
3082                 if (radio->aci_enable && radio->aci_wlan_automatic) {
3083                         bcm43xx_mac_suspend(bcm);
3084                         if (!radio->aci_enable && 1 /*TODO: not scanning? */) {
3085                                 if (0 /*TODO: bunch of conditions*/) {
3086                                         bcm43xx_radio_set_interference_mitigation(bcm,
3087                                                                                   BCM43xx_RADIO_INTERFMODE_MANUALWLAN);
3088                                 }
3089                         } else if (1/*TODO*/) {
3090                                 /*
3091                                 if ((aci_average > 1000) && !(bcm43xx_radio_aci_scan(bcm))) {
3092                                         bcm43xx_radio_set_interference_mitigation(bcm,
3093                                                                                   BCM43xx_RADIO_INTERFMODE_NONE);
3094                                 }
3095                                 */
3096                         }
3097                         bcm43xx_mac_enable(bcm);
3098                 } else if (radio->interfmode == BCM43xx_RADIO_INTERFMODE_NONWLAN &&
3099                            phy->rev == 1) {
3100                         //TODO: implement rev1 workaround
3101                 }
3102         }
3103         bcm43xx_phy_xmitpower(bcm); //FIXME: unless scanning?
3104         //TODO for APHY (temperature?)
3105 }
3106
3107 static void bcm43xx_periodic_task_handler(unsigned long d)
3108 {
3109         struct bcm43xx_private *bcm = (struct bcm43xx_private *)d;
3110         unsigned long flags;
3111         unsigned int state;
3112
3113         bcm43xx_lock_mmio(bcm, flags);
3114
3115         assert(bcm->initialized);
3116         state = bcm->periodic_state;
3117         if (state % 8 == 0)
3118                 bcm43xx_periodic_every120sec(bcm);
3119         if (state % 4 == 0)
3120                 bcm43xx_periodic_every60sec(bcm);
3121         if (state % 2 == 0)
3122                 bcm43xx_periodic_every30sec(bcm);
3123         bcm43xx_periodic_every15sec(bcm);
3124         bcm->periodic_state = state + 1;
3125
3126         mod_timer(&bcm->periodic_tasks, jiffies + (HZ * 15));
3127
3128         bcm43xx_unlock_mmio(bcm, flags);
3129 }
3130
3131 static void bcm43xx_periodic_tasks_delete(struct bcm43xx_private *bcm)
3132 {
3133         del_timer_sync(&bcm->periodic_tasks);
3134 }
3135
3136 static void bcm43xx_periodic_tasks_setup(struct bcm43xx_private *bcm)
3137 {
3138         struct timer_list *timer = &(bcm->periodic_tasks);
3139
3140         assert(bcm->initialized);
3141         setup_timer(timer,
3142                     bcm43xx_periodic_task_handler,
3143                     (unsigned long)bcm);
3144         timer->expires = jiffies;
3145         add_timer(timer);
3146 }
3147
3148 static void bcm43xx_security_init(struct bcm43xx_private *bcm)
3149 {
3150         bcm->security_offset = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
3151                                                   0x0056) * 2;
3152         bcm43xx_clear_keys(bcm);
3153 }
3154
3155 /* This is the opposite of bcm43xx_init_board() */
3156 static void bcm43xx_free_board(struct bcm43xx_private *bcm)
3157 {
3158         int i, err;
3159         unsigned long flags;
3160
3161         bcm43xx_sysfs_unregister(bcm);
3162
3163         bcm43xx_periodic_tasks_delete(bcm);
3164
3165         bcm43xx_lock(bcm, flags);
3166         bcm->initialized = 0;
3167         bcm->shutting_down = 1;
3168         bcm43xx_unlock(bcm, flags);
3169
3170         for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3171                 if (!bcm->core_80211[i].available)
3172                         continue;
3173                 if (!bcm->core_80211[i].initialized)
3174                         continue;
3175
3176                 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3177                 assert(err == 0);
3178                 bcm43xx_wireless_core_cleanup(bcm);
3179         }
3180
3181         bcm43xx_pctl_set_crystal(bcm, 0);
3182
3183         bcm43xx_lock(bcm, flags);
3184         bcm->shutting_down = 0;
3185         bcm43xx_unlock(bcm, flags);
3186 }
3187
3188 static int bcm43xx_init_board(struct bcm43xx_private *bcm)
3189 {
3190         int i, err;
3191         int connect_phy;
3192         unsigned long flags;
3193
3194         might_sleep();
3195
3196         bcm43xx_lock(bcm, flags);
3197         bcm->initialized = 0;
3198         bcm->shutting_down = 0;
3199         bcm43xx_unlock(bcm, flags);
3200
3201         err = bcm43xx_pctl_set_crystal(bcm, 1);
3202         if (err)
3203                 goto out;
3204         err = bcm43xx_pctl_init(bcm);
3205         if (err)
3206                 goto err_crystal_off;
3207         err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_FAST);
3208         if (err)
3209                 goto err_crystal_off;
3210
3211         tasklet_enable(&bcm->isr_tasklet);
3212         for (i = 0; i < bcm->nr_80211_available; i++) {
3213                 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3214                 assert(err != -ENODEV);
3215                 if (err)
3216                         goto err_80211_unwind;
3217
3218                 /* Enable the selected wireless core.
3219                  * Connect PHY only on the first core.
3220                  */
3221                 if (!bcm43xx_core_enabled(bcm)) {
3222                         if (bcm->nr_80211_available == 1) {
3223                                 connect_phy = bcm43xx_current_phy(bcm)->connected;
3224                         } else {
3225                                 if (i == 0)
3226                                         connect_phy = 1;
3227                                 else
3228                                         connect_phy = 0;
3229                         }
3230                         bcm43xx_wireless_core_reset(bcm, connect_phy);
3231                 }
3232
3233                 if (i != 0)
3234                         bcm43xx_wireless_core_mark_inactive(bcm, &bcm->core_80211[0]);
3235
3236                 err = bcm43xx_wireless_core_init(bcm);
3237                 if (err)
3238                         goto err_80211_unwind;
3239
3240                 if (i != 0) {
3241                         bcm43xx_mac_suspend(bcm);
3242                         bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3243                         bcm43xx_radio_turn_off(bcm);
3244                 }
3245         }
3246         bcm->active_80211_core = &bcm->core_80211[0];
3247         if (bcm->nr_80211_available >= 2) {
3248                 bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
3249                 bcm43xx_mac_enable(bcm);
3250         }
3251         bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
3252         bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_SELF, (u8 *)(bcm->net_dev->dev_addr));
3253         dprintk(KERN_INFO PFX "80211 cores initialized\n");
3254         bcm43xx_security_init(bcm);
3255         bcm43xx_softmac_init(bcm);
3256
3257         bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_DYNAMIC);
3258
3259         if (bcm43xx_current_radio(bcm)->initial_channel != 0xFF) {
3260                 bcm43xx_mac_suspend(bcm);
3261                 bcm43xx_radio_selectchannel(bcm, bcm43xx_current_radio(bcm)->initial_channel, 0);
3262                 bcm43xx_mac_enable(bcm);
3263         }
3264
3265         /* Initialization of the board is done. Flag it as such. */
3266         bcm43xx_lock(bcm, flags);
3267         bcm->initialized = 1;
3268         bcm43xx_unlock(bcm, flags);
3269
3270         bcm43xx_periodic_tasks_setup(bcm);
3271         bcm43xx_sysfs_register(bcm);
3272         //FIXME: check for bcm43xx_sysfs_register failure. This function is a bit messy regarding unwinding, though...
3273
3274         /*FIXME: This should be handled by softmac instead. */
3275         schedule_work(&bcm->softmac->associnfo.work);
3276
3277         assert(err == 0);
3278 out:
3279         return err;
3280
3281 err_80211_unwind:
3282         tasklet_disable(&bcm->isr_tasklet);
3283         /* unwind all 80211 initialization */
3284         for (i = 0; i < bcm->nr_80211_available; i++) {
3285                 if (!bcm->core_80211[i].initialized)
3286                         continue;
3287                 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3288                 bcm43xx_wireless_core_cleanup(bcm);
3289         }
3290 err_crystal_off:
3291         bcm43xx_pctl_set_crystal(bcm, 0);
3292         goto out;
3293 }
3294
3295 static void bcm43xx_detach_board(struct bcm43xx_private *bcm)
3296 {
3297         struct pci_dev *pci_dev = bcm->pci_dev;
3298         int i;
3299
3300         bcm43xx_chipset_detach(bcm);
3301         /* Do _not_ access the chip, after it is detached. */
3302         iounmap(bcm->mmio_addr);
3303
3304         pci_release_regions(pci_dev);
3305         pci_disable_device(pci_dev);
3306
3307         /* Free allocated structures/fields */
3308         for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3309                 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3310                 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3311                         kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
3312         }
3313 }
3314
3315 static int bcm43xx_read_phyinfo(struct bcm43xx_private *bcm)
3316 {
3317         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3318         u16 value;
3319         u8 phy_version;
3320         u8 phy_type;
3321         u8 phy_rev;
3322         int phy_rev_ok = 1;
3323         void *p;
3324
3325         value = bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_VER);
3326
3327         phy_version = (value & 0xF000) >> 12;
3328         phy_type = (value & 0x0F00) >> 8;
3329         phy_rev = (value & 0x000F);
3330
3331         dprintk(KERN_INFO PFX "Detected PHY: Version: %x, Type %x, Revision %x\n",
3332                 phy_version, phy_type, phy_rev);
3333
3334         switch (phy_type) {
3335         case BCM43xx_PHYTYPE_A:
3336                 if (phy_rev >= 4)
3337                         phy_rev_ok = 0;
3338                 /*FIXME: We need to switch the ieee->modulation, etc.. flags,
3339                  *       if we switch 80211 cores after init is done.
3340                  *       As we do not implement on the fly switching between
3341                  *       wireless cores, I will leave this as a future task.
3342                  */
3343                 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION;
3344                 bcm->ieee->mode = IEEE_A;
3345                 bcm->ieee->freq_band = IEEE80211_52GHZ_BAND |
3346                                        IEEE80211_24GHZ_BAND;
3347                 break;
3348         case BCM43xx_PHYTYPE_B:
3349                 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 && phy_rev != 7)
3350                         phy_rev_ok = 0;
3351                 bcm->ieee->modulation = IEEE80211_CCK_MODULATION;
3352                 bcm->ieee->mode = IEEE_B;
3353                 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3354                 break;
3355         case BCM43xx_PHYTYPE_G:
3356                 if (phy_rev > 7)
3357                         phy_rev_ok = 0;
3358                 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION |
3359                                         IEEE80211_CCK_MODULATION;
3360                 bcm->ieee->mode = IEEE_G;
3361                 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3362                 break;
3363         default:
3364                 printk(KERN_ERR PFX "Error: Unknown PHY Type %x\n",
3365                        phy_type);
3366                 return -ENODEV;
3367         };
3368         if (!phy_rev_ok) {
3369                 printk(KERN_WARNING PFX "Invalid PHY Revision %x\n",
3370                        phy_rev);
3371         }
3372
3373         phy->version = phy_version;
3374         phy->type = phy_type;
3375         phy->rev = phy_rev;
3376         if ((phy_type == BCM43xx_PHYTYPE_B) || (phy_type == BCM43xx_PHYTYPE_G)) {
3377                 p = kzalloc(sizeof(struct bcm43xx_lopair) * BCM43xx_LO_COUNT,
3378                             GFP_KERNEL);
3379                 if (!p)
3380                         return -ENOMEM;
3381                 phy->_lo_pairs = p;
3382         }
3383
3384         return 0;
3385 }
3386
3387 static int bcm43xx_attach_board(struct bcm43xx_private *bcm)
3388 {
3389         struct pci_dev *pci_dev = bcm->pci_dev;
3390         struct net_device *net_dev = bcm->net_dev;
3391         int err;
3392         int i;
3393         unsigned long mmio_start, mmio_flags, mmio_len;
3394         u32 coremask;
3395
3396         err = pci_enable_device(pci_dev);
3397         if (err) {
3398                 printk(KERN_ERR PFX "unable to wake up pci device (%i)\n", err);
3399                 goto out;
3400         }
3401         mmio_start = pci_resource_start(pci_dev, 0);
3402         mmio_flags = pci_resource_flags(pci_dev, 0);
3403         mmio_len = pci_resource_len(pci_dev, 0);
3404         if (!(mmio_flags & IORESOURCE_MEM)) {
3405                 printk(KERN_ERR PFX
3406                        "%s, region #0 not an MMIO resource, aborting\n",
3407                        pci_name(pci_dev));
3408                 err = -ENODEV;
3409                 goto err_pci_disable;
3410         }
3411         err = pci_request_regions(pci_dev, KBUILD_MODNAME);
3412         if (err) {
3413                 printk(KERN_ERR PFX
3414                        "could not access PCI resources (%i)\n", err);
3415                 goto err_pci_disable;
3416         }
3417         /* enable PCI bus-mastering */
3418         pci_set_master(pci_dev);
3419         bcm->mmio_addr = ioremap(mmio_start, mmio_len);
3420         if (!bcm->mmio_addr) {
3421                 printk(KERN_ERR PFX "%s: cannot remap MMIO, aborting\n",
3422                        pci_name(pci_dev));
3423                 err = -EIO;
3424                 goto err_pci_release;
3425         }
3426         bcm->mmio_len = mmio_len;
3427         net_dev->base_addr = (unsigned long)bcm->mmio_addr;
3428
3429         bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_VENDOR_ID,
3430                                   &bcm->board_vendor);
3431         bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_ID,
3432                                   &bcm->board_type);
3433         bcm43xx_pci_read_config16(bcm, PCI_REVISION_ID,
3434                                   &bcm->board_revision);
3435
3436         err = bcm43xx_chipset_attach(bcm);
3437         if (err)
3438                 goto err_iounmap;
3439         err = bcm43xx_pctl_init(bcm);
3440         if (err)
3441                 goto err_chipset_detach;
3442         err = bcm43xx_probe_cores(bcm);
3443         if (err)
3444                 goto err_chipset_detach;
3445
3446         /* Attach all IO cores to the backplane. */
3447         coremask = 0;
3448         for (i = 0; i < bcm->nr_80211_available; i++)
3449                 coremask |= (1 << bcm->core_80211[i].index);
3450         //FIXME: Also attach some non80211 cores?
3451         err = bcm43xx_setup_backplane_pci_connection(bcm, coremask);
3452         if (err) {
3453                 printk(KERN_ERR PFX "Backplane->PCI connection failed!\n");
3454                 goto err_chipset_detach;
3455         }
3456
3457         err = bcm43xx_sprom_extract(bcm);
3458         if (err)
3459                 goto err_chipset_detach;
3460         err = bcm43xx_leds_init(bcm);
3461         if (err)
3462                 goto err_chipset_detach;
3463
3464         for (i = 0; i < bcm->nr_80211_available; i++) {
3465                 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3466                 assert(err != -ENODEV);
3467                 if (err)
3468                         goto err_80211_unwind;
3469
3470                 /* Enable the selected wireless core.
3471                  * Connect PHY only on the first core.
3472                  */
3473                 bcm43xx_wireless_core_reset(bcm, (i == 0));
3474
3475                 err = bcm43xx_read_phyinfo(bcm);
3476                 if (err && (i == 0))
3477                         goto err_80211_unwind;
3478
3479                 err = bcm43xx_read_radioinfo(bcm);
3480                 if (err && (i == 0))
3481                         goto err_80211_unwind;
3482
3483                 err = bcm43xx_validate_chip(bcm);
3484                 if (err && (i == 0))
3485                         goto err_80211_unwind;
3486
3487                 bcm43xx_radio_turn_off(bcm);
3488                 err = bcm43xx_phy_init_tssi2dbm_table(bcm);
3489                 if (err)
3490                         goto err_80211_unwind;
3491                 bcm43xx_wireless_core_disable(bcm);
3492         }
3493         err = bcm43xx_geo_init(bcm);
3494         if (err)
3495                 goto err_80211_unwind;
3496         bcm43xx_pctl_set_crystal(bcm, 0);
3497
3498         /* Set the MAC address in the networking subsystem */
3499         if (is_valid_ether_addr(bcm->sprom.et1macaddr))
3500                 memcpy(bcm->net_dev->dev_addr, bcm->sprom.et1macaddr, 6);
3501         else
3502                 memcpy(bcm->net_dev->dev_addr, bcm->sprom.il0macaddr, 6);
3503
3504         snprintf(bcm->nick, IW_ESSID_MAX_SIZE,
3505                  "Broadcom %04X", bcm->chip_id);
3506
3507         assert(err == 0);
3508 out:
3509         return err;
3510
3511 err_80211_unwind:
3512         for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3513                 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3514                 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3515                         kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
3516         }
3517 err_chipset_detach:
3518         bcm43xx_chipset_detach(bcm);
3519 err_iounmap:
3520         iounmap(bcm->mmio_addr);
3521 err_pci_release:
3522         pci_release_regions(pci_dev);
3523 err_pci_disable:
3524         pci_disable_device(pci_dev);
3525         goto out;
3526 }
3527
3528 /* Do the Hardware IO operations to send the txb */
3529 static inline int bcm43xx_tx(struct bcm43xx_private *bcm,
3530                              struct ieee80211_txb *txb)
3531 {
3532         int err = -ENODEV;
3533
3534         if (bcm43xx_using_pio(bcm))
3535                 err = bcm43xx_pio_tx(bcm, txb);
3536         else
3537                 err = bcm43xx_dma_tx(bcm, txb);
3538         bcm->net_dev->trans_start = jiffies;
3539
3540         return err;
3541 }
3542
3543 static void bcm43xx_ieee80211_set_chan(struct net_device *net_dev,
3544                                        u8 channel)
3545 {
3546         struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3547         struct bcm43xx_radioinfo *radio;
3548         unsigned long flags;
3549
3550         bcm43xx_lock_mmio(bcm, flags);
3551         if (bcm->initialized) {
3552                 bcm43xx_mac_suspend(bcm);
3553                 bcm43xx_radio_selectchannel(bcm, channel, 0);
3554                 bcm43xx_mac_enable(bcm);
3555         } else {
3556                 radio = bcm43xx_current_radio(bcm);
3557                 radio->initial_channel = channel;
3558         }
3559         bcm43xx_unlock_mmio(bcm, flags);
3560 }
3561
3562 /* set_security() callback in struct ieee80211_device */
3563 static void bcm43xx_ieee80211_set_security(struct net_device *net_dev,
3564                                            struct ieee80211_security *sec)
3565 {
3566         struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3567         struct ieee80211_security *secinfo = &bcm->ieee->sec;
3568         unsigned long flags;
3569         int keyidx;
3570
3571         dprintk(KERN_INFO PFX "set security called\n");
3572
3573         bcm43xx_lock_mmio(bcm, flags);
3574
3575         for (keyidx = 0; keyidx<WEP_KEYS; keyidx++)
3576                 if (sec->flags & (1<<keyidx)) {
3577                         secinfo->encode_alg[keyidx] = sec->encode_alg[keyidx];
3578                         secinfo->key_sizes[keyidx] = sec->key_sizes[keyidx];
3579                         memcpy(secinfo->keys[keyidx], sec->keys[keyidx], SCM_KEY_LEN);
3580                 }
3581
3582         if (sec->flags & SEC_ACTIVE_KEY) {
3583                 secinfo->active_key = sec->active_key;
3584                 dprintk(KERN_INFO PFX "   .active_key = %d\n", sec->active_key);
3585         }
3586         if (sec->flags & SEC_UNICAST_GROUP) {
3587                 secinfo->unicast_uses_group = sec->unicast_uses_group;
3588                 dprintk(KERN_INFO PFX "   .unicast_uses_group = %d\n", sec->unicast_uses_group);
3589         }
3590         if (sec->flags & SEC_LEVEL) {
3591                 secinfo->level = sec->level;
3592                 dprintk(KERN_INFO PFX "   .level = %d\n", sec->level);
3593         }
3594         if (sec->flags & SEC_ENABLED) {
3595                 secinfo->enabled = sec->enabled;
3596                 dprintk(KERN_INFO PFX "   .enabled = %d\n", sec->enabled);
3597         }
3598         if (sec->flags & SEC_ENCRYPT) {
3599                 secinfo->encrypt = sec->encrypt;
3600                 dprintk(KERN_INFO PFX "   .encrypt = %d\n", sec->encrypt);
3601         }
3602         if (bcm->initialized && !bcm->ieee->host_encrypt) {
3603                 if (secinfo->enabled) {
3604                         /* upload WEP keys to hardware */
3605                         char null_address[6] = { 0 };
3606                         u8 algorithm = 0;
3607                         for (keyidx = 0; keyidx<WEP_KEYS; keyidx++) {
3608                                 if (!(sec->flags & (1<<keyidx)))
3609                                         continue;
3610                                 switch (sec->encode_alg[keyidx]) {
3611                                         case SEC_ALG_NONE: algorithm = BCM43xx_SEC_ALGO_NONE; break;
3612                                         case SEC_ALG_WEP:
3613                                                 algorithm = BCM43xx_SEC_ALGO_WEP;
3614                                                 if (secinfo->key_sizes[keyidx] == 13)
3615                                                         algorithm = BCM43xx_SEC_ALGO_WEP104;
3616                                                 break;
3617                                         case SEC_ALG_TKIP:
3618                                                 FIXME();
3619                                                 algorithm = BCM43xx_SEC_ALGO_TKIP;
3620                                                 break;
3621                                         case SEC_ALG_CCMP:
3622                                                 FIXME();
3623                                                 algorithm = BCM43xx_SEC_ALGO_AES;
3624                                                 break;
3625                                         default:
3626                                                 assert(0);
3627                                                 break;
3628                                 }
3629                                 bcm43xx_key_write(bcm, keyidx, algorithm, sec->keys[keyidx], secinfo->key_sizes[keyidx], &null_address[0]);
3630                                 bcm->key[keyidx].enabled = 1;
3631                                 bcm->key[keyidx].algorithm = algorithm;
3632                         }
3633                 } else
3634                                 bcm43xx_clear_keys(bcm);
3635         }
3636         bcm43xx_unlock_mmio(bcm, flags);
3637 }
3638
3639 /* hard_start_xmit() callback in struct ieee80211_device */
3640 static int bcm43xx_ieee80211_hard_start_xmit(struct ieee80211_txb *txb,
3641                                              struct net_device *net_dev,
3642                                              int pri)
3643 {
3644         struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3645         int err = -ENODEV;
3646         unsigned long flags;
3647
3648         bcm43xx_lock_mmio(bcm, flags);
3649         if (likely(bcm->initialized))
3650                 err = bcm43xx_tx(bcm, txb);
3651         bcm43xx_unlock_mmio(bcm, flags);
3652
3653         return err;
3654 }
3655
3656 static struct net_device_stats * bcm43xx_net_get_stats(struct net_device *net_dev)
3657 {
3658         return &(bcm43xx_priv(net_dev)->ieee->stats);
3659 }
3660
3661 static void bcm43xx_net_tx_timeout(struct net_device *net_dev)
3662 {
3663         struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3664         unsigned long flags;
3665
3666         bcm43xx_lock_mmio(bcm, flags);
3667         bcm43xx_controller_restart(bcm, "TX timeout");
3668         bcm43xx_unlock_mmio(bcm, flags);
3669 }
3670
3671 #ifdef CONFIG_NET_POLL_CONTROLLER
3672 static void bcm43xx_net_poll_controller(struct net_device *net_dev)
3673 {
3674         struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3675         unsigned long flags;
3676
3677         local_irq_save(flags);
3678         bcm43xx_interrupt_handler(bcm->irq, bcm, NULL);
3679         local_irq_restore(flags);
3680 }
3681 #endif /* CONFIG_NET_POLL_CONTROLLER */
3682
3683 static int bcm43xx_net_open(struct net_device *net_dev)
3684 {
3685         struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3686
3687         return bcm43xx_init_board(bcm);
3688 }
3689
3690 static int bcm43xx_net_stop(struct net_device *net_dev)
3691 {
3692         struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3693
3694         ieee80211softmac_stop(net_dev);
3695         bcm43xx_disable_interrupts_sync(bcm, NULL);
3696         bcm43xx_free_board(bcm);
3697
3698         return 0;
3699 }
3700
3701 static int bcm43xx_init_private(struct bcm43xx_private *bcm,
3702                                 struct net_device *net_dev,
3703                                 struct pci_dev *pci_dev)
3704 {
3705         int err;
3706
3707         bcm->ieee = netdev_priv(net_dev);
3708         bcm->softmac = ieee80211_priv(net_dev);
3709         bcm->softmac->set_channel = bcm43xx_ieee80211_set_chan;
3710
3711         bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
3712         bcm->pci_dev = pci_dev;
3713         bcm->net_dev = net_dev;
3714         bcm->bad_frames_preempt = modparam_bad_frames_preempt;
3715         spin_lock_init(&bcm->_lock);
3716         tasklet_init(&bcm->isr_tasklet,
3717                      (void (*)(unsigned long))bcm43xx_interrupt_tasklet,
3718                      (unsigned long)bcm);
3719         tasklet_disable_nosync(&bcm->isr_tasklet);
3720         if (modparam_pio) {
3721                 bcm->__using_pio = 1;
3722         } else {
3723                 err = pci_set_dma_mask(pci_dev, DMA_30BIT_MASK);
3724                 err |= pci_set_consistent_dma_mask(pci_dev, DMA_30BIT_MASK);
3725                 if (err) {
3726 #ifdef CONFIG_BCM43XX_PIO
3727                         printk(KERN_WARNING PFX "DMA not supported. Falling back to PIO.\n");
3728                         bcm->__using_pio = 1;
3729 #else
3730                         printk(KERN_ERR PFX "FATAL: DMA not supported and PIO not configured. "
3731                                             "Recompile the driver with PIO support, please.\n");
3732                         return -ENODEV;
3733 #endif /* CONFIG_BCM43XX_PIO */
3734                 }
3735         }
3736         bcm->rts_threshold = BCM43xx_DEFAULT_RTS_THRESHOLD;
3737
3738         /* default to sw encryption for now */
3739         bcm->ieee->host_build_iv = 0;
3740         bcm->ieee->host_encrypt = 1;
3741         bcm->ieee->host_decrypt = 1;
3742
3743         bcm->ieee->iw_mode = BCM43xx_INITIAL_IWMODE;
3744         bcm->ieee->tx_headroom = sizeof(struct bcm43xx_txhdr);
3745         bcm->ieee->set_security = bcm43xx_ieee80211_set_security;
3746         bcm->ieee->hard_start_xmit = bcm43xx_ieee80211_hard_start_xmit;
3747
3748         return 0;
3749 }
3750
3751 static int __devinit bcm43xx_init_one(struct pci_dev *pdev,
3752                                       const struct pci_device_id *ent)
3753 {
3754         struct net_device *net_dev;
3755         struct bcm43xx_private *bcm;
3756         int err;
3757
3758 #ifdef CONFIG_BCM947XX
3759         if ((pdev->bus->number == 0) && (pdev->device != 0x0800))
3760                 return -ENODEV;
3761 #endif
3762
3763 #ifdef DEBUG_SINGLE_DEVICE_ONLY
3764         if (strcmp(pci_name(pdev), DEBUG_SINGLE_DEVICE_ONLY))
3765                 return -ENODEV;
3766 #endif
3767
3768         net_dev = alloc_ieee80211softmac(sizeof(*bcm));
3769         if (!net_dev) {
3770                 printk(KERN_ERR PFX
3771                        "could not allocate ieee80211 device %s\n",
3772                        pci_name(pdev));
3773                 err = -ENOMEM;
3774                 goto out;
3775         }
3776         /* initialize the net_device struct */
3777         SET_MODULE_OWNER(net_dev);
3778         SET_NETDEV_DEV(net_dev, &pdev->dev);
3779
3780         net_dev->open = bcm43xx_net_open;
3781         net_dev->stop = bcm43xx_net_stop;
3782         net_dev->get_stats = bcm43xx_net_get_stats;
3783         net_dev->tx_timeout = bcm43xx_net_tx_timeout;
3784 #ifdef CONFIG_NET_POLL_CONTROLLER
3785         net_dev->poll_controller = bcm43xx_net_poll_controller;
3786 #endif
3787         net_dev->wireless_handlers = &bcm43xx_wx_handlers_def;
3788         net_dev->irq = pdev->irq;
3789         SET_ETHTOOL_OPS(net_dev, &bcm43xx_ethtool_ops);
3790
3791         /* initialize the bcm43xx_private struct */
3792         bcm = bcm43xx_priv(net_dev);
3793         memset(bcm, 0, sizeof(*bcm));
3794         err = bcm43xx_init_private(bcm, net_dev, pdev);
3795         if (err)
3796                 goto err_free_netdev;
3797
3798         pci_set_drvdata(pdev, net_dev);
3799
3800         err = bcm43xx_attach_board(bcm);
3801         if (err)
3802                 goto err_free_netdev;
3803
3804         err = register_netdev(net_dev);
3805         if (err) {
3806                 printk(KERN_ERR PFX "Cannot register net device, "
3807                        "aborting.\n");
3808                 err = -ENOMEM;
3809                 goto err_detach_board;
3810         }
3811
3812         bcm43xx_debugfs_add_device(bcm);
3813
3814         assert(err == 0);
3815 out:
3816         return err;
3817
3818 err_detach_board:
3819         bcm43xx_detach_board(bcm);
3820 err_free_netdev:
3821         free_ieee80211softmac(net_dev);
3822         goto out;
3823 }
3824
3825 static void __devexit bcm43xx_remove_one(struct pci_dev *pdev)
3826 {
3827         struct net_device *net_dev = pci_get_drvdata(pdev);
3828         struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3829
3830         bcm43xx_debugfs_remove_device(bcm);
3831         unregister_netdev(net_dev);
3832         bcm43xx_detach_board(bcm);
3833         assert(bcm->ucode == NULL);
3834         free_ieee80211softmac(net_dev);
3835 }
3836
3837 /* Hard-reset the chip. Do not call this directly.
3838  * Use bcm43xx_controller_restart()
3839  */
3840 static void bcm43xx_chip_reset(void *_bcm)
3841 {
3842         struct bcm43xx_private *bcm = _bcm;
3843         struct net_device *net_dev = bcm->net_dev;
3844         struct pci_dev *pci_dev = bcm->pci_dev;
3845         int err;
3846         int was_initialized = bcm->initialized;
3847
3848         netif_stop_queue(bcm->net_dev);
3849         tasklet_disable(&bcm->isr_tasklet);
3850
3851         bcm->firmware_norelease = 1;
3852         if (was_initialized)
3853                 bcm43xx_free_board(bcm);
3854         bcm->firmware_norelease = 0;
3855         bcm43xx_detach_board(bcm);
3856         err = bcm43xx_init_private(bcm, net_dev, pci_dev);
3857         if (err)
3858                 goto failure;
3859         err = bcm43xx_attach_board(bcm);
3860         if (err)
3861                 goto failure;
3862         if (was_initialized) {
3863                 err = bcm43xx_init_board(bcm);
3864                 if (err)
3865                         goto failure;
3866         }
3867         netif_wake_queue(bcm->net_dev);
3868         printk(KERN_INFO PFX "Controller restarted\n");
3869
3870         return;
3871 failure:
3872         printk(KERN_ERR PFX "Controller restart failed\n");
3873 }
3874
3875 /* Hard-reset the chip.
3876  * This can be called from interrupt or process context.
3877  * Make sure to _not_ re-enable device interrupts after this has been called.
3878 */
3879 void bcm43xx_controller_restart(struct bcm43xx_private *bcm, const char *reason)
3880 {
3881         bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3882         bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
3883         printk(KERN_ERR PFX "Controller RESET (%s) ...\n", reason);
3884         INIT_WORK(&bcm->restart_work, bcm43xx_chip_reset, bcm);
3885         schedule_work(&bcm->restart_work);
3886 }
3887
3888 #ifdef CONFIG_PM
3889
3890 static int bcm43xx_suspend(struct pci_dev *pdev, pm_message_t state)
3891 {
3892         struct net_device *net_dev = pci_get_drvdata(pdev);
3893         struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3894         unsigned long flags;
3895         int try_to_shutdown = 0, err;
3896
3897         dprintk(KERN_INFO PFX "Suspending...\n");
3898
3899         bcm43xx_lock(bcm, flags);
3900         bcm->was_initialized = bcm->initialized;
3901         if (bcm->initialized)
3902                 try_to_shutdown = 1;
3903         bcm43xx_unlock(bcm, flags);
3904
3905         netif_device_detach(net_dev);
3906         if (try_to_shutdown) {
3907                 ieee80211softmac_stop(net_dev);
3908                 err = bcm43xx_disable_interrupts_sync(bcm, &bcm->irq_savedstate);
3909                 if (unlikely(err)) {
3910                         dprintk(KERN_ERR PFX "Suspend failed.\n");
3911                         return -EAGAIN;
3912                 }
3913                 bcm->firmware_norelease = 1;
3914                 bcm43xx_free_board(bcm);
3915                 bcm->firmware_norelease = 0;
3916         }
3917         bcm43xx_chipset_detach(bcm);
3918
3919         pci_save_state(pdev);
3920         pci_disable_device(pdev);
3921         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3922
3923         dprintk(KERN_INFO PFX "Device suspended.\n");
3924
3925         return 0;
3926 }
3927
3928 static int bcm43xx_resume(struct pci_dev *pdev)
3929 {
3930         struct net_device *net_dev = pci_get_drvdata(pdev);
3931         struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3932         int err = 0;
3933
3934         dprintk(KERN_INFO PFX "Resuming...\n");
3935
3936         pci_set_power_state(pdev, 0);
3937         pci_enable_device(pdev);
3938         pci_restore_state(pdev);
3939
3940         bcm43xx_chipset_attach(bcm);
3941         if (bcm->was_initialized) {
3942                 bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
3943                 err = bcm43xx_init_board(bcm);
3944         }
3945         if (err) {
3946                 printk(KERN_ERR PFX "Resume failed!\n");
3947                 return err;
3948         }
3949
3950         netif_device_attach(net_dev);
3951
3952         dprintk(KERN_INFO PFX "Device resumed.\n");
3953
3954         return 0;
3955 }
3956
3957 #endif                          /* CONFIG_PM */
3958
3959 static struct pci_driver bcm43xx_pci_driver = {
3960         .name = KBUILD_MODNAME,
3961         .id_table = bcm43xx_pci_tbl,
3962         .probe = bcm43xx_init_one,
3963         .remove = __devexit_p(bcm43xx_remove_one),
3964 #ifdef CONFIG_PM
3965         .suspend = bcm43xx_suspend,
3966         .resume = bcm43xx_resume,
3967 #endif                          /* CONFIG_PM */
3968 };
3969
3970 static int __init bcm43xx_init(void)
3971 {
3972         printk(KERN_INFO KBUILD_MODNAME " driver\n");
3973         bcm43xx_debugfs_init();
3974         return pci_register_driver(&bcm43xx_pci_driver);
3975 }
3976
3977 static void __exit bcm43xx_exit(void)
3978 {
3979         pci_unregister_driver(&bcm43xx_pci_driver);
3980         bcm43xx_debugfs_exit();
3981 }
3982
3983 module_init(bcm43xx_init)
3984 module_exit(bcm43xx_exit)