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   1 /*
   2  * File:         arch/blackfin/mach-common/pm.c
   3  * Based on:     arm/mach-omap/pm.c
   4  * Author:       Cliff Brake <cbrake@accelent.com> Copyright (c) 2001
   5  *
   6  * Created:      2001
   7  * Description:  Blackfin power management
   8  *
   9  * Modified:     Nicolas Pitre - PXA250 support
  10  *                Copyright (c) 2002 Monta Vista Software, Inc.
  11  *               David Singleton - OMAP1510
  12  *                Copyright (c) 2002 Monta Vista Software, Inc.
  13  *               Dirk Behme <dirk.behme@de.bosch.com> - OMAP1510/1610
  14  *                Copyright 2004
  15  *               Copyright 2004-2008 Analog Devices Inc.
  16  *
  17  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License as published by
  21  * the Free Software Foundation; either version 2 of the License, or
  22  * (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, see the file COPYING, or write
  31  * to the Free Software Foundation, Inc.,
  32  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  33  */
  34
  35 #include <linux/suspend.h>
  36 #include <linux/sched.h>
  37 #include <linux/proc_fs.h>
  38 #include <linux/io.h>
  39 #include <linux/irq.h>
  40
  41 #include <asm/gpio.h>
  42 #include <asm/dma.h>
  43 #include <asm/dpmc.h>
  44
  45 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_H
  46 #define WAKEUP_TYPE     PM_WAKE_HIGH
  47 #endif
  48
  49 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_L
  50 #define WAKEUP_TYPE     PM_WAKE_LOW
  51 #endif
  52
  53 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_F
  54 #define WAKEUP_TYPE     PM_WAKE_FALLING
  55 #endif
  56
  57 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_R
  58 #define WAKEUP_TYPE     PM_WAKE_RISING
  59 #endif
  60
  61 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_B
  62 #define WAKEUP_TYPE     PM_WAKE_BOTH_EDGES
  63 #endif
  64
  65
  66 void bfin_pm_suspend_standby_enter(void)
  67 {
  68         unsigned long flags;
  69
  70 #ifdef CONFIG_PM_WAKEUP_BY_GPIO
  71         gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE);
  72 #endif
  73
  74         local_irq_save_hw(flags);
  75         bfin_pm_standby_setup();
  76
  77 #ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
  78         sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
  79 #else
  80         sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
  81 #endif
  82
  83         bfin_pm_standby_restore();
  84
  85 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)  || defined(CONFIG_BF561) || \
  86         defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
  87         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
  88 #if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
  89         /* BF52x system reset does not properly reset SIC_IWR1 which
  90          * will screw up the bootrom as it relies on MDMA0/1 waking it
  91          * up from IDLE instructions.  See this report for more info:
  92          * http://blackfin.uclinux.org/gf/tracker/4323
  93          */
  94         if (ANOMALY_05000435)
  95                 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
  96         else
  97                 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
  98 #else
  99         bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
 100 #endif
 101 # ifdef CONFIG_BF54x
 102         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
 103 # endif
 104 #else
 105         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
 106 #endif
 107
 108         local_irq_restore_hw(flags);
 109 }
 110
 111 int bf53x_suspend_l1_mem(unsigned char *memptr)
 112 {
 113         dma_memcpy(memptr, (const void *) L1_CODE_START, L1_CODE_LENGTH);
 114         dma_memcpy(memptr + L1_CODE_LENGTH, (const void *) L1_DATA_A_START,
 115                         L1_DATA_A_LENGTH);
 116         dma_memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
 117                         (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH);
 118         memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH +
 119                         L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START,
 120                         L1_SCRATCH_LENGTH);
 121
 122         return 0;
 123 }
 124
 125 int bf53x_resume_l1_mem(unsigned char *memptr)
 126 {
 127         dma_memcpy((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
 128         dma_memcpy((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
 129                         L1_DATA_A_LENGTH);
 130         dma_memcpy((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
 131                         L1_DATA_A_LENGTH, L1_DATA_B_LENGTH);
 132         memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH +
 133                         L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH);
 134
 135         return 0;
 136 }
 137
 138 #ifdef CONFIG_BFIN_WB
 139 static void flushinv_all_dcache(void)
 140 {
 141         u32 way, bank, subbank, set;
 142         u32 status, addr;
 143         u32 dmem_ctl = bfin_read_DMEM_CONTROL();
 144
 145         for (bank = 0; bank < 2; ++bank) {
 146                 if (!(dmem_ctl & (1 << (DMC1_P - bank))))
 147                         continue;
 148
 149                 for (way = 0; way < 2; ++way)
 150                         for (subbank = 0; subbank < 4; ++subbank)
 151                                 for (set = 0; set < 64; ++set) {
 152
 153                                         bfin_write_DTEST_COMMAND(
 154                                                 way << 26 |
 155                                                 bank << 23 |
 156                                                 subbank << 16 |
 157                                                 set << 5
 158                                         );
 159                                         CSYNC();
 160                                         status = bfin_read_DTEST_DATA0();
 161
 162                                         /* only worry about valid/dirty entries */
 163                                         if ((status & 0x3) != 0x3)
 164                                                 continue;
 165
 166                                         /* construct the address using the tag */
 167                                         addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
 168
 169                                         /* flush it */
 170                                         __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
 171                                 }
 172         }
 173 }
 174 #endif
 175
 176 static inline void dcache_disable(void)
 177 {
 178 #ifdef CONFIG_BFIN_DCACHE
 179         unsigned long ctrl;
 180
 181 #ifdef CONFIG_BFIN_WB
 182         flushinv_all_dcache();
 183 #endif
 184         SSYNC();
 185         ctrl = bfin_read_DMEM_CONTROL();
 186         ctrl &= ~ENDCPLB;
 187         bfin_write_DMEM_CONTROL(ctrl);
 188         SSYNC();
 189 #endif
 190 }
 191
 192 static inline void dcache_enable(void)
 193 {
 194 #ifdef CONFIG_BFIN_DCACHE
 195         unsigned long ctrl;
 196         SSYNC();
 197         ctrl = bfin_read_DMEM_CONTROL();
 198         ctrl |= ENDCPLB;
 199         bfin_write_DMEM_CONTROL(ctrl);
 200         SSYNC();
 201 #endif
 202 }
 203
 204 static inline void icache_disable(void)
 205 {
 206 #ifdef CONFIG_BFIN_ICACHE
 207         unsigned long ctrl;
 208         SSYNC();
 209         ctrl = bfin_read_IMEM_CONTROL();
 210         ctrl &= ~ENICPLB;
 211         bfin_write_IMEM_CONTROL(ctrl);
 212         SSYNC();
 213 #endif
 214 }
 215
 216 static inline void icache_enable(void)
 217 {
 218 #ifdef CONFIG_BFIN_ICACHE
 219         unsigned long ctrl;
 220         SSYNC();
 221         ctrl = bfin_read_IMEM_CONTROL();
 222         ctrl |= ENICPLB;
 223         bfin_write_IMEM_CONTROL(ctrl);
 224         SSYNC();
 225 #endif
 226 }
 227
 228 int bfin_pm_suspend_mem_enter(void)
 229 {
 230         unsigned long flags;
 231         int wakeup, ret;
 232
 233         unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
 234                                          + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH,
 235                                           GFP_KERNEL);
 236
 237         if (memptr == NULL) {
 238                 panic("bf53x_suspend_l1_mem malloc failed");
 239                 return -ENOMEM;
 240         }
 241
 242         wakeup = bfin_read_VR_CTL() & ~FREQ;
 243         wakeup |= SCKELOW;
 244
 245 #ifdef CONFIG_PM_BFIN_WAKE_PH6
 246         wakeup |= PHYWE;
 247 #endif
 248 #ifdef CONFIG_PM_BFIN_WAKE_GP
 249         wakeup |= GPWE;
 250 #endif
 251
 252         local_irq_save_hw(flags);
 253
 254         ret = blackfin_dma_suspend();
 255
 256         if (ret) {
 257                 local_irq_restore_hw(flags);
 258                 kfree(memptr);
 259                 return ret;
 260         }
 261
 262         bfin_gpio_pm_hibernate_suspend();
 263
 264         dcache_disable();
 265         icache_disable();
 266         bf53x_suspend_l1_mem(memptr);
 267
 268         do_hibernate(wakeup | vr_wakeup);       /* Goodbye */
 269
 270         bf53x_resume_l1_mem(memptr);
 271
 272         icache_enable();
 273         dcache_enable();
 274
 275         bfin_gpio_pm_hibernate_restore();
 276         blackfin_dma_resume();
 277
 278         local_irq_restore_hw(flags);
 279         kfree(memptr);
 280
 281         return 0;
 282 }
 283
 284 /*
 285  *      bfin_pm_valid - Tell the PM core that we only support the standby sleep
 286  *                      state
 287  *      @state:         suspend state we're checking.
 288  *
 289  */
 290 static int bfin_pm_valid(suspend_state_t state)
 291 {
 292         return (state == PM_SUSPEND_STANDBY
 293 #ifndef BF533_FAMILY
 294         /*
 295          * On BF533/2/1:
 296          * If we enter Hibernate the SCKE Pin is driven Low,
 297          * so that the SDRAM enters Self Refresh Mode.
 298          * However when the reset sequence that follows hibernate
 299          * state is executed, SCKE is driven High, taking the
 300          * SDRAM out of Self Refresh.
 301          *
 302          * If you reconfigure and access the SDRAM "very quickly",
 303          * you are likely to avoid errors, otherwise the SDRAM
 304          * start losing its contents.
 305          * An external HW workaround is possible using logic gates.
 306          */
 307         || state == PM_SUSPEND_MEM
 308 #endif
 309         );
 310 }
 311
 312 /*
 313  *      bfin_pm_enter - Actually enter a sleep state.
 314  *      @state:         State we're entering.
 315  *
 316  */
 317 static int bfin_pm_enter(suspend_state_t state)
 318 {
 319         switch (state) {
 320         case PM_SUSPEND_STANDBY:
 321                 bfin_pm_suspend_standby_enter();
 322                 break;
 323         case PM_SUSPEND_MEM:
 324                 bfin_pm_suspend_mem_enter();
 325                 break;
 326         default:
 327                 return -EINVAL;
 328         }
 329
 330         return 0;
 331 }
 332
 333 struct platform_suspend_ops bfin_pm_ops = {
 334         .enter = bfin_pm_enter,
 335         .valid  = bfin_pm_valid,
 336 };
 337
 338 static int __init bfin_pm_init(void)
 339 {
 340         suspend_set_ops(&bfin_pm_ops);
 341         return 0;
 342 }
 343
 344 __initcall(bfin_pm_init);