git.oblomov.eu Git - linux-2.6/blob - drivers/i2c/busses/i2c-s3c2410.c

   1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
   2  *
   3  * Copyright (C) 2004,2005 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 I2C Controller
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21 */
  22
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25
  26 #include <linux/i2c.h>
  27 #include <linux/i2c-id.h>
  28 #include <linux/init.h>
  29 #include <linux/time.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/delay.h>
  32 #include <linux/errno.h>
  33 #include <linux/err.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/clk.h>
  36 #include <linux/cpufreq.h>
  37
  38 #include <asm/irq.h>
  39 #include <asm/io.h>
  40
  41 #include <asm/plat-s3c/regs-iic.h>
  42 #include <asm/plat-s3c/iic.h>
  43
  44 /* i2c controller state */
  45
  46 enum s3c24xx_i2c_state {
  47         STATE_IDLE,
  48         STATE_START,
  49         STATE_READ,
  50         STATE_WRITE,
  51         STATE_STOP
  52 };
  53
  54 struct s3c24xx_i2c {
  55         spinlock_t              lock;
  56         wait_queue_head_t       wait;
  57
  58         struct i2c_msg          *msg;
  59         unsigned int            msg_num;
  60         unsigned int            msg_idx;
  61         unsigned int            msg_ptr;
  62
  63         unsigned int            tx_setup;
  64
  65         enum s3c24xx_i2c_state  state;
  66         unsigned long           clkrate;
  67
  68         void __iomem            *regs;
  69         struct clk              *clk;
  70         struct device           *dev;
  71         struct resource         *irq;
  72         struct resource         *ioarea;
  73         struct i2c_adapter      adap;
  74
  75 #ifdef CONFIG_CPU_FREQ
  76         struct notifier_block   freq_transition;
  77 #endif
  78 };
  79
  80 /* default platform data removed, dev should always carry data. */
  81
  82 /* s3c24xx_i2c_is2440()
  83  *
  84  * return true is this is an s3c2440
  85 */
  86
  87 static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
  88 {
  89         struct platform_device *pdev = to_platform_device(i2c->dev);
  90
  91         return !strcmp(pdev->name, "s3c2440-i2c");
  92 }
  93
  94 /* s3c24xx_i2c_master_complete
  95  *
  96  * complete the message and wake up the caller, using the given return code,
  97  * or zero to mean ok.
  98 */
  99
 100 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
 101 {
 102         dev_dbg(i2c->dev, "master_complete %d\n", ret);
 103
 104         i2c->msg_ptr = 0;
 105         i2c->msg = NULL;
 106         i2c->msg_idx++;
 107         i2c->msg_num = 0;
 108         if (ret)
 109                 i2c->msg_idx = ret;
 110
 111         wake_up(&i2c->wait);
 112 }
 113
 114 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
 115 {
 116         unsigned long tmp;
 117
 118         tmp = readl(i2c->regs + S3C2410_IICCON);
 119         writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 120 }
 121
 122 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
 123 {
 124         unsigned long tmp;
 125
 126         tmp = readl(i2c->regs + S3C2410_IICCON);
 127         writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 128 }
 129
 130 /* irq enable/disable functions */
 131
 132 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
 133 {
 134         unsigned long tmp;
 135
 136         tmp = readl(i2c->regs + S3C2410_IICCON);
 137         writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 138 }
 139
 140 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
 141 {
 142         unsigned long tmp;
 143
 144         tmp = readl(i2c->regs + S3C2410_IICCON);
 145         writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 146 }
 147
 148
 149 /* s3c24xx_i2c_message_start
 150  *
 151  * put the start of a message onto the bus
 152 */
 153
 154 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
 155                                       struct i2c_msg *msg)
 156 {
 157         unsigned int addr = (msg->addr & 0x7f) << 1;
 158         unsigned long stat;
 159         unsigned long iiccon;
 160
 161         stat = 0;
 162         stat |=  S3C2410_IICSTAT_TXRXEN;
 163
 164         if (msg->flags & I2C_M_RD) {
 165                 stat |= S3C2410_IICSTAT_MASTER_RX;
 166                 addr |= 1;
 167         } else
 168                 stat |= S3C2410_IICSTAT_MASTER_TX;
 169
 170         if (msg->flags & I2C_M_REV_DIR_ADDR)
 171                 addr ^= 1;
 172
 173         /* todo - check for wether ack wanted or not */
 174         s3c24xx_i2c_enable_ack(i2c);
 175
 176         iiccon = readl(i2c->regs + S3C2410_IICCON);
 177         writel(stat, i2c->regs + S3C2410_IICSTAT);
 178
 179         dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
 180         writeb(addr, i2c->regs + S3C2410_IICDS);
 181
 182         /* delay here to ensure the data byte has gotten onto the bus
 183          * before the transaction is started */
 184
 185         ndelay(i2c->tx_setup);
 186
 187         dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
 188         writel(iiccon, i2c->regs + S3C2410_IICCON);
 189
 190         stat |= S3C2410_IICSTAT_START;
 191         writel(stat, i2c->regs + S3C2410_IICSTAT);
 192 }
 193
 194 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
 195 {
 196         unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 197
 198         dev_dbg(i2c->dev, "STOP\n");
 199
 200         /* stop the transfer */
 201         iicstat &= ~S3C2410_IICSTAT_START;
 202         writel(iicstat, i2c->regs + S3C2410_IICSTAT);
 203
 204         i2c->state = STATE_STOP;
 205
 206         s3c24xx_i2c_master_complete(i2c, ret);
 207         s3c24xx_i2c_disable_irq(i2c);
 208 }
 209
 210 /* helper functions to determine the current state in the set of
 211  * messages we are sending */
 212
 213 /* is_lastmsg()
 214  *
 215  * returns TRUE if the current message is the last in the set
 216 */
 217
 218 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
 219 {
 220         return i2c->msg_idx >= (i2c->msg_num - 1);
 221 }
 222
 223 /* is_msglast
 224  *
 225  * returns TRUE if we this is the last byte in the current message
 226 */
 227
 228 static inline int is_msglast(struct s3c24xx_i2c *i2c)
 229 {
 230         return i2c->msg_ptr == i2c->msg->len-1;
 231 }
 232
 233 /* is_msgend
 234  *
 235  * returns TRUE if we reached the end of the current message
 236 */
 237
 238 static inline int is_msgend(struct s3c24xx_i2c *i2c)
 239 {
 240         return i2c->msg_ptr >= i2c->msg->len;
 241 }
 242
 243 /* i2s_s3c_irq_nextbyte
 244  *
 245  * process an interrupt and work out what to do
 246  */
 247
 248 static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
 249 {
 250         unsigned long tmp;
 251         unsigned char byte;
 252         int ret = 0;
 253
 254         switch (i2c->state) {
 255
 256         case STATE_IDLE:
 257                 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
 258                 goto out;
 259                 break;
 260
 261         case STATE_STOP:
 262                 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
 263                 s3c24xx_i2c_disable_irq(i2c);
 264                 goto out_ack;
 265
 266         case STATE_START:
 267                 /* last thing we did was send a start condition on the
 268                  * bus, or started a new i2c message
 269                  */
 270
 271                 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
 272                     !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 273                         /* ack was not received... */
 274
 275                         dev_dbg(i2c->dev, "ack was not received\n");
 276                         s3c24xx_i2c_stop(i2c, -ENXIO);
 277                         goto out_ack;
 278                 }
 279
 280                 if (i2c->msg->flags & I2C_M_RD)
 281                         i2c->state = STATE_READ;
 282                 else
 283                         i2c->state = STATE_WRITE;
 284
 285                 /* terminate the transfer if there is nothing to do
 286                  * as this is used by the i2c probe to find devices. */
 287
 288                 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
 289                         s3c24xx_i2c_stop(i2c, 0);
 290                         goto out_ack;
 291                 }
 292
 293                 if (i2c->state == STATE_READ)
 294                         goto prepare_read;
 295
 296                 /* fall through to the write state, as we will need to
 297                  * send a byte as well */
 298
 299         case STATE_WRITE:
 300                 /* we are writing data to the device... check for the
 301                  * end of the message, and if so, work out what to do
 302                  */
 303
 304                 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 305                         if (iicstat & S3C2410_IICSTAT_LASTBIT) {
 306                                 dev_dbg(i2c->dev, "WRITE: No Ack\n");
 307
 308                                 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
 309                                 goto out_ack;
 310                         }
 311                 }
 312
 313  retry_write:
 314
 315                 if (!is_msgend(i2c)) {
 316                         byte = i2c->msg->buf[i2c->msg_ptr++];
 317                         writeb(byte, i2c->regs + S3C2410_IICDS);
 318
 319                         /* delay after writing the byte to allow the
 320                          * data setup time on the bus, as writing the
 321                          * data to the register causes the first bit
 322                          * to appear on SDA, and SCL will change as
 323                          * soon as the interrupt is acknowledged */
 324
 325                         ndelay(i2c->tx_setup);
 326
 327                 } else if (!is_lastmsg(i2c)) {
 328                         /* we need to go to the next i2c message */
 329
 330                         dev_dbg(i2c->dev, "WRITE: Next Message\n");
 331
 332                         i2c->msg_ptr = 0;
 333                         i2c->msg_idx++;
 334                         i2c->msg++;
 335
 336                         /* check to see if we need to do another message */
 337                         if (i2c->msg->flags & I2C_M_NOSTART) {
 338
 339                                 if (i2c->msg->flags & I2C_M_RD) {
 340                                         /* cannot do this, the controller
 341                                          * forces us to send a new START
 342                                          * when we change direction */
 343
 344                                         s3c24xx_i2c_stop(i2c, -EINVAL);
 345                                 }
 346
 347                                 goto retry_write;
 348                         } else {
 349                                 /* send the new start */
 350                                 s3c24xx_i2c_message_start(i2c, i2c->msg);
 351                                 i2c->state = STATE_START;
 352                         }
 353
 354                 } else {
 355                         /* send stop */
 356
 357                         s3c24xx_i2c_stop(i2c, 0);
 358                 }
 359                 break;
 360
 361         case STATE_READ:
 362                 /* we have a byte of data in the data register, do
 363                  * something with it, and then work out wether we are
 364                  * going to do any more read/write
 365                  */
 366
 367                 byte = readb(i2c->regs + S3C2410_IICDS);
 368                 i2c->msg->buf[i2c->msg_ptr++] = byte;
 369
 370  prepare_read:
 371                 if (is_msglast(i2c)) {
 372                         /* last byte of buffer */
 373
 374                         if (is_lastmsg(i2c))
 375                                 s3c24xx_i2c_disable_ack(i2c);
 376
 377                 } else if (is_msgend(i2c)) {
 378                         /* ok, we've read the entire buffer, see if there
 379                          * is anything else we need to do */
 380
 381                         if (is_lastmsg(i2c)) {
 382                                 /* last message, send stop and complete */
 383                                 dev_dbg(i2c->dev, "READ: Send Stop\n");
 384
 385                                 s3c24xx_i2c_stop(i2c, 0);
 386                         } else {
 387                                 /* go to the next transfer */
 388                                 dev_dbg(i2c->dev, "READ: Next Transfer\n");
 389
 390                                 i2c->msg_ptr = 0;
 391                                 i2c->msg_idx++;
 392                                 i2c->msg++;
 393                         }
 394                 }
 395
 396                 break;
 397         }
 398
 399         /* acknowlegde the IRQ and get back on with the work */
 400
 401  out_ack:
 402         tmp = readl(i2c->regs + S3C2410_IICCON);
 403         tmp &= ~S3C2410_IICCON_IRQPEND;
 404         writel(tmp, i2c->regs + S3C2410_IICCON);
 405  out:
 406         return ret;
 407 }
 408
 409 /* s3c24xx_i2c_irq
 410  *
 411  * top level IRQ servicing routine
 412 */
 413
 414 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
 415 {
 416         struct s3c24xx_i2c *i2c = dev_id;
 417         unsigned long status;
 418         unsigned long tmp;
 419
 420         status = readl(i2c->regs + S3C2410_IICSTAT);
 421
 422         if (status & S3C2410_IICSTAT_ARBITR) {
 423                 /* deal with arbitration loss */
 424                 dev_err(i2c->dev, "deal with arbitration loss\n");
 425         }
 426
 427         if (i2c->state == STATE_IDLE) {
 428                 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
 429
 430                 tmp = readl(i2c->regs + S3C2410_IICCON);
 431                 tmp &= ~S3C2410_IICCON_IRQPEND;
 432                 writel(tmp, i2c->regs +  S3C2410_IICCON);
 433                 goto out;
 434         }
 435
 436         /* pretty much this leaves us with the fact that we've
 437          * transmitted or received whatever byte we last sent */
 438
 439         i2s_s3c_irq_nextbyte(i2c, status);
 440
 441  out:
 442         return IRQ_HANDLED;
 443 }
 444
 445
 446 /* s3c24xx_i2c_set_master
 447  *
 448  * get the i2c bus for a master transaction
 449 */
 450
 451 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
 452 {
 453         unsigned long iicstat;
 454         int timeout = 400;
 455
 456         while (timeout-- > 0) {
 457                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 458
 459                 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
 460                         return 0;
 461
 462                 msleep(1);
 463         }
 464
 465         return -ETIMEDOUT;
 466 }
 467
 468 /* s3c24xx_i2c_doxfer
 469  *
 470  * this starts an i2c transfer
 471 */
 472
 473 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
 474                               struct i2c_msg *msgs, int num)
 475 {
 476         unsigned long timeout;
 477         int ret;
 478
 479         if (!(readl(i2c->regs + S3C2410_IICCON) & S3C2410_IICCON_IRQEN))
 480                 return -EIO;
 481
 482         ret = s3c24xx_i2c_set_master(i2c);
 483         if (ret != 0) {
 484                 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
 485                 ret = -EAGAIN;
 486                 goto out;
 487         }
 488
 489         spin_lock_irq(&i2c->lock);
 490
 491         i2c->msg     = msgs;
 492         i2c->msg_num = num;
 493         i2c->msg_ptr = 0;
 494         i2c->msg_idx = 0;
 495         i2c->state   = STATE_START;
 496
 497         s3c24xx_i2c_enable_irq(i2c);
 498         s3c24xx_i2c_message_start(i2c, msgs);
 499         spin_unlock_irq(&i2c->lock);
 500
 501         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 502
 503         ret = i2c->msg_idx;
 504
 505         /* having these next two as dev_err() makes life very
 506          * noisy when doing an i2cdetect */
 507
 508         if (timeout == 0)
 509                 dev_dbg(i2c->dev, "timeout\n");
 510         else if (ret != num)
 511                 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
 512
 513         /* ensure the stop has been through the bus */
 514
 515         msleep(1);
 516
 517  out:
 518         return ret;
 519 }
 520
 521 /* s3c24xx_i2c_xfer
 522  *
 523  * first port of call from the i2c bus code when an message needs
 524  * transferring across the i2c bus.
 525 */
 526
 527 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
 528                         struct i2c_msg *msgs, int num)
 529 {
 530         struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
 531         int retry;
 532         int ret;
 533
 534         for (retry = 0; retry < adap->retries; retry++) {
 535
 536                 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
 537
 538                 if (ret != -EAGAIN)
 539                         return ret;
 540
 541                 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
 542
 543                 udelay(100);
 544         }
 545
 546         return -EREMOTEIO;
 547 }
 548
 549 /* declare our i2c functionality */
 550 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
 551 {
 552         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 553 }
 554
 555 /* i2c bus registration info */
 556
 557 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
 558         .master_xfer            = s3c24xx_i2c_xfer,
 559         .functionality          = s3c24xx_i2c_func,
 560 };
 561
 562 static struct s3c24xx_i2c s3c24xx_i2c = {
 563         .lock           = __SPIN_LOCK_UNLOCKED(s3c24xx_i2c.lock),
 564         .wait           = __WAIT_QUEUE_HEAD_INITIALIZER(s3c24xx_i2c.wait),
 565         .tx_setup       = 50,
 566         .adap           = {
 567                 .name                   = "s3c2410-i2c",
 568                 .owner                  = THIS_MODULE,
 569                 .algo                   = &s3c24xx_i2c_algorithm,
 570                 .retries                = 2,
 571                 .class                  = I2C_CLASS_HWMON | I2C_CLASS_SPD,
 572         },
 573 };
 574
 575 /* s3c24xx_i2c_calcdivisor
 576  *
 577  * return the divisor settings for a given frequency
 578 */
 579
 580 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
 581                                    unsigned int *div1, unsigned int *divs)
 582 {
 583         unsigned int calc_divs = clkin / wanted;
 584         unsigned int calc_div1;
 585
 586         if (calc_divs > (16*16))
 587                 calc_div1 = 512;
 588         else
 589                 calc_div1 = 16;
 590
 591         calc_divs += calc_div1-1;
 592         calc_divs /= calc_div1;
 593
 594         if (calc_divs == 0)
 595                 calc_divs = 1;
 596         if (calc_divs > 17)
 597                 calc_divs = 17;
 598
 599         *divs = calc_divs;
 600         *div1 = calc_div1;
 601
 602         return clkin / (calc_divs * calc_div1);
 603 }
 604
 605 /* freq_acceptable
 606  *
 607  * test wether a frequency is within the acceptable range of error
 608 */
 609
 610 static inline int freq_acceptable(unsigned int freq, unsigned int wanted)
 611 {
 612         int diff = freq - wanted;
 613
 614         return diff >= -2 && diff <= 2;
 615 }
 616
 617 /* s3c24xx_i2c_clockrate
 618  *
 619  * work out a divisor for the user requested frequency setting,
 620  * either by the requested frequency, or scanning the acceptable
 621  * range of frequencies until something is found
 622 */
 623
 624 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
 625 {
 626         struct s3c2410_platform_i2c *pdata = i2c->dev->platform_data;
 627         unsigned long clkin = clk_get_rate(i2c->clk);
 628         unsigned int divs, div1;
 629         u32 iiccon;
 630         int freq;
 631         int start, end;
 632
 633         i2c->clkrate = clkin;
 634         clkin /= 1000;          /* clkin now in KHz */
 635
 636         dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n",
 637                  pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq);
 638
 639         if (pdata->bus_freq != 0) {
 640                 freq = s3c24xx_i2c_calcdivisor(clkin, pdata->bus_freq/1000,
 641                                                &div1, &divs);
 642                 if (freq_acceptable(freq, pdata->bus_freq/1000))
 643                         goto found;
 644         }
 645
 646         /* ok, we may have to search for something suitable... */
 647
 648         start = (pdata->max_freq == 0) ? pdata->bus_freq : pdata->max_freq;
 649         end = pdata->min_freq;
 650
 651         start /= 1000;
 652         end /= 1000;
 653
 654         /* search loop... */
 655
 656         for (; start > end; start--) {
 657                 freq = s3c24xx_i2c_calcdivisor(clkin, start, &div1, &divs);
 658                 if (freq_acceptable(freq, start))
 659                         goto found;
 660         }
 661
 662         /* cannot find frequency spec */
 663
 664         return -EINVAL;
 665
 666  found:
 667         *got = freq;
 668
 669         iiccon = readl(i2c->regs + S3C2410_IICCON);
 670         iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
 671         iiccon |= (divs-1);
 672
 673         if (div1 == 512)
 674                 iiccon |= S3C2410_IICCON_TXDIV_512;
 675
 676         writel(iiccon, i2c->regs + S3C2410_IICCON);
 677
 678         return 0;
 679 }
 680
 681 #ifdef CONFIG_CPU_FREQ
 682
 683 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
 684
 685 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
 686                                           unsigned long val, void *data)
 687 {
 688         struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
 689         unsigned long flags;
 690         unsigned int got;
 691         int delta_f;
 692         int ret;
 693
 694         delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
 695
 696         /* if we're post-change and the input clock has slowed down
 697          * or at pre-change and the clock is about to speed up, then
 698          * adjust our clock rate. <0 is slow, >0 speedup.
 699          */
 700
 701         if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
 702             (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
 703                 spin_lock_irqsave(&i2c->lock, flags);
 704                 ret = s3c24xx_i2c_clockrate(i2c, &got);
 705                 spin_unlock_irqrestore(&i2c->lock, flags);
 706
 707                 if (ret < 0)
 708                         dev_err(i2c->dev, "cannot find frequency\n");
 709                 else
 710                         dev_info(i2c->dev, "setting freq %d\n", got);
 711         }
 712
 713         return 0;
 714 }
 715
 716 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 717 {
 718         i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
 719
 720         return cpufreq_register_notifier(&i2c->freq_transition,
 721                                          CPUFREQ_TRANSITION_NOTIFIER);
 722 }
 723
 724 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 725 {
 726         cpufreq_unregister_notifier(&i2c->freq_transition,
 727                                     CPUFREQ_TRANSITION_NOTIFIER);
 728 }
 729
 730 #else
 731 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 732 {
 733         return 0;
 734 }
 735
 736 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 737 {
 738 }
 739 #endif
 740
 741 /* s3c24xx_i2c_init
 742  *
 743  * initialise the controller, set the IO lines and frequency
 744 */
 745
 746 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
 747 {
 748         unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
 749         struct s3c2410_platform_i2c *pdata;
 750         unsigned int freq;
 751
 752         /* get the plafrom data */
 753
 754         pdata = i2c->dev->platform_data;
 755
 756         /* inititalise the gpio */
 757
 758         if (pdata->cfg_gpio)
 759                 pdata->cfg_gpio(to_platform_device(i2c->dev));
 760
 761         /* write slave address */
 762
 763         writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
 764
 765         dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
 766
 767         writel(iicon, i2c->regs + S3C2410_IICCON);
 768
 769         /* we need to work out the divisors for the clock... */
 770
 771         if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
 772                 writel(0, i2c->regs + S3C2410_IICCON);
 773                 dev_err(i2c->dev, "cannot meet bus frequency required\n");
 774                 return -EINVAL;
 775         }
 776
 777         /* todo - check that the i2c lines aren't being dragged anywhere */
 778
 779         dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
 780         dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
 781
 782         /* check for s3c2440 i2c controller  */
 783
 784         if (s3c24xx_i2c_is2440(i2c)) {
 785                 dev_dbg(i2c->dev, "S3C2440_IICLC=%08x\n", pdata->sda_delay);
 786
 787                 writel(pdata->sda_delay, i2c->regs + S3C2440_IICLC);
 788         }
 789
 790         return 0;
 791 }
 792
 793 /* s3c24xx_i2c_probe
 794  *
 795  * called by the bus driver when a suitable device is found
 796 */
 797
 798 static int s3c24xx_i2c_probe(struct platform_device *pdev)
 799 {
 800         struct s3c24xx_i2c *i2c = &s3c24xx_i2c;
 801         struct s3c2410_platform_i2c *pdata;
 802         struct resource *res;
 803         int ret;
 804
 805         pdata = pdev->dev.platform_data;
 806         if (!pdata) {
 807                 dev_err(&pdev->dev, "no platform data\n");
 808                 return -EINVAL;
 809         }
 810
 811         /* find the clock and enable it */
 812
 813         i2c->dev = &pdev->dev;
 814         i2c->clk = clk_get(&pdev->dev, "i2c");
 815         if (IS_ERR(i2c->clk)) {
 816                 dev_err(&pdev->dev, "cannot get clock\n");
 817                 ret = -ENOENT;
 818                 goto err_noclk;
 819         }
 820
 821         dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
 822
 823         clk_enable(i2c->clk);
 824
 825         /* map the registers */
 826
 827         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 828         if (res == NULL) {
 829                 dev_err(&pdev->dev, "cannot find IO resource\n");
 830                 ret = -ENOENT;
 831                 goto err_clk;
 832         }
 833
 834         i2c->ioarea = request_mem_region(res->start, (res->end-res->start)+1,
 835                                          pdev->name);
 836
 837         if (i2c->ioarea == NULL) {
 838                 dev_err(&pdev->dev, "cannot request IO\n");
 839                 ret = -ENXIO;
 840                 goto err_clk;
 841         }
 842
 843         i2c->regs = ioremap(res->start, (res->end-res->start)+1);
 844
 845         if (i2c->regs == NULL) {
 846                 dev_err(&pdev->dev, "cannot map IO\n");
 847                 ret = -ENXIO;
 848                 goto err_ioarea;
 849         }
 850
 851         dev_dbg(&pdev->dev, "registers %p (%p, %p)\n",
 852                 i2c->regs, i2c->ioarea, res);
 853
 854         /* setup info block for the i2c core */
 855
 856         i2c->adap.algo_data = i2c;
 857         i2c->adap.dev.parent = &pdev->dev;
 858
 859         /* initialise the i2c controller */
 860
 861         ret = s3c24xx_i2c_init(i2c);
 862         if (ret != 0)
 863                 goto err_iomap;
 864
 865         /* find the IRQ for this unit (note, this relies on the init call to
 866          * ensure no current IRQs pending
 867          */
 868
 869         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 870         if (res == NULL) {
 871                 dev_err(&pdev->dev, "cannot find IRQ\n");
 872                 ret = -ENOENT;
 873                 goto err_iomap;
 874         }
 875
 876         ret = request_irq(res->start, s3c24xx_i2c_irq, IRQF_DISABLED,
 877                           pdev->name, i2c);
 878
 879         if (ret != 0) {
 880                 dev_err(&pdev->dev, "cannot claim IRQ\n");
 881                 goto err_iomap;
 882         }
 883
 884         i2c->irq = res;
 885
 886         dev_dbg(&pdev->dev, "irq resource %p (%lu)\n", res,
 887                 (unsigned long)res->start);
 888
 889         ret = s3c24xx_i2c_register_cpufreq(i2c);
 890         if (ret < 0) {
 891                 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
 892                 goto err_irq;
 893         }
 894
 895         /* Note, previous versions of the driver used i2c_add_adapter()
 896          * to add the bus at any number. We now pass the bus number via
 897          * the platform data, so if unset it will now default to always
 898          * being bus 0.
 899          */
 900
 901         i2c->adap.nr = pdata->bus_num;
 902
 903         ret = i2c_add_numbered_adapter(&i2c->adap);
 904         if (ret < 0) {
 905                 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
 906                 goto err_cpufreq;
 907         }
 908
 909         platform_set_drvdata(pdev, i2c);
 910
 911         dev_info(&pdev->dev, "%s: S3C I2C adapter\n", i2c->adap.dev.bus_id);
 912         return 0;
 913
 914  err_cpufreq:
 915         s3c24xx_i2c_deregister_cpufreq(i2c);
 916
 917  err_irq:
 918         free_irq(i2c->irq->start, i2c);
 919
 920  err_iomap:
 921         iounmap(i2c->regs);
 922
 923  err_ioarea:
 924         release_resource(i2c->ioarea);
 925         kfree(i2c->ioarea);
 926
 927  err_clk:
 928         clk_disable(i2c->clk);
 929         clk_put(i2c->clk);
 930
 931  err_noclk:
 932         return ret;
 933 }
 934
 935 /* s3c24xx_i2c_remove
 936  *
 937  * called when device is removed from the bus
 938 */
 939
 940 static int s3c24xx_i2c_remove(struct platform_device *pdev)
 941 {
 942         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
 943
 944         s3c24xx_i2c_deregister_cpufreq(i2c);
 945
 946         i2c_del_adapter(&i2c->adap);
 947         free_irq(i2c->irq->start, i2c);
 948
 949         clk_disable(i2c->clk);
 950         clk_put(i2c->clk);
 951
 952         iounmap(i2c->regs);
 953
 954         release_resource(i2c->ioarea);
 955         kfree(i2c->ioarea);
 956
 957         return 0;
 958 }
 959
 960 #ifdef CONFIG_PM
 961 static int s3c24xx_i2c_resume(struct platform_device *dev)
 962 {
 963         struct s3c24xx_i2c *i2c = platform_get_drvdata(dev);
 964
 965         if (i2c != NULL)
 966                 s3c24xx_i2c_init(i2c);
 967
 968         return 0;
 969 }
 970
 971 #else
 972 #define s3c24xx_i2c_resume NULL
 973 #endif
 974
 975 /* device driver for platform bus bits */
 976
 977 static struct platform_driver s3c2410_i2c_driver = {
 978         .probe          = s3c24xx_i2c_probe,
 979         .remove         = s3c24xx_i2c_remove,
 980         .resume         = s3c24xx_i2c_resume,
 981         .driver         = {
 982                 .owner  = THIS_MODULE,
 983                 .name   = "s3c2410-i2c",
 984         },
 985 };
 986
 987 static struct platform_driver s3c2440_i2c_driver = {
 988         .probe          = s3c24xx_i2c_probe,
 989         .remove         = s3c24xx_i2c_remove,
 990         .resume         = s3c24xx_i2c_resume,
 991         .driver         = {
 992                 .owner  = THIS_MODULE,
 993                 .name   = "s3c2440-i2c",
 994         },
 995 };
 996
 997 static int __init i2c_adap_s3c_init(void)
 998 {
 999         int ret;
1000
1001         ret = platform_driver_register(&s3c2410_i2c_driver);
1002         if (ret == 0) {
1003                 ret = platform_driver_register(&s3c2440_i2c_driver);
1004                 if (ret)
1005                         platform_driver_unregister(&s3c2410_i2c_driver);
1006         }
1007
1008         return ret;
1009 }
1010
1011 static void __exit i2c_adap_s3c_exit(void)
1012 {
1013         platform_driver_unregister(&s3c2410_i2c_driver);
1014         platform_driver_unregister(&s3c2440_i2c_driver);
1015 }
1016
1017 module_init(i2c_adap_s3c_init);
1018 module_exit(i2c_adap_s3c_exit);
1019
1020 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1021 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1022 MODULE_LICENSE("GPL");
1023 MODULE_ALIAS("platform:s3c2410-i2c");
1024 MODULE_ALIAS("platform:s3c2440-i2c");