1 /* b44.c: Broadcom 44xx/47xx Fast Ethernet device driver.
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
4 * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
5 * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
6 * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
7 * Copyright (C) 2006 Broadcom Corporation.
8 * Copyright (C) 2007 Michael Buesch <mb@bu3sch.de>
10 * Distribute under GPL.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/types.h>
17 #include <linux/netdevice.h>
18 #include <linux/ethtool.h>
19 #include <linux/mii.h>
20 #include <linux/if_ether.h>
21 #include <linux/if_vlan.h>
22 #include <linux/etherdevice.h>
23 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/ssb/ssb.h>
29 #include <asm/uaccess.h>
36 #define DRV_MODULE_NAME "b44"
37 #define PFX DRV_MODULE_NAME ": "
38 #define DRV_MODULE_VERSION "2.0"
40 #define B44_DEF_MSG_ENABLE \
50 /* length of time before we decide the hardware is borked,
51 * and dev->tx_timeout() should be called to fix the problem
53 #define B44_TX_TIMEOUT (5 * HZ)
55 /* hardware minimum and maximum for a single frame's data payload */
56 #define B44_MIN_MTU 60
57 #define B44_MAX_MTU 1500
59 #define B44_RX_RING_SIZE 512
60 #define B44_DEF_RX_RING_PENDING 200
61 #define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
63 #define B44_TX_RING_SIZE 512
64 #define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
65 #define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
68 #define TX_RING_GAP(BP) \
69 (B44_TX_RING_SIZE - (BP)->tx_pending)
70 #define TX_BUFFS_AVAIL(BP) \
71 (((BP)->tx_cons <= (BP)->tx_prod) ? \
72 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
73 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
74 #define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
76 #define RX_PKT_OFFSET (RX_HEADER_LEN + 2)
77 #define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET)
79 /* minimum number of free TX descriptors required to wake up TX process */
80 #define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
82 /* b44 internal pattern match filter info */
83 #define B44_PATTERN_BASE 0x400
84 #define B44_PATTERN_SIZE 0x80
85 #define B44_PMASK_BASE 0x600
86 #define B44_PMASK_SIZE 0x10
87 #define B44_MAX_PATTERNS 16
88 #define B44_ETHIPV6UDP_HLEN 62
89 #define B44_ETHIPV4UDP_HLEN 42
91 static char version[] __devinitdata =
92 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION "\n";
94 MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
95 MODULE_DESCRIPTION("Broadcom 44xx/47xx 10/100 PCI ethernet driver");
96 MODULE_LICENSE("GPL");
97 MODULE_VERSION(DRV_MODULE_VERSION);
99 static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
100 module_param(b44_debug, int, 0);
101 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
104 #ifdef CONFIG_B44_PCI
105 static const struct pci_device_id b44_pci_tbl[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401) },
107 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0) },
108 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1) },
109 { 0 } /* terminate list with empty entry */
111 MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
113 static struct pci_driver b44_pci_driver = {
114 .name = DRV_MODULE_NAME,
115 .id_table = b44_pci_tbl,
117 #endif /* CONFIG_B44_PCI */
119 static const struct ssb_device_id b44_ssb_tbl[] = {
120 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET, SSB_ANY_REV),
123 MODULE_DEVICE_TABLE(ssb, b44_ssb_tbl);
125 static void b44_halt(struct b44 *);
126 static void b44_init_rings(struct b44 *);
128 #define B44_FULL_RESET 1
129 #define B44_FULL_RESET_SKIP_PHY 2
130 #define B44_PARTIAL_RESET 3
131 #define B44_CHIP_RESET_FULL 4
132 #define B44_CHIP_RESET_PARTIAL 5
134 static void b44_init_hw(struct b44 *, int);
136 static int dma_desc_align_mask;
137 static int dma_desc_sync_size;
140 static const char b44_gstrings[][ETH_GSTRING_LEN] = {
141 #define _B44(x...) # x,
146 static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
148 unsigned long offset,
149 enum dma_data_direction dir)
151 ssb_dma_sync_single_range_for_device(sdev, dma_base,
152 offset & dma_desc_align_mask,
153 dma_desc_sync_size, dir);
156 static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
158 unsigned long offset,
159 enum dma_data_direction dir)
161 ssb_dma_sync_single_range_for_cpu(sdev, dma_base,
162 offset & dma_desc_align_mask,
163 dma_desc_sync_size, dir);
166 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
168 return ssb_read32(bp->sdev, reg);
171 static inline void bw32(const struct b44 *bp,
172 unsigned long reg, unsigned long val)
174 ssb_write32(bp->sdev, reg, val);
177 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
178 u32 bit, unsigned long timeout, const int clear)
182 for (i = 0; i < timeout; i++) {
183 u32 val = br32(bp, reg);
185 if (clear && !(val & bit))
187 if (!clear && (val & bit))
192 printk(KERN_ERR PFX "%s: BUG! Timeout waiting for bit %08x of register "
196 (clear ? "clear" : "set"));
202 static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
206 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
207 (index << CAM_CTRL_INDEX_SHIFT)));
209 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
211 val = br32(bp, B44_CAM_DATA_LO);
213 data[2] = (val >> 24) & 0xFF;
214 data[3] = (val >> 16) & 0xFF;
215 data[4] = (val >> 8) & 0xFF;
216 data[5] = (val >> 0) & 0xFF;
218 val = br32(bp, B44_CAM_DATA_HI);
220 data[0] = (val >> 8) & 0xFF;
221 data[1] = (val >> 0) & 0xFF;
224 static inline void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
228 val = ((u32) data[2]) << 24;
229 val |= ((u32) data[3]) << 16;
230 val |= ((u32) data[4]) << 8;
231 val |= ((u32) data[5]) << 0;
232 bw32(bp, B44_CAM_DATA_LO, val);
233 val = (CAM_DATA_HI_VALID |
234 (((u32) data[0]) << 8) |
235 (((u32) data[1]) << 0));
236 bw32(bp, B44_CAM_DATA_HI, val);
237 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
238 (index << CAM_CTRL_INDEX_SHIFT)));
239 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
242 static inline void __b44_disable_ints(struct b44 *bp)
244 bw32(bp, B44_IMASK, 0);
247 static void b44_disable_ints(struct b44 *bp)
249 __b44_disable_ints(bp);
251 /* Flush posted writes. */
255 static void b44_enable_ints(struct b44 *bp)
257 bw32(bp, B44_IMASK, bp->imask);
260 static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
264 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
265 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
266 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
267 (phy_addr << MDIO_DATA_PMD_SHIFT) |
268 (reg << MDIO_DATA_RA_SHIFT) |
269 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
270 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
271 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
276 static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
278 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
279 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
280 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
281 (phy_addr << MDIO_DATA_PMD_SHIFT) |
282 (reg << MDIO_DATA_RA_SHIFT) |
283 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
284 (val & MDIO_DATA_DATA)));
285 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
288 static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
290 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
293 return __b44_readphy(bp, bp->phy_addr, reg, val);
296 static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
298 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
301 return __b44_writephy(bp, bp->phy_addr, reg, val);
304 /* miilib interface */
305 static int b44_mii_read(struct net_device *dev, int phy_id, int location)
308 struct b44 *bp = netdev_priv(dev);
309 int rc = __b44_readphy(bp, phy_id, location, &val);
315 static void b44_mii_write(struct net_device *dev, int phy_id, int location,
318 struct b44 *bp = netdev_priv(dev);
319 __b44_writephy(bp, phy_id, location, val);
322 static int b44_phy_reset(struct b44 *bp)
327 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
329 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
333 err = b44_readphy(bp, MII_BMCR, &val);
335 if (val & BMCR_RESET) {
336 printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
345 static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
349 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
350 bp->flags |= pause_flags;
352 val = br32(bp, B44_RXCONFIG);
353 if (pause_flags & B44_FLAG_RX_PAUSE)
354 val |= RXCONFIG_FLOW;
356 val &= ~RXCONFIG_FLOW;
357 bw32(bp, B44_RXCONFIG, val);
359 val = br32(bp, B44_MAC_FLOW);
360 if (pause_flags & B44_FLAG_TX_PAUSE)
361 val |= (MAC_FLOW_PAUSE_ENAB |
362 (0xc0 & MAC_FLOW_RX_HI_WATER));
364 val &= ~MAC_FLOW_PAUSE_ENAB;
365 bw32(bp, B44_MAC_FLOW, val);
368 static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
372 /* The driver supports only rx pause by default because
373 the b44 mac tx pause mechanism generates excessive
375 Use ethtool to turn on b44 tx pause if necessary.
377 if ((local & ADVERTISE_PAUSE_CAP) &&
378 (local & ADVERTISE_PAUSE_ASYM)){
379 if ((remote & LPA_PAUSE_ASYM) &&
380 !(remote & LPA_PAUSE_CAP))
381 pause_enab |= B44_FLAG_RX_PAUSE;
384 __b44_set_flow_ctrl(bp, pause_enab);
387 #ifdef SSB_DRIVER_MIPS
388 extern char *nvram_get(char *name);
389 static void b44_wap54g10_workaround(struct b44 *bp)
396 * workaround for bad hardware design in Linksys WAP54G v1.0
397 * see https://dev.openwrt.org/ticket/146
398 * check and reset bit "isolate"
400 str = nvram_get("boardnum");
403 if (simple_strtoul(str, NULL, 0) == 2) {
404 err = __b44_readphy(bp, 0, MII_BMCR, &val);
407 if (!(val & BMCR_ISOLATE))
409 val &= ~BMCR_ISOLATE;
410 err = __b44_writephy(bp, 0, MII_BMCR, val);
416 printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n");
419 static inline void b44_wap54g10_workaround(struct b44 *bp)
424 static int b44_setup_phy(struct b44 *bp)
429 b44_wap54g10_workaround(bp);
431 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
433 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
435 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
436 val & MII_ALEDCTRL_ALLMSK)) != 0)
438 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
440 if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
441 val | MII_TLEDCTRL_ENABLE)) != 0)
444 if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
445 u32 adv = ADVERTISE_CSMA;
447 if (bp->flags & B44_FLAG_ADV_10HALF)
448 adv |= ADVERTISE_10HALF;
449 if (bp->flags & B44_FLAG_ADV_10FULL)
450 adv |= ADVERTISE_10FULL;
451 if (bp->flags & B44_FLAG_ADV_100HALF)
452 adv |= ADVERTISE_100HALF;
453 if (bp->flags & B44_FLAG_ADV_100FULL)
454 adv |= ADVERTISE_100FULL;
456 if (bp->flags & B44_FLAG_PAUSE_AUTO)
457 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
459 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
461 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
462 BMCR_ANRESTART))) != 0)
467 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
469 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
470 if (bp->flags & B44_FLAG_100_BASE_T)
471 bmcr |= BMCR_SPEED100;
472 if (bp->flags & B44_FLAG_FULL_DUPLEX)
473 bmcr |= BMCR_FULLDPLX;
474 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
477 /* Since we will not be negotiating there is no safe way
478 * to determine if the link partner supports flow control
479 * or not. So just disable it completely in this case.
481 b44_set_flow_ctrl(bp, 0, 0);
488 static void b44_stats_update(struct b44 *bp)
493 val = &bp->hw_stats.tx_good_octets;
494 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
495 *val++ += br32(bp, reg);
501 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
502 *val++ += br32(bp, reg);
506 static void b44_link_report(struct b44 *bp)
508 if (!netif_carrier_ok(bp->dev)) {
509 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
511 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
513 (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
514 (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
516 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
519 (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
520 (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
524 static void b44_check_phy(struct b44 *bp)
528 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
529 bp->flags |= B44_FLAG_100_BASE_T;
530 bp->flags |= B44_FLAG_FULL_DUPLEX;
531 if (!netif_carrier_ok(bp->dev)) {
532 u32 val = br32(bp, B44_TX_CTRL);
533 val |= TX_CTRL_DUPLEX;
534 bw32(bp, B44_TX_CTRL, val);
535 netif_carrier_on(bp->dev);
541 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
542 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
544 if (aux & MII_AUXCTRL_SPEED)
545 bp->flags |= B44_FLAG_100_BASE_T;
547 bp->flags &= ~B44_FLAG_100_BASE_T;
548 if (aux & MII_AUXCTRL_DUPLEX)
549 bp->flags |= B44_FLAG_FULL_DUPLEX;
551 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
553 if (!netif_carrier_ok(bp->dev) &&
554 (bmsr & BMSR_LSTATUS)) {
555 u32 val = br32(bp, B44_TX_CTRL);
556 u32 local_adv, remote_adv;
558 if (bp->flags & B44_FLAG_FULL_DUPLEX)
559 val |= TX_CTRL_DUPLEX;
561 val &= ~TX_CTRL_DUPLEX;
562 bw32(bp, B44_TX_CTRL, val);
564 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
565 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
566 !b44_readphy(bp, MII_LPA, &remote_adv))
567 b44_set_flow_ctrl(bp, local_adv, remote_adv);
570 netif_carrier_on(bp->dev);
572 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
574 netif_carrier_off(bp->dev);
578 if (bmsr & BMSR_RFAULT)
579 printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
582 printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
587 static void b44_timer(unsigned long __opaque)
589 struct b44 *bp = (struct b44 *) __opaque;
591 spin_lock_irq(&bp->lock);
595 b44_stats_update(bp);
597 spin_unlock_irq(&bp->lock);
599 mod_timer(&bp->timer, round_jiffies(jiffies + HZ));
602 static void b44_tx(struct b44 *bp)
606 cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
607 cur /= sizeof(struct dma_desc);
609 /* XXX needs updating when NETIF_F_SG is supported */
610 for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
611 struct ring_info *rp = &bp->tx_buffers[cons];
612 struct sk_buff *skb = rp->skb;
616 ssb_dma_unmap_single(bp->sdev,
621 dev_kfree_skb_irq(skb);
625 if (netif_queue_stopped(bp->dev) &&
626 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
627 netif_wake_queue(bp->dev);
629 bw32(bp, B44_GPTIMER, 0);
632 /* Works like this. This chip writes a 'struct rx_header" 30 bytes
633 * before the DMA address you give it. So we allocate 30 more bytes
634 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
635 * point the chip at 30 bytes past where the rx_header will go.
637 static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
640 struct ring_info *src_map, *map;
641 struct rx_header *rh;
649 src_map = &bp->rx_buffers[src_idx];
650 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
651 map = &bp->rx_buffers[dest_idx];
652 skb = netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ);
656 mapping = ssb_dma_map_single(bp->sdev, skb->data,
660 /* Hardware bug work-around, the chip is unable to do PCI DMA
661 to/from anything above 1GB :-( */
662 if (ssb_dma_mapping_error(bp->sdev, mapping) ||
663 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
665 if (!ssb_dma_mapping_error(bp->sdev, mapping))
666 ssb_dma_unmap_single(bp->sdev, mapping,
667 RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
668 dev_kfree_skb_any(skb);
669 skb = __netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ, GFP_ATOMIC|GFP_DMA);
672 mapping = ssb_dma_map_single(bp->sdev, skb->data,
675 if (ssb_dma_mapping_error(bp->sdev, mapping) ||
676 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
677 if (!ssb_dma_mapping_error(bp->sdev, mapping))
678 ssb_dma_unmap_single(bp->sdev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
679 dev_kfree_skb_any(skb);
682 bp->force_copybreak = 1;
685 rh = (struct rx_header *) skb->data;
691 map->mapping = mapping;
696 ctrl = (DESC_CTRL_LEN & RX_PKT_BUF_SZ);
697 if (dest_idx == (B44_RX_RING_SIZE - 1))
698 ctrl |= DESC_CTRL_EOT;
700 dp = &bp->rx_ring[dest_idx];
701 dp->ctrl = cpu_to_le32(ctrl);
702 dp->addr = cpu_to_le32((u32) mapping + bp->dma_offset);
704 if (bp->flags & B44_FLAG_RX_RING_HACK)
705 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
706 dest_idx * sizeof(*dp),
709 return RX_PKT_BUF_SZ;
712 static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
714 struct dma_desc *src_desc, *dest_desc;
715 struct ring_info *src_map, *dest_map;
716 struct rx_header *rh;
720 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
721 dest_desc = &bp->rx_ring[dest_idx];
722 dest_map = &bp->rx_buffers[dest_idx];
723 src_desc = &bp->rx_ring[src_idx];
724 src_map = &bp->rx_buffers[src_idx];
726 dest_map->skb = src_map->skb;
727 rh = (struct rx_header *) src_map->skb->data;
730 dest_map->mapping = src_map->mapping;
732 if (bp->flags & B44_FLAG_RX_RING_HACK)
733 b44_sync_dma_desc_for_cpu(bp->sdev, bp->rx_ring_dma,
734 src_idx * sizeof(*src_desc),
737 ctrl = src_desc->ctrl;
738 if (dest_idx == (B44_RX_RING_SIZE - 1))
739 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
741 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
743 dest_desc->ctrl = ctrl;
744 dest_desc->addr = src_desc->addr;
748 if (bp->flags & B44_FLAG_RX_RING_HACK)
749 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
750 dest_idx * sizeof(*dest_desc),
753 ssb_dma_sync_single_for_device(bp->sdev, dest_map->mapping,
758 static int b44_rx(struct b44 *bp, int budget)
764 prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
765 prod /= sizeof(struct dma_desc);
768 while (cons != prod && budget > 0) {
769 struct ring_info *rp = &bp->rx_buffers[cons];
770 struct sk_buff *skb = rp->skb;
771 dma_addr_t map = rp->mapping;
772 struct rx_header *rh;
775 ssb_dma_sync_single_for_cpu(bp->sdev, map,
778 rh = (struct rx_header *) skb->data;
779 len = le16_to_cpu(rh->len);
780 if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
781 (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
783 b44_recycle_rx(bp, cons, bp->rx_prod);
785 bp->stats.rx_dropped++;
795 len = le16_to_cpu(rh->len);
796 } while (len == 0 && i++ < 5);
804 if (!bp->force_copybreak && len > RX_COPY_THRESHOLD) {
806 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
809 ssb_dma_unmap_single(bp->sdev, map,
810 skb_size, DMA_FROM_DEVICE);
811 /* Leave out rx_header */
812 skb_put(skb, len + RX_PKT_OFFSET);
813 skb_pull(skb, RX_PKT_OFFSET);
815 struct sk_buff *copy_skb;
817 b44_recycle_rx(bp, cons, bp->rx_prod);
818 copy_skb = dev_alloc_skb(len + 2);
819 if (copy_skb == NULL)
820 goto drop_it_no_recycle;
822 skb_reserve(copy_skb, 2);
823 skb_put(copy_skb, len);
824 /* DMA sync done above, copy just the actual packet */
825 skb_copy_from_linear_data_offset(skb, RX_PKT_OFFSET,
826 copy_skb->data, len);
829 skb->ip_summed = CHECKSUM_NONE;
830 skb->protocol = eth_type_trans(skb, bp->dev);
831 netif_receive_skb(skb);
835 bp->rx_prod = (bp->rx_prod + 1) &
836 (B44_RX_RING_SIZE - 1);
837 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
841 bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
846 static int b44_poll(struct napi_struct *napi, int budget)
848 struct b44 *bp = container_of(napi, struct b44, napi);
851 spin_lock_irq(&bp->lock);
853 if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
854 /* spin_lock(&bp->tx_lock); */
856 /* spin_unlock(&bp->tx_lock); */
858 spin_unlock_irq(&bp->lock);
861 if (bp->istat & ISTAT_RX)
862 work_done += b44_rx(bp, budget);
864 if (bp->istat & ISTAT_ERRORS) {
867 spin_lock_irqsave(&bp->lock, flags);
870 b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
871 netif_wake_queue(bp->dev);
872 spin_unlock_irqrestore(&bp->lock, flags);
876 if (work_done < budget) {
884 static irqreturn_t b44_interrupt(int irq, void *dev_id)
886 struct net_device *dev = dev_id;
887 struct b44 *bp = netdev_priv(dev);
891 spin_lock(&bp->lock);
893 istat = br32(bp, B44_ISTAT);
894 imask = br32(bp, B44_IMASK);
896 /* The interrupt mask register controls which interrupt bits
897 * will actually raise an interrupt to the CPU when set by hw/firmware,
898 * but doesn't mask off the bits.
904 if (unlikely(!netif_running(dev))) {
905 printk(KERN_INFO "%s: late interrupt.\n", dev->name);
909 if (napi_schedule_prep(&bp->napi)) {
910 /* NOTE: These writes are posted by the readback of
911 * the ISTAT register below.
914 __b44_disable_ints(bp);
915 __napi_schedule(&bp->napi);
917 printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
922 bw32(bp, B44_ISTAT, istat);
925 spin_unlock(&bp->lock);
926 return IRQ_RETVAL(handled);
929 static void b44_tx_timeout(struct net_device *dev)
931 struct b44 *bp = netdev_priv(dev);
933 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
936 spin_lock_irq(&bp->lock);
940 b44_init_hw(bp, B44_FULL_RESET);
942 spin_unlock_irq(&bp->lock);
946 netif_wake_queue(dev);
949 static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
951 struct b44 *bp = netdev_priv(dev);
952 int rc = NETDEV_TX_OK;
954 u32 len, entry, ctrl;
957 spin_lock_irq(&bp->lock);
959 /* This is a hard error, log it. */
960 if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
961 netif_stop_queue(dev);
962 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
967 mapping = ssb_dma_map_single(bp->sdev, skb->data, len, DMA_TO_DEVICE);
968 if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
969 struct sk_buff *bounce_skb;
971 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
972 if (!ssb_dma_mapping_error(bp->sdev, mapping))
973 ssb_dma_unmap_single(bp->sdev, mapping, len,
976 bounce_skb = __netdev_alloc_skb(dev, len, GFP_ATOMIC | GFP_DMA);
980 mapping = ssb_dma_map_single(bp->sdev, bounce_skb->data,
982 if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
983 if (!ssb_dma_mapping_error(bp->sdev, mapping))
984 ssb_dma_unmap_single(bp->sdev, mapping,
986 dev_kfree_skb_any(bounce_skb);
990 skb_copy_from_linear_data(skb, skb_put(bounce_skb, len), len);
991 dev_kfree_skb_any(skb);
996 bp->tx_buffers[entry].skb = skb;
997 bp->tx_buffers[entry].mapping = mapping;
999 ctrl = (len & DESC_CTRL_LEN);
1000 ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
1001 if (entry == (B44_TX_RING_SIZE - 1))
1002 ctrl |= DESC_CTRL_EOT;
1004 bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
1005 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
1007 if (bp->flags & B44_FLAG_TX_RING_HACK)
1008 b44_sync_dma_desc_for_device(bp->sdev, bp->tx_ring_dma,
1009 entry * sizeof(bp->tx_ring[0]),
1012 entry = NEXT_TX(entry);
1014 bp->tx_prod = entry;
1018 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1019 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1020 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1021 if (bp->flags & B44_FLAG_REORDER_BUG)
1022 br32(bp, B44_DMATX_PTR);
1024 if (TX_BUFFS_AVAIL(bp) < 1)
1025 netif_stop_queue(dev);
1027 dev->trans_start = jiffies;
1030 spin_unlock_irq(&bp->lock);
1035 rc = NETDEV_TX_BUSY;
1039 static int b44_change_mtu(struct net_device *dev, int new_mtu)
1041 struct b44 *bp = netdev_priv(dev);
1043 if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1046 if (!netif_running(dev)) {
1047 /* We'll just catch it later when the
1054 spin_lock_irq(&bp->lock);
1058 b44_init_hw(bp, B44_FULL_RESET);
1059 spin_unlock_irq(&bp->lock);
1061 b44_enable_ints(bp);
1066 /* Free up pending packets in all rx/tx rings.
1068 * The chip has been shut down and the driver detached from
1069 * the networking, so no interrupts or new tx packets will
1070 * end up in the driver. bp->lock is not held and we are not
1071 * in an interrupt context and thus may sleep.
1073 static void b44_free_rings(struct b44 *bp)
1075 struct ring_info *rp;
1078 for (i = 0; i < B44_RX_RING_SIZE; i++) {
1079 rp = &bp->rx_buffers[i];
1081 if (rp->skb == NULL)
1083 ssb_dma_unmap_single(bp->sdev, rp->mapping, RX_PKT_BUF_SZ,
1085 dev_kfree_skb_any(rp->skb);
1089 /* XXX needs changes once NETIF_F_SG is set... */
1090 for (i = 0; i < B44_TX_RING_SIZE; i++) {
1091 rp = &bp->tx_buffers[i];
1093 if (rp->skb == NULL)
1095 ssb_dma_unmap_single(bp->sdev, rp->mapping, rp->skb->len,
1097 dev_kfree_skb_any(rp->skb);
1102 /* Initialize tx/rx rings for packet processing.
1104 * The chip has been shut down and the driver detached from
1105 * the networking, so no interrupts or new tx packets will
1106 * end up in the driver.
1108 static void b44_init_rings(struct b44 *bp)
1114 memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1115 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1117 if (bp->flags & B44_FLAG_RX_RING_HACK)
1118 ssb_dma_sync_single_for_device(bp->sdev, bp->rx_ring_dma,
1122 if (bp->flags & B44_FLAG_TX_RING_HACK)
1123 ssb_dma_sync_single_for_device(bp->sdev, bp->tx_ring_dma,
1127 for (i = 0; i < bp->rx_pending; i++) {
1128 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1134 * Must not be invoked with interrupt sources disabled and
1135 * the hardware shutdown down.
1137 static void b44_free_consistent(struct b44 *bp)
1139 kfree(bp->rx_buffers);
1140 bp->rx_buffers = NULL;
1141 kfree(bp->tx_buffers);
1142 bp->tx_buffers = NULL;
1144 if (bp->flags & B44_FLAG_RX_RING_HACK) {
1145 ssb_dma_unmap_single(bp->sdev, bp->rx_ring_dma,
1150 ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
1151 bp->rx_ring, bp->rx_ring_dma,
1154 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1157 if (bp->flags & B44_FLAG_TX_RING_HACK) {
1158 ssb_dma_unmap_single(bp->sdev, bp->tx_ring_dma,
1163 ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
1164 bp->tx_ring, bp->tx_ring_dma,
1167 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1172 * Must not be invoked with interrupt sources disabled and
1173 * the hardware shutdown down. Can sleep.
1175 static int b44_alloc_consistent(struct b44 *bp, gfp_t gfp)
1179 size = B44_RX_RING_SIZE * sizeof(struct ring_info);
1180 bp->rx_buffers = kzalloc(size, gfp);
1181 if (!bp->rx_buffers)
1184 size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1185 bp->tx_buffers = kzalloc(size, gfp);
1186 if (!bp->tx_buffers)
1189 size = DMA_TABLE_BYTES;
1190 bp->rx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->rx_ring_dma, gfp);
1192 /* Allocation may have failed due to pci_alloc_consistent
1193 insisting on use of GFP_DMA, which is more restrictive
1194 than necessary... */
1195 struct dma_desc *rx_ring;
1196 dma_addr_t rx_ring_dma;
1198 rx_ring = kzalloc(size, gfp);
1202 rx_ring_dma = ssb_dma_map_single(bp->sdev, rx_ring,
1206 if (ssb_dma_mapping_error(bp->sdev, rx_ring_dma) ||
1207 rx_ring_dma + size > DMA_BIT_MASK(30)) {
1212 bp->rx_ring = rx_ring;
1213 bp->rx_ring_dma = rx_ring_dma;
1214 bp->flags |= B44_FLAG_RX_RING_HACK;
1217 bp->tx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->tx_ring_dma, gfp);
1219 /* Allocation may have failed due to ssb_dma_alloc_consistent
1220 insisting on use of GFP_DMA, which is more restrictive
1221 than necessary... */
1222 struct dma_desc *tx_ring;
1223 dma_addr_t tx_ring_dma;
1225 tx_ring = kzalloc(size, gfp);
1229 tx_ring_dma = ssb_dma_map_single(bp->sdev, tx_ring,
1233 if (ssb_dma_mapping_error(bp->sdev, tx_ring_dma) ||
1234 tx_ring_dma + size > DMA_BIT_MASK(30)) {
1239 bp->tx_ring = tx_ring;
1240 bp->tx_ring_dma = tx_ring_dma;
1241 bp->flags |= B44_FLAG_TX_RING_HACK;
1247 b44_free_consistent(bp);
1251 /* bp->lock is held. */
1252 static void b44_clear_stats(struct b44 *bp)
1256 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1257 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1259 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1263 /* bp->lock is held. */
1264 static void b44_chip_reset(struct b44 *bp, int reset_kind)
1266 struct ssb_device *sdev = bp->sdev;
1269 was_enabled = ssb_device_is_enabled(bp->sdev);
1271 ssb_device_enable(bp->sdev, 0);
1272 ssb_pcicore_dev_irqvecs_enable(&sdev->bus->pcicore, sdev);
1275 bw32(bp, B44_RCV_LAZY, 0);
1276 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1277 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 200, 1);
1278 bw32(bp, B44_DMATX_CTRL, 0);
1279 bp->tx_prod = bp->tx_cons = 0;
1280 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1281 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1284 bw32(bp, B44_DMARX_CTRL, 0);
1285 bp->rx_prod = bp->rx_cons = 0;
1288 b44_clear_stats(bp);
1291 * Don't enable PHY if we are doing a partial reset
1292 * we are probably going to power down
1294 if (reset_kind == B44_CHIP_RESET_PARTIAL)
1297 switch (sdev->bus->bustype) {
1298 case SSB_BUSTYPE_SSB:
1299 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1300 (((ssb_clockspeed(sdev->bus) + (B44_MDC_RATIO / 2)) / B44_MDC_RATIO)
1301 & MDIO_CTRL_MAXF_MASK)));
1303 case SSB_BUSTYPE_PCI:
1304 case SSB_BUSTYPE_PCMCIA:
1305 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1306 (0x0d & MDIO_CTRL_MAXF_MASK)));
1310 br32(bp, B44_MDIO_CTRL);
1312 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1313 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1314 br32(bp, B44_ENET_CTRL);
1315 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1317 u32 val = br32(bp, B44_DEVCTRL);
1319 if (val & DEVCTRL_EPR) {
1320 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1321 br32(bp, B44_DEVCTRL);
1324 bp->flags |= B44_FLAG_INTERNAL_PHY;
1328 /* bp->lock is held. */
1329 static void b44_halt(struct b44 *bp)
1331 b44_disable_ints(bp);
1334 /* power down PHY */
1335 printk(KERN_INFO PFX "%s: powering down PHY\n", bp->dev->name);
1336 bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN);
1337 /* now reset the chip, but without enabling the MAC&PHY
1338 * part of it. This has to be done _after_ we shut down the PHY */
1339 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1342 /* bp->lock is held. */
1343 static void __b44_set_mac_addr(struct b44 *bp)
1345 bw32(bp, B44_CAM_CTRL, 0);
1346 if (!(bp->dev->flags & IFF_PROMISC)) {
1349 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1350 val = br32(bp, B44_CAM_CTRL);
1351 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1355 static int b44_set_mac_addr(struct net_device *dev, void *p)
1357 struct b44 *bp = netdev_priv(dev);
1358 struct sockaddr *addr = p;
1361 if (netif_running(dev))
1364 if (!is_valid_ether_addr(addr->sa_data))
1367 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1369 spin_lock_irq(&bp->lock);
1371 val = br32(bp, B44_RXCONFIG);
1372 if (!(val & RXCONFIG_CAM_ABSENT))
1373 __b44_set_mac_addr(bp);
1375 spin_unlock_irq(&bp->lock);
1380 /* Called at device open time to get the chip ready for
1381 * packet processing. Invoked with bp->lock held.
1383 static void __b44_set_rx_mode(struct net_device *);
1384 static void b44_init_hw(struct b44 *bp, int reset_kind)
1388 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
1389 if (reset_kind == B44_FULL_RESET) {
1394 /* Enable CRC32, set proper LED modes and power on PHY */
1395 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1396 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1398 /* This sets the MAC address too. */
1399 __b44_set_rx_mode(bp->dev);
1401 /* MTU + eth header + possible VLAN tag + struct rx_header */
1402 bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1403 bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1405 bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1406 if (reset_kind == B44_PARTIAL_RESET) {
1407 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1408 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1410 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1411 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1412 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1413 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1414 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1416 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1417 bp->rx_prod = bp->rx_pending;
1419 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1422 val = br32(bp, B44_ENET_CTRL);
1423 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1426 static int b44_open(struct net_device *dev)
1428 struct b44 *bp = netdev_priv(dev);
1431 err = b44_alloc_consistent(bp, GFP_KERNEL);
1435 napi_enable(&bp->napi);
1438 b44_init_hw(bp, B44_FULL_RESET);
1442 err = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
1443 if (unlikely(err < 0)) {
1444 napi_disable(&bp->napi);
1445 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1447 b44_free_consistent(bp);
1451 init_timer(&bp->timer);
1452 bp->timer.expires = jiffies + HZ;
1453 bp->timer.data = (unsigned long) bp;
1454 bp->timer.function = b44_timer;
1455 add_timer(&bp->timer);
1457 b44_enable_ints(bp);
1458 netif_start_queue(dev);
1463 #ifdef CONFIG_NET_POLL_CONTROLLER
1465 * Polling receive - used by netconsole and other diagnostic tools
1466 * to allow network i/o with interrupts disabled.
1468 static void b44_poll_controller(struct net_device *dev)
1470 disable_irq(dev->irq);
1471 b44_interrupt(dev->irq, dev);
1472 enable_irq(dev->irq);
1476 static void bwfilter_table(struct b44 *bp, u8 *pp, u32 bytes, u32 table_offset)
1479 u32 *pattern = (u32 *) pp;
1481 for (i = 0; i < bytes; i += sizeof(u32)) {
1482 bw32(bp, B44_FILT_ADDR, table_offset + i);
1483 bw32(bp, B44_FILT_DATA, pattern[i / sizeof(u32)]);
1487 static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset)
1490 int k, j, len = offset;
1491 int ethaddr_bytes = ETH_ALEN;
1493 memset(ppattern + offset, 0xff, magicsync);
1494 for (j = 0; j < magicsync; j++)
1495 set_bit(len++, (unsigned long *) pmask);
1497 for (j = 0; j < B44_MAX_PATTERNS; j++) {
1498 if ((B44_PATTERN_SIZE - len) >= ETH_ALEN)
1499 ethaddr_bytes = ETH_ALEN;
1501 ethaddr_bytes = B44_PATTERN_SIZE - len;
1502 if (ethaddr_bytes <=0)
1504 for (k = 0; k< ethaddr_bytes; k++) {
1505 ppattern[offset + magicsync +
1506 (j * ETH_ALEN) + k] = macaddr[k];
1508 set_bit(len, (unsigned long *) pmask);
1514 /* Setup magic packet patterns in the b44 WOL
1515 * pattern matching filter.
1517 static void b44_setup_pseudo_magicp(struct b44 *bp)
1521 int plen0, plen1, plen2;
1523 u8 pwol_mask[B44_PMASK_SIZE];
1525 pwol_pattern = kzalloc(B44_PATTERN_SIZE, GFP_KERNEL);
1526 if (!pwol_pattern) {
1527 printk(KERN_ERR PFX "Memory not available for WOL\n");
1531 /* Ipv4 magic packet pattern - pattern 0.*/
1532 memset(pwol_mask, 0, B44_PMASK_SIZE);
1533 plen0 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1534 B44_ETHIPV4UDP_HLEN);
1536 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE, B44_PATTERN_BASE);
1537 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE, B44_PMASK_BASE);
1539 /* Raw ethernet II magic packet pattern - pattern 1 */
1540 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1541 memset(pwol_mask, 0, B44_PMASK_SIZE);
1542 plen1 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1545 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1546 B44_PATTERN_BASE + B44_PATTERN_SIZE);
1547 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1548 B44_PMASK_BASE + B44_PMASK_SIZE);
1550 /* Ipv6 magic packet pattern - pattern 2 */
1551 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1552 memset(pwol_mask, 0, B44_PMASK_SIZE);
1553 plen2 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1554 B44_ETHIPV6UDP_HLEN);
1556 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1557 B44_PATTERN_BASE + B44_PATTERN_SIZE + B44_PATTERN_SIZE);
1558 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1559 B44_PMASK_BASE + B44_PMASK_SIZE + B44_PMASK_SIZE);
1561 kfree(pwol_pattern);
1563 /* set these pattern's lengths: one less than each real length */
1564 val = plen0 | (plen1 << 8) | (plen2 << 16) | WKUP_LEN_ENABLE_THREE;
1565 bw32(bp, B44_WKUP_LEN, val);
1567 /* enable wakeup pattern matching */
1568 val = br32(bp, B44_DEVCTRL);
1569 bw32(bp, B44_DEVCTRL, val | DEVCTRL_PFE);
1573 #ifdef CONFIG_B44_PCI
1574 static void b44_setup_wol_pci(struct b44 *bp)
1578 if (bp->sdev->bus->bustype != SSB_BUSTYPE_SSB) {
1579 bw32(bp, SSB_TMSLOW, br32(bp, SSB_TMSLOW) | SSB_TMSLOW_PE);
1580 pci_read_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, &val);
1581 pci_write_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, val | SSB_PE);
1585 static inline void b44_setup_wol_pci(struct b44 *bp) { }
1586 #endif /* CONFIG_B44_PCI */
1588 static void b44_setup_wol(struct b44 *bp)
1592 bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);
1594 if (bp->flags & B44_FLAG_B0_ANDLATER) {
1596 bw32(bp, B44_WKUP_LEN, WKUP_LEN_DISABLE);
1598 val = bp->dev->dev_addr[2] << 24 |
1599 bp->dev->dev_addr[3] << 16 |
1600 bp->dev->dev_addr[4] << 8 |
1601 bp->dev->dev_addr[5];
1602 bw32(bp, B44_ADDR_LO, val);
1604 val = bp->dev->dev_addr[0] << 8 |
1605 bp->dev->dev_addr[1];
1606 bw32(bp, B44_ADDR_HI, val);
1608 val = br32(bp, B44_DEVCTRL);
1609 bw32(bp, B44_DEVCTRL, val | DEVCTRL_MPM | DEVCTRL_PFE);
1612 b44_setup_pseudo_magicp(bp);
1614 b44_setup_wol_pci(bp);
1617 static int b44_close(struct net_device *dev)
1619 struct b44 *bp = netdev_priv(dev);
1621 netif_stop_queue(dev);
1623 napi_disable(&bp->napi);
1625 del_timer_sync(&bp->timer);
1627 spin_lock_irq(&bp->lock);
1631 netif_carrier_off(dev);
1633 spin_unlock_irq(&bp->lock);
1635 free_irq(dev->irq, dev);
1637 if (bp->flags & B44_FLAG_WOL_ENABLE) {
1638 b44_init_hw(bp, B44_PARTIAL_RESET);
1642 b44_free_consistent(bp);
1647 static struct net_device_stats *b44_get_stats(struct net_device *dev)
1649 struct b44 *bp = netdev_priv(dev);
1650 struct net_device_stats *nstat = &bp->stats;
1651 struct b44_hw_stats *hwstat = &bp->hw_stats;
1653 /* Convert HW stats into netdevice stats. */
1654 nstat->rx_packets = hwstat->rx_pkts;
1655 nstat->tx_packets = hwstat->tx_pkts;
1656 nstat->rx_bytes = hwstat->rx_octets;
1657 nstat->tx_bytes = hwstat->tx_octets;
1658 nstat->tx_errors = (hwstat->tx_jabber_pkts +
1659 hwstat->tx_oversize_pkts +
1660 hwstat->tx_underruns +
1661 hwstat->tx_excessive_cols +
1662 hwstat->tx_late_cols);
1663 nstat->multicast = hwstat->tx_multicast_pkts;
1664 nstat->collisions = hwstat->tx_total_cols;
1666 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1667 hwstat->rx_undersize);
1668 nstat->rx_over_errors = hwstat->rx_missed_pkts;
1669 nstat->rx_frame_errors = hwstat->rx_align_errs;
1670 nstat->rx_crc_errors = hwstat->rx_crc_errs;
1671 nstat->rx_errors = (hwstat->rx_jabber_pkts +
1672 hwstat->rx_oversize_pkts +
1673 hwstat->rx_missed_pkts +
1674 hwstat->rx_crc_align_errs +
1675 hwstat->rx_undersize +
1676 hwstat->rx_crc_errs +
1677 hwstat->rx_align_errs +
1678 hwstat->rx_symbol_errs);
1680 nstat->tx_aborted_errors = hwstat->tx_underruns;
1682 /* Carrier lost counter seems to be broken for some devices */
1683 nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1689 static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1691 struct dev_mc_list *mclist;
1694 num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1695 mclist = dev->mc_list;
1696 for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1697 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1702 static void __b44_set_rx_mode(struct net_device *dev)
1704 struct b44 *bp = netdev_priv(dev);
1707 val = br32(bp, B44_RXCONFIG);
1708 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1709 if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
1710 val |= RXCONFIG_PROMISC;
1711 bw32(bp, B44_RXCONFIG, val);
1713 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
1716 __b44_set_mac_addr(bp);
1718 if ((dev->flags & IFF_ALLMULTI) ||
1719 (dev->mc_count > B44_MCAST_TABLE_SIZE))
1720 val |= RXCONFIG_ALLMULTI;
1722 i = __b44_load_mcast(bp, dev);
1725 __b44_cam_write(bp, zero, i);
1727 bw32(bp, B44_RXCONFIG, val);
1728 val = br32(bp, B44_CAM_CTRL);
1729 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1733 static void b44_set_rx_mode(struct net_device *dev)
1735 struct b44 *bp = netdev_priv(dev);
1737 spin_lock_irq(&bp->lock);
1738 __b44_set_rx_mode(dev);
1739 spin_unlock_irq(&bp->lock);
1742 static u32 b44_get_msglevel(struct net_device *dev)
1744 struct b44 *bp = netdev_priv(dev);
1745 return bp->msg_enable;
1748 static void b44_set_msglevel(struct net_device *dev, u32 value)
1750 struct b44 *bp = netdev_priv(dev);
1751 bp->msg_enable = value;
1754 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1756 struct b44 *bp = netdev_priv(dev);
1757 struct ssb_bus *bus = bp->sdev->bus;
1759 strncpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1760 strncpy(info->version, DRV_MODULE_VERSION, sizeof(info->driver));
1761 switch (bus->bustype) {
1762 case SSB_BUSTYPE_PCI:
1763 strncpy(info->bus_info, pci_name(bus->host_pci), sizeof(info->bus_info));
1765 case SSB_BUSTYPE_PCMCIA:
1766 case SSB_BUSTYPE_SSB:
1767 strncpy(info->bus_info, "SSB", sizeof(info->bus_info));
1772 static int b44_nway_reset(struct net_device *dev)
1774 struct b44 *bp = netdev_priv(dev);
1778 spin_lock_irq(&bp->lock);
1779 b44_readphy(bp, MII_BMCR, &bmcr);
1780 b44_readphy(bp, MII_BMCR, &bmcr);
1782 if (bmcr & BMCR_ANENABLE) {
1783 b44_writephy(bp, MII_BMCR,
1784 bmcr | BMCR_ANRESTART);
1787 spin_unlock_irq(&bp->lock);
1792 static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1794 struct b44 *bp = netdev_priv(dev);
1796 cmd->supported = (SUPPORTED_Autoneg);
1797 cmd->supported |= (SUPPORTED_100baseT_Half |
1798 SUPPORTED_100baseT_Full |
1799 SUPPORTED_10baseT_Half |
1800 SUPPORTED_10baseT_Full |
1803 cmd->advertising = 0;
1804 if (bp->flags & B44_FLAG_ADV_10HALF)
1805 cmd->advertising |= ADVERTISED_10baseT_Half;
1806 if (bp->flags & B44_FLAG_ADV_10FULL)
1807 cmd->advertising |= ADVERTISED_10baseT_Full;
1808 if (bp->flags & B44_FLAG_ADV_100HALF)
1809 cmd->advertising |= ADVERTISED_100baseT_Half;
1810 if (bp->flags & B44_FLAG_ADV_100FULL)
1811 cmd->advertising |= ADVERTISED_100baseT_Full;
1812 cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1813 cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1814 SPEED_100 : SPEED_10;
1815 cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1816 DUPLEX_FULL : DUPLEX_HALF;
1818 cmd->phy_address = bp->phy_addr;
1819 cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1820 XCVR_INTERNAL : XCVR_EXTERNAL;
1821 cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1822 AUTONEG_DISABLE : AUTONEG_ENABLE;
1823 if (cmd->autoneg == AUTONEG_ENABLE)
1824 cmd->advertising |= ADVERTISED_Autoneg;
1825 if (!netif_running(dev)){
1834 static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1836 struct b44 *bp = netdev_priv(dev);
1838 /* We do not support gigabit. */
1839 if (cmd->autoneg == AUTONEG_ENABLE) {
1840 if (cmd->advertising &
1841 (ADVERTISED_1000baseT_Half |
1842 ADVERTISED_1000baseT_Full))
1844 } else if ((cmd->speed != SPEED_100 &&
1845 cmd->speed != SPEED_10) ||
1846 (cmd->duplex != DUPLEX_HALF &&
1847 cmd->duplex != DUPLEX_FULL)) {
1851 spin_lock_irq(&bp->lock);
1853 if (cmd->autoneg == AUTONEG_ENABLE) {
1854 bp->flags &= ~(B44_FLAG_FORCE_LINK |
1855 B44_FLAG_100_BASE_T |
1856 B44_FLAG_FULL_DUPLEX |
1857 B44_FLAG_ADV_10HALF |
1858 B44_FLAG_ADV_10FULL |
1859 B44_FLAG_ADV_100HALF |
1860 B44_FLAG_ADV_100FULL);
1861 if (cmd->advertising == 0) {
1862 bp->flags |= (B44_FLAG_ADV_10HALF |
1863 B44_FLAG_ADV_10FULL |
1864 B44_FLAG_ADV_100HALF |
1865 B44_FLAG_ADV_100FULL);
1867 if (cmd->advertising & ADVERTISED_10baseT_Half)
1868 bp->flags |= B44_FLAG_ADV_10HALF;
1869 if (cmd->advertising & ADVERTISED_10baseT_Full)
1870 bp->flags |= B44_FLAG_ADV_10FULL;
1871 if (cmd->advertising & ADVERTISED_100baseT_Half)
1872 bp->flags |= B44_FLAG_ADV_100HALF;
1873 if (cmd->advertising & ADVERTISED_100baseT_Full)
1874 bp->flags |= B44_FLAG_ADV_100FULL;
1877 bp->flags |= B44_FLAG_FORCE_LINK;
1878 bp->flags &= ~(B44_FLAG_100_BASE_T | B44_FLAG_FULL_DUPLEX);
1879 if (cmd->speed == SPEED_100)
1880 bp->flags |= B44_FLAG_100_BASE_T;
1881 if (cmd->duplex == DUPLEX_FULL)
1882 bp->flags |= B44_FLAG_FULL_DUPLEX;
1885 if (netif_running(dev))
1888 spin_unlock_irq(&bp->lock);
1893 static void b44_get_ringparam(struct net_device *dev,
1894 struct ethtool_ringparam *ering)
1896 struct b44 *bp = netdev_priv(dev);
1898 ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1899 ering->rx_pending = bp->rx_pending;
1901 /* XXX ethtool lacks a tx_max_pending, oops... */
1904 static int b44_set_ringparam(struct net_device *dev,
1905 struct ethtool_ringparam *ering)
1907 struct b44 *bp = netdev_priv(dev);
1909 if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1910 (ering->rx_mini_pending != 0) ||
1911 (ering->rx_jumbo_pending != 0) ||
1912 (ering->tx_pending > B44_TX_RING_SIZE - 1))
1915 spin_lock_irq(&bp->lock);
1917 bp->rx_pending = ering->rx_pending;
1918 bp->tx_pending = ering->tx_pending;
1922 b44_init_hw(bp, B44_FULL_RESET);
1923 netif_wake_queue(bp->dev);
1924 spin_unlock_irq(&bp->lock);
1926 b44_enable_ints(bp);
1931 static void b44_get_pauseparam(struct net_device *dev,
1932 struct ethtool_pauseparam *epause)
1934 struct b44 *bp = netdev_priv(dev);
1937 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1939 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1941 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1944 static int b44_set_pauseparam(struct net_device *dev,
1945 struct ethtool_pauseparam *epause)
1947 struct b44 *bp = netdev_priv(dev);
1949 spin_lock_irq(&bp->lock);
1950 if (epause->autoneg)
1951 bp->flags |= B44_FLAG_PAUSE_AUTO;
1953 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1954 if (epause->rx_pause)
1955 bp->flags |= B44_FLAG_RX_PAUSE;
1957 bp->flags &= ~B44_FLAG_RX_PAUSE;
1958 if (epause->tx_pause)
1959 bp->flags |= B44_FLAG_TX_PAUSE;
1961 bp->flags &= ~B44_FLAG_TX_PAUSE;
1962 if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1965 b44_init_hw(bp, B44_FULL_RESET);
1967 __b44_set_flow_ctrl(bp, bp->flags);
1969 spin_unlock_irq(&bp->lock);
1971 b44_enable_ints(bp);
1976 static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1980 memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
1985 static int b44_get_sset_count(struct net_device *dev, int sset)
1989 return ARRAY_SIZE(b44_gstrings);
1995 static void b44_get_ethtool_stats(struct net_device *dev,
1996 struct ethtool_stats *stats, u64 *data)
1998 struct b44 *bp = netdev_priv(dev);
1999 u32 *val = &bp->hw_stats.tx_good_octets;
2002 spin_lock_irq(&bp->lock);
2004 b44_stats_update(bp);
2006 for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
2009 spin_unlock_irq(&bp->lock);
2012 static void b44_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2014 struct b44 *bp = netdev_priv(dev);
2016 wol->supported = WAKE_MAGIC;
2017 if (bp->flags & B44_FLAG_WOL_ENABLE)
2018 wol->wolopts = WAKE_MAGIC;
2021 memset(&wol->sopass, 0, sizeof(wol->sopass));
2024 static int b44_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2026 struct b44 *bp = netdev_priv(dev);
2028 spin_lock_irq(&bp->lock);
2029 if (wol->wolopts & WAKE_MAGIC)
2030 bp->flags |= B44_FLAG_WOL_ENABLE;
2032 bp->flags &= ~B44_FLAG_WOL_ENABLE;
2033 spin_unlock_irq(&bp->lock);
2038 static const struct ethtool_ops b44_ethtool_ops = {
2039 .get_drvinfo = b44_get_drvinfo,
2040 .get_settings = b44_get_settings,
2041 .set_settings = b44_set_settings,
2042 .nway_reset = b44_nway_reset,
2043 .get_link = ethtool_op_get_link,
2044 .get_wol = b44_get_wol,
2045 .set_wol = b44_set_wol,
2046 .get_ringparam = b44_get_ringparam,
2047 .set_ringparam = b44_set_ringparam,
2048 .get_pauseparam = b44_get_pauseparam,
2049 .set_pauseparam = b44_set_pauseparam,
2050 .get_msglevel = b44_get_msglevel,
2051 .set_msglevel = b44_set_msglevel,
2052 .get_strings = b44_get_strings,
2053 .get_sset_count = b44_get_sset_count,
2054 .get_ethtool_stats = b44_get_ethtool_stats,
2057 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2059 struct mii_ioctl_data *data = if_mii(ifr);
2060 struct b44 *bp = netdev_priv(dev);
2063 if (!netif_running(dev))
2066 spin_lock_irq(&bp->lock);
2067 err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
2068 spin_unlock_irq(&bp->lock);
2073 static int __devinit b44_get_invariants(struct b44 *bp)
2075 struct ssb_device *sdev = bp->sdev;
2079 bp->dma_offset = ssb_dma_translation(sdev);
2081 if (sdev->bus->bustype == SSB_BUSTYPE_SSB &&
2083 addr = sdev->bus->sprom.et1mac;
2084 bp->phy_addr = sdev->bus->sprom.et1phyaddr;
2086 addr = sdev->bus->sprom.et0mac;
2087 bp->phy_addr = sdev->bus->sprom.et0phyaddr;
2089 /* Some ROMs have buggy PHY addresses with the high
2090 * bits set (sign extension?). Truncate them to a
2091 * valid PHY address. */
2092 bp->phy_addr &= 0x1F;
2094 memcpy(bp->dev->dev_addr, addr, 6);
2096 if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
2097 printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
2101 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
2103 bp->imask = IMASK_DEF;
2105 /* XXX - really required?
2106 bp->flags |= B44_FLAG_BUGGY_TXPTR;
2109 if (bp->sdev->id.revision >= 7)
2110 bp->flags |= B44_FLAG_B0_ANDLATER;
2115 static const struct net_device_ops b44_netdev_ops = {
2116 .ndo_open = b44_open,
2117 .ndo_stop = b44_close,
2118 .ndo_start_xmit = b44_start_xmit,
2119 .ndo_get_stats = b44_get_stats,
2120 .ndo_set_multicast_list = b44_set_rx_mode,
2121 .ndo_set_mac_address = b44_set_mac_addr,
2122 .ndo_validate_addr = eth_validate_addr,
2123 .ndo_do_ioctl = b44_ioctl,
2124 .ndo_tx_timeout = b44_tx_timeout,
2125 .ndo_change_mtu = b44_change_mtu,
2126 #ifdef CONFIG_NET_POLL_CONTROLLER
2127 .ndo_poll_controller = b44_poll_controller,
2131 static int __devinit b44_init_one(struct ssb_device *sdev,
2132 const struct ssb_device_id *ent)
2134 static int b44_version_printed = 0;
2135 struct net_device *dev;
2141 if (b44_version_printed++ == 0)
2142 printk(KERN_INFO "%s", version);
2145 dev = alloc_etherdev(sizeof(*bp));
2147 dev_err(sdev->dev, "Etherdev alloc failed, aborting.\n");
2152 SET_NETDEV_DEV(dev, sdev->dev);
2154 /* No interesting netdevice features in this card... */
2157 bp = netdev_priv(dev);
2160 bp->force_copybreak = 0;
2162 bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
2164 spin_lock_init(&bp->lock);
2166 bp->rx_pending = B44_DEF_RX_RING_PENDING;
2167 bp->tx_pending = B44_DEF_TX_RING_PENDING;
2169 dev->netdev_ops = &b44_netdev_ops;
2170 netif_napi_add(dev, &bp->napi, b44_poll, 64);
2171 dev->watchdog_timeo = B44_TX_TIMEOUT;
2172 dev->irq = sdev->irq;
2173 SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
2175 netif_carrier_off(dev);
2177 err = ssb_bus_powerup(sdev->bus, 0);
2180 "Failed to powerup the bus\n");
2181 goto err_out_free_dev;
2183 err = ssb_dma_set_mask(sdev, DMA_BIT_MASK(30));
2186 "Required 30BIT DMA mask unsupported by the system.\n");
2187 goto err_out_powerdown;
2189 err = b44_get_invariants(bp);
2192 "Problem fetching invariants of chip, aborting.\n");
2193 goto err_out_powerdown;
2196 bp->mii_if.dev = dev;
2197 bp->mii_if.mdio_read = b44_mii_read;
2198 bp->mii_if.mdio_write = b44_mii_write;
2199 bp->mii_if.phy_id = bp->phy_addr;
2200 bp->mii_if.phy_id_mask = 0x1f;
2201 bp->mii_if.reg_num_mask = 0x1f;
2203 /* By default, advertise all speed/duplex settings. */
2204 bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
2205 B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
2207 /* By default, auto-negotiate PAUSE. */
2208 bp->flags |= B44_FLAG_PAUSE_AUTO;
2210 err = register_netdev(dev);
2212 dev_err(sdev->dev, "Cannot register net device, aborting.\n");
2213 goto err_out_powerdown;
2216 ssb_set_drvdata(sdev, dev);
2218 /* Chip reset provides power to the b44 MAC & PCI cores, which
2219 * is necessary for MAC register access.
2221 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
2223 printk(KERN_INFO "%s: Broadcom 44xx/47xx 10/100BaseT Ethernet %pM\n",
2224 dev->name, dev->dev_addr);
2229 ssb_bus_may_powerdown(sdev->bus);
2238 static void __devexit b44_remove_one(struct ssb_device *sdev)
2240 struct net_device *dev = ssb_get_drvdata(sdev);
2242 unregister_netdev(dev);
2243 ssb_device_disable(sdev, 0);
2244 ssb_bus_may_powerdown(sdev->bus);
2246 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
2247 ssb_set_drvdata(sdev, NULL);
2250 static int b44_suspend(struct ssb_device *sdev, pm_message_t state)
2252 struct net_device *dev = ssb_get_drvdata(sdev);
2253 struct b44 *bp = netdev_priv(dev);
2255 if (!netif_running(dev))
2258 del_timer_sync(&bp->timer);
2260 spin_lock_irq(&bp->lock);
2263 netif_carrier_off(bp->dev);
2264 netif_device_detach(bp->dev);
2267 spin_unlock_irq(&bp->lock);
2269 free_irq(dev->irq, dev);
2270 if (bp->flags & B44_FLAG_WOL_ENABLE) {
2271 b44_init_hw(bp, B44_PARTIAL_RESET);
2275 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
2279 static int b44_resume(struct ssb_device *sdev)
2281 struct net_device *dev = ssb_get_drvdata(sdev);
2282 struct b44 *bp = netdev_priv(dev);
2285 rc = ssb_bus_powerup(sdev->bus, 0);
2288 "Failed to powerup the bus\n");
2292 if (!netif_running(dev))
2295 rc = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
2297 printk(KERN_ERR PFX "%s: request_irq failed\n", dev->name);
2301 spin_lock_irq(&bp->lock);
2304 b44_init_hw(bp, B44_FULL_RESET);
2305 netif_device_attach(bp->dev);
2306 spin_unlock_irq(&bp->lock);
2308 b44_enable_ints(bp);
2309 netif_wake_queue(dev);
2311 mod_timer(&bp->timer, jiffies + 1);
2316 static struct ssb_driver b44_ssb_driver = {
2317 .name = DRV_MODULE_NAME,
2318 .id_table = b44_ssb_tbl,
2319 .probe = b44_init_one,
2320 .remove = __devexit_p(b44_remove_one),
2321 .suspend = b44_suspend,
2322 .resume = b44_resume,
2325 static inline int b44_pci_init(void)
2328 #ifdef CONFIG_B44_PCI
2329 err = ssb_pcihost_register(&b44_pci_driver);
2334 static inline void b44_pci_exit(void)
2336 #ifdef CONFIG_B44_PCI
2337 ssb_pcihost_unregister(&b44_pci_driver);
2341 static int __init b44_init(void)
2343 unsigned int dma_desc_align_size = dma_get_cache_alignment();
2346 /* Setup paramaters for syncing RX/TX DMA descriptors */
2347 dma_desc_align_mask = ~(dma_desc_align_size - 1);
2348 dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
2350 err = b44_pci_init();
2353 err = ssb_driver_register(&b44_ssb_driver);
2359 static void __exit b44_cleanup(void)
2361 ssb_driver_unregister(&b44_ssb_driver);
2365 module_init(b44_init);
2366 module_exit(b44_cleanup);