2 * arch/s390/kernel/entry64.S
3 * S390 low-level entry points.
5 * Copyright (C) IBM Corp. 1999,2006
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 * Hartmut Penner (hp@de.ibm.com),
8 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
9 * Heiko Carstens <heiko.carstens@de.ibm.com>
12 #include <linux/sys.h>
13 #include <linux/linkage.h>
14 #include <linux/init.h>
15 #include <asm/cache.h>
16 #include <asm/lowcore.h>
17 #include <asm/errno.h>
18 #include <asm/ptrace.h>
19 #include <asm/thread_info.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/unistd.h>
25 * Stack layout for the system_call stack entry.
26 * The first few entries are identical to the user_regs_struct.
28 SP_PTREGS = STACK_FRAME_OVERHEAD
29 SP_ARGS = STACK_FRAME_OVERHEAD + __PT_ARGS
30 SP_PSW = STACK_FRAME_OVERHEAD + __PT_PSW
31 SP_R0 = STACK_FRAME_OVERHEAD + __PT_GPRS
32 SP_R1 = STACK_FRAME_OVERHEAD + __PT_GPRS + 8
33 SP_R2 = STACK_FRAME_OVERHEAD + __PT_GPRS + 16
34 SP_R3 = STACK_FRAME_OVERHEAD + __PT_GPRS + 24
35 SP_R4 = STACK_FRAME_OVERHEAD + __PT_GPRS + 32
36 SP_R5 = STACK_FRAME_OVERHEAD + __PT_GPRS + 40
37 SP_R6 = STACK_FRAME_OVERHEAD + __PT_GPRS + 48
38 SP_R7 = STACK_FRAME_OVERHEAD + __PT_GPRS + 56
39 SP_R8 = STACK_FRAME_OVERHEAD + __PT_GPRS + 64
40 SP_R9 = STACK_FRAME_OVERHEAD + __PT_GPRS + 72
41 SP_R10 = STACK_FRAME_OVERHEAD + __PT_GPRS + 80
42 SP_R11 = STACK_FRAME_OVERHEAD + __PT_GPRS + 88
43 SP_R12 = STACK_FRAME_OVERHEAD + __PT_GPRS + 96
44 SP_R13 = STACK_FRAME_OVERHEAD + __PT_GPRS + 104
45 SP_R14 = STACK_FRAME_OVERHEAD + __PT_GPRS + 112
46 SP_R15 = STACK_FRAME_OVERHEAD + __PT_GPRS + 120
47 SP_ORIG_R2 = STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2
48 SP_ILC = STACK_FRAME_OVERHEAD + __PT_ILC
49 SP_TRAP = STACK_FRAME_OVERHEAD + __PT_TRAP
50 SP_SIZE = STACK_FRAME_OVERHEAD + __PT_SIZE
52 STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER
53 STACK_SIZE = 1 << STACK_SHIFT
55 _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
56 _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP )
57 _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
60 #define BASED(name) name-system_call(%r13)
62 #ifdef CONFIG_TRACE_IRQFLAGS
64 brasl %r14,trace_hardirqs_on
68 brasl %r14,trace_hardirqs_off
71 .macro TRACE_IRQS_CHECK
72 tm SP_PSW(%r15),0x03 # irqs enabled?
74 brasl %r14,trace_hardirqs_on
76 0: brasl %r14,trace_hardirqs_off
81 #define TRACE_IRQS_OFF
82 #define TRACE_IRQS_CHECK
86 .macro LOCKDEP_SYS_EXIT
87 tm SP_PSW+1(%r15),0x01 # returning to user ?
89 brasl %r14,lockdep_sys_exit
93 #define LOCKDEP_SYS_EXIT
96 .macro STORE_TIMER lc_offset
97 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
102 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
103 .macro UPDATE_VTIME lc_from,lc_to,lc_sum
112 * Register usage in interrupt handlers:
113 * R9 - pointer to current task structure
114 * R13 - pointer to literal pool
115 * R14 - return register for function calls
116 * R15 - kernel stack pointer
119 .macro SAVE_ALL_BASE savearea
120 stmg %r12,%r15,\savearea
121 larl %r13,system_call
124 .macro SAVE_ALL_SVC psworg,savearea
126 lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
129 .macro SAVE_ALL_SYNC psworg,savearea
131 tm \psworg+1,0x01 # test problem state bit
132 jz 2f # skip stack setup save
133 lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
134 #ifdef CONFIG_CHECK_STACK
136 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
143 .macro SAVE_ALL_ASYNC psworg,savearea
145 tm \psworg+1,0x01 # test problem state bit
146 jnz 1f # from user -> load kernel stack
147 clc \psworg+8(8),BASED(.Lcritical_end)
149 clc \psworg+8(8),BASED(.Lcritical_start)
151 brasl %r14,cleanup_critical
152 tm 1(%r12),0x01 # retest problem state after cleanup
154 0: lg %r14,__LC_ASYNC_STACK # are we already on the async. stack ?
156 srag %r14,%r14,STACK_SHIFT
158 1: lg %r15,__LC_ASYNC_STACK # load async stack
159 #ifdef CONFIG_CHECK_STACK
161 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
168 .macro CREATE_STACK_FRAME psworg,savearea
169 aghi %r15,-SP_SIZE # make room for registers & psw
170 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
172 stg %r2,SP_ORIG_R2(%r15) # store original content of gpr 2
173 icm %r12,12,__LC_SVC_ILC
174 stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack
176 mvc SP_R12(32,%r15),\savearea # move %r12-%r15 to stack
178 stg %r12,__SF_BACKCHAIN(%r15)
181 .macro RESTORE_ALL psworg,sync
182 mvc \psworg(16),SP_PSW(%r15) # move user PSW to lowcore
184 ni \psworg+1,0xfd # clear wait state bit
186 lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15 of user
187 STORE_TIMER __LC_EXIT_TIMER
188 lpswe \psworg # back to caller
192 * Scheduler resume function, called by switch_to
193 * gpr2 = (task_struct *) prev
194 * gpr3 = (task_struct *) next
200 tm __THREAD_per+4(%r3),0xe8 # is the new process using per ?
201 jz __switch_to_noper # if not we're fine
202 stctg %c9,%c11,__SF_EMPTY(%r15)# We are using per stuff
203 clc __THREAD_per(24,%r3),__SF_EMPTY(%r15)
204 je __switch_to_noper # we got away without bashing TLB's
205 lctlg %c9,%c11,__THREAD_per(%r3) # Nope we didn't
207 lg %r4,__THREAD_info(%r2) # get thread_info of prev
208 tm __TI_flags+7(%r4),_TIF_MCCK_PENDING # machine check pending?
209 jz __switch_to_no_mcck
210 ni __TI_flags+7(%r4),255-_TIF_MCCK_PENDING # clear flag in prev
211 lg %r4,__THREAD_info(%r3) # get thread_info of next
212 oi __TI_flags+7(%r4),_TIF_MCCK_PENDING # set it in next
214 stmg %r6,%r15,__SF_GPRS(%r15)# store __switch_to registers of prev task
215 stg %r15,__THREAD_ksp(%r2) # store kernel stack to prev->tss.ksp
216 lg %r15,__THREAD_ksp(%r3) # load kernel stack from next->tss.ksp
217 lmg %r6,%r15,__SF_GPRS(%r15)# load __switch_to registers of next task
218 stg %r3,__LC_CURRENT # __LC_CURRENT = current task struct
219 lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4
220 lg %r3,__THREAD_info(%r3) # load thread_info from task struct
221 stg %r3,__LC_THREAD_INFO
223 stg %r3,__LC_KERNEL_STACK # __LC_KERNEL_STACK = new kernel stack
228 * SVC interrupt handler routine. System calls are synchronous events and
229 * are executed with interrupts enabled.
234 STORE_TIMER __LC_SYNC_ENTER_TIMER
236 SAVE_ALL_BASE __LC_SAVE_AREA
237 SAVE_ALL_SVC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
238 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
239 llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
240 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
242 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
244 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
246 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
249 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
250 slag %r7,%r7,2 # *4 and test for svc 0
252 # svc 0: system call number in %r1
253 cl %r1,BASED(.Lnr_syscalls)
255 lgfr %r7,%r1 # clear high word in r1
256 slag %r7,%r7,2 # svc 0: system call number in %r1
258 mvc SP_ARGS(8,%r15),SP_R7(%r15)
260 larl %r10,sys_call_table
262 tm __TI_flags+5(%r9),(_TIF_31BIT>>16) # running in 31 bit mode ?
264 larl %r10,sys_call_table_emu # use 31 bit emulation system calls
267 tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)
268 lgf %r8,0(%r7,%r10) # load address of system call routine
270 basr %r14,%r8 # call sys_xxxx
271 stg %r2,SP_R2(%r15) # store return value (change R2 on stack)
274 tm __TI_flags+7(%r9),_TIF_WORK_SVC
275 jnz sysc_work # there is work to do (signals etc.)
277 #ifdef CONFIG_TRACE_IRQFLAGS
278 larl %r1,sysc_restore_trace_psw
285 RESTORE_ALL __LC_RETURN_PSW,1
288 #ifdef CONFIG_TRACE_IRQFLAGS
290 .globl sysc_restore_trace_psw
291 sysc_restore_trace_psw:
292 .quad 0, sysc_restore_trace
296 # recheck if there is more work to do
299 tm __TI_flags+7(%r9),_TIF_WORK_SVC
300 jz sysc_restore # there is no work to do
302 # One of the work bits is on. Find out which one.
305 tm SP_PSW+1(%r15),0x01 # returning to user ?
307 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
309 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
311 tm __TI_flags+7(%r9),_TIF_SIGPENDING
313 tm __TI_flags+7(%r9),_TIF_RESTART_SVC
315 tm __TI_flags+7(%r9),_TIF_SINGLE_STEP
321 # _TIF_NEED_RESCHED is set, call schedule
324 larl %r14,sysc_work_loop
325 jg schedule # return point is sysc_return
328 # _TIF_MCCK_PENDING is set, call handler
331 larl %r14,sysc_work_loop
332 jg s390_handle_mcck # TIF bit will be cleared by handler
335 # _TIF_SIGPENDING is set, call do_signal
338 ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
339 la %r2,SP_PTREGS(%r15) # load pt_regs
340 brasl %r14,do_signal # call do_signal
341 tm __TI_flags+7(%r9),_TIF_RESTART_SVC
343 tm __TI_flags+7(%r9),_TIF_SINGLE_STEP
348 # _TIF_RESTART_SVC is set, set up registers and restart svc
351 ni __TI_flags+7(%r9),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC
352 lg %r7,SP_R2(%r15) # load new svc number
354 mvc SP_R2(8,%r15),SP_ORIG_R2(%r15) # restore first argument
355 lmg %r2,%r6,SP_R2(%r15) # load svc arguments
356 j sysc_do_restart # restart svc
359 # _TIF_SINGLE_STEP is set, call do_single_step
362 ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
363 lhi %r0,__LC_PGM_OLD_PSW
364 sth %r0,SP_TRAP(%r15) # set trap indication to pgm check
365 la %r2,SP_PTREGS(%r15) # address of register-save area
366 larl %r14,sysc_return # load adr. of system return
367 jg do_single_step # branch to do_sigtrap
370 # call syscall_trace before and after system call
371 # special linkage: %r12 contains the return address for trace_svc
374 la %r2,SP_PTREGS(%r15) # load pt_regs
378 brasl %r14,syscall_trace
382 lg %r7,SP_R2(%r15) # strace might have changed the
383 sll %r7,2 # system call
386 lmg %r3,%r6,SP_R3(%r15)
387 lg %r2,SP_ORIG_R2(%r15)
388 basr %r14,%r8 # call sys_xxx
389 stg %r2,SP_R2(%r15) # store return value
391 tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)
393 la %r2,SP_PTREGS(%r15) # load pt_regs
395 larl %r14,sysc_return # return point is sysc_return
399 # a new process exits the kernel with ret_from_fork
403 lg %r13,__LC_SVC_NEW_PSW+8
404 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
405 tm SP_PSW+1(%r15),0x01 # forking a kernel thread ?
407 stg %r15,SP_R15(%r15) # store stack pointer for new kthread
408 0: brasl %r14,schedule_tail
410 stosm 24(%r15),0x03 # reenable interrupts
414 # kernel_execve function needs to deal with pt_regs that is not
419 stmg %r12,%r15,96(%r15)
422 stg %r14,__SF_BACKCHAIN(%r15)
423 la %r12,SP_PTREGS(%r15)
424 xc 0(__PT_SIZE,%r12),0(%r12)
430 lmg %r12,%r15,96(%r15)
433 0: stnsm __SF_EMPTY(%r15),0xfc # disable interrupts
434 lg %r15,__LC_KERNEL_STACK # load ksp
435 aghi %r15,-SP_SIZE # make room for registers & psw
436 lg %r13,__LC_SVC_NEW_PSW+8
437 lg %r9,__LC_THREAD_INFO
438 mvc SP_PTREGS(__PT_SIZE,%r15),0(%r12) # copy pt_regs
439 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
440 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
441 brasl %r14,execve_tail
445 * Program check handler routine
448 .globl pgm_check_handler
451 * First we need to check for a special case:
452 * Single stepping an instruction that disables the PER event mask will
453 * cause a PER event AFTER the mask has been set. Example: SVC or LPSW.
454 * For a single stepped SVC the program check handler gets control after
455 * the SVC new PSW has been loaded. But we want to execute the SVC first and
456 * then handle the PER event. Therefore we update the SVC old PSW to point
457 * to the pgm_check_handler and branch to the SVC handler after we checked
458 * if we have to load the kernel stack register.
459 * For every other possible cause for PER event without the PER mask set
460 * we just ignore the PER event (FIXME: is there anything we have to do
463 STORE_TIMER __LC_SYNC_ENTER_TIMER
464 SAVE_ALL_BASE __LC_SAVE_AREA
465 tm __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception
466 jnz pgm_per # got per exception -> special case
467 SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA
468 CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA
469 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
470 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
472 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
473 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
474 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
477 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
478 mvc SP_ARGS(8,%r15),__LC_LAST_BREAK
480 lgf %r3,__LC_PGM_ILC # load program interruption code
485 larl %r1,pgm_check_table
486 lg %r1,0(%r8,%r1) # load address of handler routine
487 la %r2,SP_PTREGS(%r15) # address of register-save area
488 larl %r14,sysc_return
489 br %r1 # branch to interrupt-handler
492 # handle per exception
495 tm __LC_PGM_OLD_PSW,0x40 # test if per event recording is on
496 jnz pgm_per_std # ok, normal per event from user space
497 # ok its one of the special cases, now we need to find out which one
498 clc __LC_PGM_OLD_PSW(16),__LC_SVC_NEW_PSW
500 # no interesting special case, ignore PER event
501 lmg %r12,%r15,__LC_SAVE_AREA
502 lpswe __LC_PGM_OLD_PSW
505 # Normal per exception
508 SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA
509 CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA
510 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
511 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
513 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
514 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
515 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
518 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
520 lg %r1,__TI_task(%r9)
521 tm SP_PSW+1(%r15),0x01 # kernel per event ?
523 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
524 mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
525 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
526 oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
527 lgf %r3,__LC_PGM_ILC # load program interruption code
529 ngr %r8,%r3 # clear per-event-bit and ilc
534 # it was a single stepped SVC that is causing all the trouble
537 SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
538 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
539 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
540 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
541 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
542 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
544 llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
545 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
546 lg %r1,__TI_task(%r9)
547 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
548 mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
549 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
550 oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
552 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
556 # per was called from kernel, must be kprobes
559 lhi %r0,__LC_PGM_OLD_PSW
560 sth %r0,SP_TRAP(%r15) # set trap indication to pgm check
561 la %r2,SP_PTREGS(%r15) # address of register-save area
562 larl %r14,sysc_restore # load adr. of system ret, no work
563 jg do_single_step # branch to do_single_step
566 * IO interrupt handler routine
568 .globl io_int_handler
570 STORE_TIMER __LC_ASYNC_ENTER_TIMER
572 SAVE_ALL_BASE __LC_SAVE_AREA+32
573 SAVE_ALL_ASYNC __LC_IO_OLD_PSW,__LC_SAVE_AREA+32
574 CREATE_STACK_FRAME __LC_IO_OLD_PSW,__LC_SAVE_AREA+32
575 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
576 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
578 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
579 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
580 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
583 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
585 la %r2,SP_PTREGS(%r15) # address of register-save area
586 brasl %r14,do_IRQ # call standard irq handler
588 tm __TI_flags+7(%r9),_TIF_WORK_INT
589 jnz io_work # there is work to do (signals etc.)
591 #ifdef CONFIG_TRACE_IRQFLAGS
592 larl %r1,io_restore_trace_psw
599 RESTORE_ALL __LC_RETURN_PSW,0
602 #ifdef CONFIG_TRACE_IRQFLAGS
604 .globl io_restore_trace_psw
605 io_restore_trace_psw:
606 .quad 0, io_restore_trace
610 # There is work todo, we need to check if we return to userspace, then
611 # check, if we are in SIE, if yes leave it
614 tm SP_PSW+1(%r15),0x01 # returning to user ?
615 #ifndef CONFIG_PREEMPT
616 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
617 jnz io_work_user # yes -> no need to check for SIE
618 la %r1, BASED(sie_opcode) # we return to kernel here
619 lg %r2, SP_PSW+8(%r15)
620 clc 0(2,%r1), 0(%r2) # is current instruction = SIE?
621 jne io_restore # no-> return to kernel
622 lg %r1, SP_PSW+8(%r15) # yes-> add 4 bytes to leave SIE
624 stg %r1, SP_PSW+8(%r15)
625 j io_restore # return to kernel
627 jno io_restore # no-> skip resched & signal
630 jnz io_work_user # yes -> do resched & signal
631 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
632 la %r1, BASED(sie_opcode)
633 lg %r2, SP_PSW+8(%r15)
634 clc 0(2,%r1), 0(%r2) # is current instruction = SIE?
635 jne 0f # no -> leave PSW alone
636 lg %r1, SP_PSW+8(%r15) # yes-> add 4 bytes to leave SIE
638 stg %r1, SP_PSW+8(%r15)
641 # check for preemptive scheduling
642 icm %r0,15,__TI_precount(%r9)
643 jnz io_restore # preemption is disabled
644 # switch to kernel stack
647 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
648 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
651 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
653 larl %r14,io_resume_loop
654 jg preempt_schedule_irq
658 lg %r1,__LC_KERNEL_STACK
660 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
661 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
664 # One of the work bits is on. Find out which one.
665 # Checked are: _TIF_SIGPENDING, _TIF_RESTORE_SIGPENDING, _TIF_NEED_RESCHED
666 # and _TIF_MCCK_PENDING
669 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
671 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
673 tm __TI_flags+7(%r9),_TIF_SIGPENDING
678 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
684 # _TIF_MCCK_PENDING is set, call handler
687 brasl %r14,s390_handle_mcck # TIF bit will be cleared by handler
691 # _TIF_NEED_RESCHED is set, call schedule
695 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
696 brasl %r14,schedule # call scheduler
697 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
699 tm __TI_flags+7(%r9),_TIF_WORK_INT
700 jz io_restore # there is no work to do
704 # _TIF_SIGPENDING or is set, call do_signal
708 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
709 la %r2,SP_PTREGS(%r15) # load pt_regs
710 brasl %r14,do_signal # call do_signal
711 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
716 * External interrupt handler routine
718 .globl ext_int_handler
720 STORE_TIMER __LC_ASYNC_ENTER_TIMER
722 SAVE_ALL_BASE __LC_SAVE_AREA+32
723 SAVE_ALL_ASYNC __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32
724 CREATE_STACK_FRAME __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32
725 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
726 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
728 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
729 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
730 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
733 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
735 la %r2,SP_PTREGS(%r15) # address of register-save area
736 llgh %r3,__LC_EXT_INT_CODE # get interruption code
743 * Machine check handler routines
745 .globl mcck_int_handler
747 la %r1,4095 # revalidate r1
748 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # revalidate cpu timer
749 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs
750 SAVE_ALL_BASE __LC_SAVE_AREA+64
751 la %r12,__LC_MCK_OLD_PSW
752 tm __LC_MCCK_CODE,0x80 # system damage?
753 jo mcck_int_main # yes -> rest of mcck code invalid
754 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
756 mvc __LC_SAVE_AREA+104(8),__LC_ASYNC_ENTER_TIMER
757 mvc __LC_ASYNC_ENTER_TIMER(8),__LC_CPU_TIMER_SAVE_AREA-4095(%r14)
758 tm __LC_MCCK_CODE+5,0x02 # stored cpu timer value valid?
760 la %r14,__LC_SYNC_ENTER_TIMER
761 clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER
763 la %r14,__LC_ASYNC_ENTER_TIMER
764 0: clc 0(8,%r14),__LC_EXIT_TIMER
766 la %r14,__LC_EXIT_TIMER
767 0: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
769 la %r14,__LC_LAST_UPDATE_TIMER
771 mvc __LC_ASYNC_ENTER_TIMER(8),0(%r14)
774 tm __LC_MCCK_CODE+2,0x09 # mwp + ia of old psw valid?
775 jno mcck_int_main # no -> skip cleanup critical
776 tm __LC_MCK_OLD_PSW+1,0x01 # test problem state bit
777 jnz mcck_int_main # from user -> load kernel stack
778 clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_end)
780 clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_start)
782 brasl %r14,cleanup_critical
784 lg %r14,__LC_PANIC_STACK # are we already on the panic stack?
786 srag %r14,%r14,PAGE_SHIFT
788 lg %r15,__LC_PANIC_STACK # load panic stack
789 0: CREATE_STACK_FRAME __LC_MCK_OLD_PSW,__LC_SAVE_AREA+64
790 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
791 tm __LC_MCCK_CODE+2,0x08 # mwp of old psw valid?
792 jno mcck_no_vtime # no -> no timer update
793 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
795 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
796 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
797 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
800 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
801 la %r2,SP_PTREGS(%r15) # load pt_regs
802 brasl %r14,s390_do_machine_check
803 tm SP_PSW+1(%r15),0x01 # returning to user ?
805 lg %r1,__LC_KERNEL_STACK # switch to kernel stack
807 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
808 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
810 stosm __SF_EMPTY(%r15),0x04 # turn dat on
811 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
814 brasl %r14,s390_handle_mcck
817 mvc __LC_RETURN_MCCK_PSW(16),SP_PSW(%r15) # move return PSW
818 ni __LC_RETURN_MCCK_PSW+1,0xfd # clear wait state bit
819 lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15
820 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
821 mvc __LC_ASYNC_ENTER_TIMER(8),__LC_SAVE_AREA+104
822 tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
827 lpswe __LC_RETURN_MCCK_PSW # back to caller
830 * Restart interruption handler, kick starter for additional CPUs
834 .globl restart_int_handler
836 lg %r15,__LC_SAVE_AREA+120 # load ksp
837 lghi %r10,__LC_CREGS_SAVE_AREA
838 lctlg %c0,%c15,0(%r10) # get new ctl regs
839 lghi %r10,__LC_AREGS_SAVE_AREA
841 lmg %r6,%r15,__SF_GPRS(%r15) # load registers from clone
842 stosm __SF_EMPTY(%r15),0x04 # now we can turn dat on
847 * If we do not run with SMP enabled, let the new CPU crash ...
849 .globl restart_int_handler
853 lpswe restart_crash-restart_base(%r1)
856 .long 0x000a0000,0x00000000,0x00000000,0x00000000
860 #ifdef CONFIG_CHECK_STACK
862 * The synchronous or the asynchronous stack overflowed. We are dead.
863 * No need to properly save the registers, we are going to panic anyway.
864 * Setup a pt_regs so that show_trace can provide a good call trace.
867 lg %r15,__LC_PANIC_STACK # change to panic stack
869 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
870 stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack
871 la %r1,__LC_SAVE_AREA
872 chi %r12,__LC_SVC_OLD_PSW
874 chi %r12,__LC_PGM_OLD_PSW
876 la %r1,__LC_SAVE_AREA+32
877 0: mvc SP_R12(32,%r15),0(%r1) # move %r12-%r15 to stack
878 mvc SP_ARGS(8,%r15),__LC_LAST_BREAK
879 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) # clear back chain
880 la %r2,SP_PTREGS(%r15) # load pt_regs
881 jg kernel_stack_overflow
884 cleanup_table_system_call:
885 .quad system_call, sysc_do_svc
886 cleanup_table_sysc_return:
887 .quad sysc_return, sysc_leave
888 cleanup_table_sysc_leave:
889 .quad sysc_leave, sysc_done
890 cleanup_table_sysc_work_loop:
891 .quad sysc_work_loop, sysc_work_done
892 cleanup_table_io_return:
893 .quad io_return, io_leave
894 cleanup_table_io_leave:
895 .quad io_leave, io_done
896 cleanup_table_io_work_loop:
897 .quad io_work_loop, io_work_done
900 clc 8(8,%r12),BASED(cleanup_table_system_call)
902 clc 8(8,%r12),BASED(cleanup_table_system_call+8)
903 jl cleanup_system_call
905 clc 8(8,%r12),BASED(cleanup_table_sysc_return)
907 clc 8(8,%r12),BASED(cleanup_table_sysc_return+8)
908 jl cleanup_sysc_return
910 clc 8(8,%r12),BASED(cleanup_table_sysc_leave)
912 clc 8(8,%r12),BASED(cleanup_table_sysc_leave+8)
913 jl cleanup_sysc_leave
915 clc 8(8,%r12),BASED(cleanup_table_sysc_work_loop)
917 clc 8(8,%r12),BASED(cleanup_table_sysc_work_loop+8)
918 jl cleanup_sysc_return
920 clc 8(8,%r12),BASED(cleanup_table_io_return)
922 clc 8(8,%r12),BASED(cleanup_table_io_return+8)
925 clc 8(8,%r12),BASED(cleanup_table_io_leave)
927 clc 8(8,%r12),BASED(cleanup_table_io_leave+8)
930 clc 8(8,%r12),BASED(cleanup_table_io_work_loop)
932 clc 8(8,%r12),BASED(cleanup_table_io_work_loop+8)
938 mvc __LC_RETURN_PSW(16),0(%r12)
939 cghi %r12,__LC_MCK_OLD_PSW
941 la %r12,__LC_SAVE_AREA+32
943 0: la %r12,__LC_SAVE_AREA+64
945 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
946 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+8)
948 mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
949 0: clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+16)
952 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn)
954 mvc __LC_SAVE_AREA(32),0(%r12)
956 stg %r12,__LC_SAVE_AREA+96 # argh
957 SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
958 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
959 lg %r12,__LC_SAVE_AREA+96 # argh
961 llgh %r7,__LC_SVC_INT_CODE
962 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
964 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+24)
966 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
968 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+32)
970 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
972 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
974 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_system_call+8)
975 la %r12,__LC_RETURN_PSW
977 cleanup_system_call_insn:
979 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
987 mvc __LC_RETURN_PSW(8),0(%r12)
988 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_sysc_return)
989 la %r12,__LC_RETURN_PSW
993 clc 8(8,%r12),BASED(cleanup_sysc_leave_insn)
995 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
996 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
997 clc 8(8,%r12),BASED(cleanup_sysc_leave_insn+8)
1000 mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
1001 cghi %r12,__LC_MCK_OLD_PSW
1003 mvc __LC_SAVE_AREA+64(32),SP_R12(%r15)
1005 0: mvc __LC_SAVE_AREA+32(32),SP_R12(%r15)
1006 1: lmg %r0,%r11,SP_R0(%r15)
1007 lg %r15,SP_R15(%r15)
1008 2: la %r12,__LC_RETURN_PSW
1010 cleanup_sysc_leave_insn:
1012 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
1017 mvc __LC_RETURN_PSW(8),0(%r12)
1018 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_io_work_loop)
1019 la %r12,__LC_RETURN_PSW
1023 clc 8(8,%r12),BASED(cleanup_io_leave_insn)
1025 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
1026 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
1027 clc 8(8,%r12),BASED(cleanup_io_leave_insn+8)
1030 mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
1031 cghi %r12,__LC_MCK_OLD_PSW
1033 mvc __LC_SAVE_AREA+64(32),SP_R12(%r15)
1035 0: mvc __LC_SAVE_AREA+32(32),SP_R12(%r15)
1036 1: lmg %r0,%r11,SP_R0(%r15)
1037 lg %r15,SP_R15(%r15)
1038 2: la %r12,__LC_RETURN_PSW
1040 cleanup_io_leave_insn:
1042 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
1051 .Lnr_syscalls: .long NR_syscalls
1052 .L0x0130: .short 0x130
1053 .L0x0140: .short 0x140
1054 .L0x0150: .short 0x150
1055 .L0x0160: .short 0x160
1056 .L0x0170: .short 0x170
1058 .quad __critical_start
1060 .quad __critical_end
1062 .section .rodata, "a"
1063 #define SYSCALL(esa,esame,emu) .long esame
1065 #include "syscalls.S"
1068 #ifdef CONFIG_COMPAT
1070 #define SYSCALL(esa,esame,emu) .long emu
1072 #include "syscalls.S"