2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 * Interrupt exception dispatch code.
22 #include <asm/mipsregs.h>
23 #include <asm/regdef.h>
24 #include <asm/stackframe.h>
26 /* A lot of complication here is taken away because:
28 * 1) We handle one interrupt and return, sitting in a loop and moving across
29 * all the pending IRQ bits in the cause register is _NOT_ the answer, the
30 * common case is one pending IRQ so optimize in that direction.
32 * 2) We need not check against bits in the status register IRQ mask, that
33 * would make this routine slow as hell.
35 * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
36 * between like BSD spl() brain-damage.
38 * Furthermore, the IRQs on the MIPS board look basically (barring software
39 * IRQs which we don't use at all and all external interrupt sources are
40 * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
44 * 0 Software (ignored)
45 * 1 Software (ignored)
46 * 2 Combined hardware interrupt (hw0)
47 * 3 Hardware (ignored)
48 * 4 Hardware (ignored)
49 * 5 Hardware (ignored)
50 * 6 Hardware (ignored)
51 * 7 R4k timer (what we use)
53 * Note: On the SEAD board thing are a little bit different.
54 * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
57 * We handle the IRQ according to _our_ priority which is:
59 * Highest ---- R4k Timer
60 * Lowest ---- Combined hardware interrupt
62 * then we just return, if multiple IRQs are pending then we will just take
63 * another exception, big deal.
70 NESTED(mipsIRQ, PT_SIZE, sp)
75 mfc0 s0, CP0_CAUSE # get irq bits
76 mfc0 s1, CP0_STATUS # get irq mask
79 /* First we check for r4k counter/timer IRQ. */
80 andi a0, s0, CAUSEF_IP7
82 andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt
84 /* Wheee, a timer interrupt. */
86 jal mips_timer_interrupt
93 #if defined(CONFIG_MIPS_SEAD)
95 andi a0, s0, CAUSEF_IP3 # delay slot, check hw1 interrupt
97 beq a0, zero, 1f # delay slot, check hw3 interrupt
98 andi a0, s0, CAUSEF_IP5
101 /* Wheee, combined hardware level zero interrupt. */
102 #if defined(CONFIG_MIPS_ATLAS)
103 jal atlas_hw0_irqdispatch
104 #elif defined(CONFIG_MIPS_MALTA)
105 jal malta_hw0_irqdispatch
106 #elif defined(CONFIG_MIPS_SEAD)
107 jal sead_hw0_irqdispatch
109 #error "MIPS board not supported\n"
111 move a0, sp # delay slot
117 #if defined(CONFIG_MIPS_SEAD)
119 andi a0, s0, CAUSEF_IP5 # delay slot, check hw3 interrupt
120 jal sead_hw1_irqdispatch
121 move a0, sp # delay slot
126 #if defined(CONFIG_MIPS_MALTA)
127 beq a0, zero, 1f # check hw3 (coreHI) interrupt
129 jal corehi_irqdispatch
136 * Here by mistake? This is possible, what can happen is that by the
137 * time we take the exception the IRQ pin goes low, so just leave if
141 PRINT("Got interrupt: c0_cause = %08x\n")
143 PRINT("c0_epc = %08x\n")