4 * Copyright (C) 2007 Markus Brunner, Mark Jonas
5 * Copyright (C) 2009 Paul Mundt
7 * Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c:
9 * Copyright (C) 2006 Paul Mundt
10 * Copyright (C) 2006 Jamie Lenehan
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
16 #include <linux/platform_device.h>
17 #include <linux/init.h>
18 #include <linux/serial.h>
20 #include <linux/serial_sci.h>
21 #include <linux/sh_timer.h>
24 static struct resource rtc_resources[] = {
27 .end = 0xa413fec0 + 0x28 - 1,
28 .flags = IORESOURCE_IO,
31 /* Shared Period/Carry/Alarm IRQ */
33 .flags = IORESOURCE_IRQ,
37 static struct sh_rtc_platform_info rtc_info = {
38 .capabilities = RTC_CAP_4_DIGIT_YEAR,
41 static struct platform_device rtc_device = {
44 .num_resources = ARRAY_SIZE(rtc_resources),
45 .resource = rtc_resources,
47 .platform_data = &rtc_info,
51 static struct plat_sci_port sci_platform_data[] = {
53 .mapbase = 0xa4430000,
54 .flags = UPF_BOOT_AUTOCONF,
56 .irqs = { 80, 80, 80, 80 },
58 .mapbase = 0xa4438000,
59 .flags = UPF_BOOT_AUTOCONF,
61 .irqs = { 81, 81, 81, 81 },
68 static struct platform_device sci_device = {
72 .platform_data = sci_platform_data,
76 static struct resource usb_ohci_resources[] = {
80 .flags = IORESOURCE_MEM,
85 .flags = IORESOURCE_IRQ,
89 static u64 usb_ohci_dma_mask = 0xffffffffUL;
90 static struct platform_device usb_ohci_device = {
94 .dma_mask = &usb_ohci_dma_mask,
95 .coherent_dma_mask = 0xffffffff,
97 .num_resources = ARRAY_SIZE(usb_ohci_resources),
98 .resource = usb_ohci_resources,
101 static struct resource usbf_resources[] = {
106 .flags = IORESOURCE_MEM,
112 .flags = IORESOURCE_IRQ,
116 static struct platform_device usbf_device = {
121 .coherent_dma_mask = 0xffffffff,
123 .num_resources = ARRAY_SIZE(usbf_resources),
124 .resource = usbf_resources,
127 static struct sh_timer_config cmt0_platform_data = {
129 .channel_offset = 0x10,
131 .clk = "peripheral_clk",
132 .clockevent_rating = 125,
133 .clocksource_rating = 125,
136 static struct resource cmt0_resources[] = {
141 .flags = IORESOURCE_MEM,
145 .flags = IORESOURCE_IRQ,
149 static struct platform_device cmt0_device = {
153 .platform_data = &cmt0_platform_data,
155 .resource = cmt0_resources,
156 .num_resources = ARRAY_SIZE(cmt0_resources),
159 static struct sh_timer_config cmt1_platform_data = {
161 .channel_offset = 0x20,
163 .clk = "peripheral_clk",
166 static struct resource cmt1_resources[] = {
171 .flags = IORESOURCE_MEM,
175 .flags = IORESOURCE_IRQ,
179 static struct platform_device cmt1_device = {
183 .platform_data = &cmt1_platform_data,
185 .resource = cmt1_resources,
186 .num_resources = ARRAY_SIZE(cmt1_resources),
189 static struct sh_timer_config cmt2_platform_data = {
191 .channel_offset = 0x30,
193 .clk = "peripheral_clk",
196 static struct resource cmt2_resources[] = {
201 .flags = IORESOURCE_MEM,
205 .flags = IORESOURCE_IRQ,
209 static struct platform_device cmt2_device = {
213 .platform_data = &cmt2_platform_data,
215 .resource = cmt2_resources,
216 .num_resources = ARRAY_SIZE(cmt2_resources),
219 static struct sh_timer_config cmt3_platform_data = {
221 .channel_offset = 0x40,
223 .clk = "peripheral_clk",
226 static struct resource cmt3_resources[] = {
231 .flags = IORESOURCE_MEM,
235 .flags = IORESOURCE_IRQ,
239 static struct platform_device cmt3_device = {
243 .platform_data = &cmt3_platform_data,
245 .resource = cmt3_resources,
246 .num_resources = ARRAY_SIZE(cmt3_resources),
249 static struct sh_timer_config cmt4_platform_data = {
251 .channel_offset = 0x50,
253 .clk = "peripheral_clk",
256 static struct resource cmt4_resources[] = {
261 .flags = IORESOURCE_MEM,
265 .flags = IORESOURCE_IRQ,
269 static struct platform_device cmt4_device = {
273 .platform_data = &cmt4_platform_data,
275 .resource = cmt4_resources,
276 .num_resources = ARRAY_SIZE(cmt4_resources),
279 static struct sh_timer_config tmu0_platform_data = {
281 .channel_offset = 0x02,
283 .clk = "peripheral_clk",
284 .clockevent_rating = 200,
287 static struct resource tmu0_resources[] = {
292 .flags = IORESOURCE_MEM,
296 .flags = IORESOURCE_IRQ,
300 static struct platform_device tmu0_device = {
304 .platform_data = &tmu0_platform_data,
306 .resource = tmu0_resources,
307 .num_resources = ARRAY_SIZE(tmu0_resources),
310 static struct sh_timer_config tmu1_platform_data = {
312 .channel_offset = 0xe,
314 .clk = "peripheral_clk",
315 .clocksource_rating = 200,
318 static struct resource tmu1_resources[] = {
323 .flags = IORESOURCE_MEM,
327 .flags = IORESOURCE_IRQ,
331 static struct platform_device tmu1_device = {
335 .platform_data = &tmu1_platform_data,
337 .resource = tmu1_resources,
338 .num_resources = ARRAY_SIZE(tmu1_resources),
341 static struct sh_timer_config tmu2_platform_data = {
343 .channel_offset = 0x1a,
345 .clk = "peripheral_clk",
348 static struct resource tmu2_resources[] = {
353 .flags = IORESOURCE_MEM,
357 .flags = IORESOURCE_IRQ,
361 static struct platform_device tmu2_device = {
365 .platform_data = &tmu2_platform_data,
367 .resource = tmu2_resources,
368 .num_resources = ARRAY_SIZE(tmu2_resources),
371 static struct platform_device *sh7720_devices[] __initdata = {
386 static int __init sh7720_devices_setup(void)
388 return platform_add_devices(sh7720_devices,
389 ARRAY_SIZE(sh7720_devices));
391 __initcall(sh7720_devices_setup);
393 static struct platform_device *sh7720_early_devices[] __initdata = {
404 void __init plat_early_device_setup(void)
406 early_platform_add_devices(sh7720_early_devices,
407 ARRAY_SIZE(sh7720_early_devices));
413 /* interrupt sources */
414 TMU0, TMU1, TMU2, RTC,
416 IRQ0, IRQ1, IRQ2, IRQ3,
417 USBF_SPD, TMU_SUNI, IRQ5, IRQ4,
419 ADC, DMAC2, USBFI, CMT,
421 PINT07, PINT815, TPU, IIC,
422 SIOF0, SIOF1, MMC, PCC,
427 static struct intc_vect vectors[] __initdata = {
428 /* IRQ0->5 are handled in setup-sh3.c */
429 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
430 INTC_VECT(TMU2, 0x440), INTC_VECT(RTC, 0x480),
431 INTC_VECT(RTC, 0x4a0), INTC_VECT(RTC, 0x4c0),
432 INTC_VECT(SIM, 0x4e0), INTC_VECT(SIM, 0x500),
433 INTC_VECT(SIM, 0x520), INTC_VECT(SIM, 0x540),
434 INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580),
435 /* H_UDI cannot be masked */ INTC_VECT(TMU_SUNI, 0x6c0),
436 INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1, 0x800),
437 INTC_VECT(DMAC1, 0x820), INTC_VECT(DMAC1, 0x840),
438 INTC_VECT(DMAC1, 0x860), INTC_VECT(LCDC, 0x900),
439 #if defined(CONFIG_CPU_SUBTYPE_SH7720)
440 INTC_VECT(SSL, 0x980),
442 INTC_VECT(USBFI, 0xa20), INTC_VECT(USBFI, 0xa40),
443 INTC_VECT(USBHI, 0xa60),
444 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0),
445 INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00),
446 INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80),
447 INTC_VECT(PINT815, 0xca0), INTC_VECT(SIOF0, 0xd00),
448 INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU, 0xd80),
449 INTC_VECT(TPU, 0xda0), INTC_VECT(TPU, 0xdc0),
450 INTC_VECT(TPU, 0xde0), INTC_VECT(IIC, 0xe00),
451 INTC_VECT(MMC, 0xe80), INTC_VECT(MMC, 0xea0),
452 INTC_VECT(MMC, 0xec0), INTC_VECT(MMC, 0xee0),
453 INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60),
454 INTC_VECT(AFEIF, 0xfe0),
457 static struct intc_prio_reg prio_registers[] __initdata = {
458 { 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
459 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
460 { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
461 { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } },
462 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },
463 { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } },
464 { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } },
465 { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } },
466 { 0xA4080006UL, 0, 16, 4, /* IPRI */ { SIOF0, SIOF1, MMC, PCC } },
467 { 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } },
470 static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, NULL,
471 NULL, prio_registers, NULL);
473 void __init plat_irq_setup(void)
475 register_intc_controller(&intc_desc);
476 plat_irq_setup_sh3();